CMOS Cell Array With Transistor Isolation

1. Field of the Invention

The present invention relates to a technique for forming custom logic integrated circuits utilizing CMOS cell arrays and, more particularly, to the utilization of a transistor isolation technique, in lieu of field oxide isolation, to combine the advantages of the gate array and standard cell design processes.

2. Description of the Prior Art

In designing custom logic circuits, which often include many thousands of separate devices, automated design and layout techniques must be utilized which provide quick turnaround time to avoid spending many valuable hours attempting to manually produce a workable and efficient logic circuit design. There are two popular approaches in the prior art to providing this quick turnaround, standard cell (polycell) design and gate array design.

Integrated circuits designed with polycells, or pre-characterized groups of transistors capable of performing a specific function, offer a great deal of flexibility in terms of final circuit function. One such design arrangement is discussed in the article "16b CPU Design by a Hierarchical Polycell Approach" by T. Tokuda et al, appearing in the Proceedings of the IEEE International Conference on Circuits and Components (ICCC 82), Sept. 28-Oct. 1, 1982, at pp. 102-5. The standard cell approach offers a rich library of functions, or precharacterized cells, allowing the designer to create virtually any logic circuit desired. A drawback of this approach, however, is that since each polycell definition contains all of the mask level for the entire logic circuit and it is impossible to predict where the various geometries on the different mask levels will finally be placed, it is necessary to respecify all mask levels for each new circuit and accordingly have to wait for all these levels to be processed for initial circuit evaluation. It is not unusual for a custom logic circuit to require ten or more mask levels, thus requiring an extended processing interval.

The gate array concept of circuit design addresses this long processing turnaround problem by having, on partially preprocessed wafers, predefined circuit elements which are isolated from one another by a thick oxide region and only require interconnection processing steps to form the completed circuit. Hence, in this case a designer needs only to specify the interconnection of these preplaced transistors or groups of transistors to implement a given LSI circuit design. As the transistor placement is known, silicon wafers containing these transistors can be preprocessed up to but excluding the interconnection mask levels. The few remaining mask levels (typically two to four levels) necessary for interconnection will then be processed to implement a specific function. A complete description of an exemplary gate array design technique can be found in the article "CMOS Gate Arrays: Design Techniques and Tradeoffs" by M. Insley et al appearing in the Proceedings of the 1982 Custom Intergrated Circuits Conference, May 17-19, 1982 at pp. 304-6. The gate array technique, however, is inherently limited to designing with partially preprocessed wafers, restricting the number of functions for the designer to chose from and thereby limiting the amount of customizing the designer may do.

One technique for increasing the customization possible with gate arrays is discussed in the article "A CMOS/SOS Gate Array with a New Customization Technique of Cutting" by N. Sasaki et al appearing in IEEE Transactions on Electron Devices, Vol. ED-29, No. 10, October 1982 at pp. 1535-1541. As discussed by the authors, customization of the silicon wiring level is realized by arbitrarily cutting the pre-defined epitaxial-silicon lines into many pieces after the fabrication of the transistors. Customization at the silicon wiring level results in higher packing density and reduction of the silicon wiring channels by a factor of two. Another problem with gate arrays, however, is that the thick field oxide regions, which separate the transistor pairs forming the basic circuit elements, occupy a large portion of the gate array structure. This factor appreciably reduces the number of actual circuit elements which may be included in the complete logic circuit. One solution to this problem is to utilize "gate isolation" in place of the field oxide regions to separate the circuits. This concept is discussed in detail in an article entitled "Gate Isolation--A Novel Basic Cell Configuration for CMOS Gate Arrays" By I. Ohkura el al appearing in Proceedings of the 1982 Custom Integrated Circuits Conference, May 17-19, 1982 at pp. 307-310. In particular, the gate isolation method proposes forming the basic CMOS cell out of a single transistor pair, where the transistor pairs are arranged in a row, closely spaced, without oxide isolation, resulting in a serial p-channel transistor chain and a serial n-channel transistor chain. A master slice gate array formed by this method is discussed in the article "A 10K Gate CMOS Gate Array with Gate Isolation Configuration" By K. Sakashita el al appearing in Proceedings of the 1983 Custom Integrated Circuits Conference, May 23-25, 1983 at pp. 14-18. A problem with this gate isolation approach, however, is that many standard cell definitions require at least two or three n- and p-channel transistor pairs and, therefore, cannot be utilized since the gate isolation standard cell contains only one transistor pair. Further, many more interconnections between cells are necessary in this configuration than are needed in custom logic circuits formed by the prior art methods discussed above.

Thus, there remains to desire to provide a method of achieving custom logic integrated circuit design which can provide quick turnaround time without the disadvantages of thick field oxide isolation or cell definition restrictions related to the above-cited methods.

The present invention relates to an improved method for achieving quick turnaround custom logic integrated circuit design by utilizing CMOS cell arrays and, more particularly, to the utilization of a transistor isolation technique, in lieu of field oxide isolation, to combine the advantages of the gate array and standard cell design processes.

It is an aspect of the present invention to provide a technique which uses both the partially preprocessed wafers of gate arrays and the flexibility and computer-aided-design (CAD) facilities of the standard cell approach.

A further aspect of the present invention is to employ transistor isolation in the standard cell to provide the preprocessing of gate arrays and allow flexibility in cell placement. This allows the wafers to be preprocessed with all the necessary diffusions, where final transistor size and placement are part of the isolation and add to the flexibility of the design.

Another aspect of the present invention is to provide a design method capable of employing all of the CAD tools already available with the standard cell approach, thereby giving the designer more options in creating a custom logic integrated circuit.

Other and further aspects of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.

Referring now to the drawings,

FIG. 1 illustrates an exemplary cell arrangement designed using the prior art standard cell technique with field oxide isolation;

FIG. 2 illustrates a cross-sectional view of the exemplary cell arrangement of FIG. 1;

FIG. 3 illustrates an exemplary cell arrangement designed utilizing the transistor isolation technique of the present invention;

FIG. 4 illustrates a cross-sectional view of the exemplary cell arrangement of FIG. 3; and

FIG. 5 illustrates a generic cell formed in accordance with the present invention before any customization has taken place.

A prior art standard cell, in CMOS technology, formed using field oxide isolation is illustrated in FIG. 1. Three cells 10, 12, and 14 are shown, separated by regions of field oxide 16 along cell boundaries 18 and 20, where in this exemplary arrangement field oxide 16 is SiO.sub.2. Cell boundaries 22 and 24, which separate cells 10 and 14 from the remaining cells (not shown) are also formed from field oxide 16. As shown, each cell comprises a separate p+ source/drain diffusion and an n+ source/drain diffusion. In particular, cell 10 comprises a p+ source/drain diffusion 30 and an n+ source/drain diffusion 32, cell 12 comprises a p+ diffusion 34 and an n+ diffusion 36, and cell 14 comprises a p+ diffusion 38 and an n+ diffusion 40.

The logic transistors included in the CMOS array are formed, as is well known in the art, by the intersection of a polysilicon mask with the separate p+ and n+ diffusions. Thus, by programming the polysilicon mask, the location and interconnection of the logic transistors can be controlled to form whatever logic circuit is desired. For example, in the arrangement illustrated in FIG. 1, cell 10 contains two logic transistor pairs 42 and 44, cell 12 contains a single logic transistor pair 46 and similarly, cell 14 contains a single logic transistor pair 48.

A cross-sectional view of this exemplary prior art arrangement is illustrated in FIG. 2. The view of FIG. 2 also illustrates an n epitaxial layer 50 and a p-tub layer 52, both of which are necessary layers in forming a CMOS logic circuit. Although it cannot be seen in this cross-sectional view, an n-tub layer may also, but does not necessarily have to, be formed on n epitaxial layer 50, concomitant with p-tub layer 52. Both the n-tub and p-tub layers are necessary in the "twin-tub" CMOS process. A complete description of this CMOS process, which is useful but not necessary for the understanding of the present invention, can be found in the article "Twin-Tub CMOS--A Technology for VLSI Circuits" by L. C. Parrillo et al appearing in International Electron Devices Meeting, Technical Digest, Dec. 8-10, 1980 at pp. 752-755. As shown in FIG. 2, field oxide 16 does not comprise a flat profile, rather the SiO.sub.2 layer forming field oxide 16 is grown to the same height as the polysilicon mask at cell boundaries 16, 18, 20, and 22. Thus, as can be seen from the above description, the processing involved in this prior art method is somewhat intricate. In particular, separate p+ and n+ source/drain diffusions are needed for each cell, which once set cannot be modified without re-doing all of the steps beyond the formation of the tub layers.

An exemplary arrangement of the same three cells 10, 12, and 14 formed using the transistor isolation technology of the present invention is illustrated in FIG. 3. As shown, FIG. 3 includes the same cells 10, 12 and 14 separated by the same cell boundaries 18, 20, 22, 24. In contrast to the prior art arrangement, however, separate p+ and n+ source/drain diffusion regions separated by field oxide are not required. Rather, a pair of thin oxide diffusion strips 60 and 62 are utilized in accordance with the present invention, where these strips comprise whatever length is necessary to include the number of cells desired. During a subsequent implant step, diffusion strip 60 is p+ doped and diffusion strip 62 is n+ doped. Thus, unlike the prior art arrangement where the separate p+ and n+ diffusion regions must be part of the customization process, these p+ and n+ diffusion strips of the present invention are "generic" layers, like n-epi layer 50, which do not vary from circuit design to circuit design, thus significantly decreasing the turnaround time associated with design and layout of custom logic integrated circuit.

In comparing FIG. 3 with prior art FIG. 1, the arrangement of cells 10, 12, and 14 in FIG. 3 contains the same logic transistor pairs 42, 44, 46, and 48 shown in FIG. 1. However, in accordance with the present invention, field oxide 16 is not used to separate cells 10, 12, and 14. Rather, the isolation is achieved by utilizing additional pairs of logic transistors that are permanently "off" in the circuit. That is, the gates of the p-channel devices are permanently tied to the positive power supply and the gates of the n-channel devices are permanently tied to the negative power supply. As shown in FIG. 3, a pair of isolation transistors 64 and 65 are positioned at cell boundary 18 between cells 10 and 12, where isolation transistor 64 is connected to the positive power supply (5 V) and isolation transistor 65 is connected to the negative power supply (0 V). In a similar manner, a pair of isolation transistors 66 and 67 are positioned at cell boundary 20 and connected to the positive and negative power supplies, respectively. Likewise, a pair of isolation transistors 68 and 69 are positioned at cell boundary 22 and a pair of isolation 70 and 71 are positioned at cell boundary 24. In accordance with the present invention, isolation transistors 68-71 are identical in form and composition to logic transistor pairs 42, 44, 46 and 48, and are, in fact, included in the logic circuit during the same processing step as the logic transistor pairs. The only difference between the two types of transistors is that those transistors which are used for isolation purposes are constructed to be permanently "off".

A cross-sectional view of this arrangement of the present invention is illustrated in FIG. 4. As shown, field oxide diffusion 16 is a flat profile layer and can be processed as one of the generic steps in forming a custom logic integrated circuit in accordance with the present invention. In this view, isolation transistors 65, 67, 69 and 71 are illustrated and coupled to ground (where in this example ground is the negative power supply), thereby achieving the separation between cells 10, 12, and 14 in n+ diffusion strip 62 to form n+ diffusion regions 32, 36 and 40.

In accordance with the present invention, therefore, at least three of the customization steps in the process of forming a custom logic IC (SIO.sub.2 field oxide, p+ source/drain diffusions, and n+ source/drain diffusions) are replaced by generic diffusion layers which can significantly decrease the turnaround time. Further, as seen by reference to FIGS. 1-4, the structure of the individual cells comprising the transistor isolated cell arrangement is identical to the structure of the cells in the prior art field oxide arrangement. Thus, the same software used to generate the standard cell library may be used in association with the techniques of the present invention, and circuits which have previously been designed using the standard cell approach can easily be processed using the transistor isolation techniques of the present invention.

FIG. 5 illustrates a generic wafer formed using the techniques of the present invention, before the inclusion of any of the customization steps necessary to produce a complete custom logic circuit. The sites for the standard cells are the predefined p- and n-well strips 60 and 62, respectively, located in the center of the wafer. The variable width cells, denoted 80 and 82 are place in strips 60 and 62 and interconnected in routing region 64 (formed of field oxide 16) between strips 60 and 62. It is to be noted that in accordance with the present invention, a particular cell may contain any number of transistor pairs since the width of the cell is only a function of the placement of the isolation transistors. This fact can, in the future, lead to the inclusion of standard cells in the CAD library which contain four, five, or more transistor pairs, greatly increasing the design options available.