US 5,519,236 AGrant
Semiconductor Memory Device Having Surrounding Gate Transistor
Issue Date:1996-05-21
•7 Claims
•15 Drawing Sheets
Abstract
A semiconductor memory device includes at least one memory cell formed on a substrate. The memory cell is constructed by a hole capacitor and a vertical transistor. The hole capacitor is formed in a hole on the substrate. The vertical transistor is formed in a semiconductor column formed in position adjacent to the hole.
Metadata
Assignee
- Kabushiki Kaisha Toshiba
Inventor
- Tohru Ozaki
Application Information
Application Number:US 2663899
Filing Date:1994-06-27
Priority Date:1993-06-28
Art Unit:253
Classifications
IPC:
H01L 27108
Field of Search:
257302;401;773;905
Patent Drawings (15 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to a semiconductor memory device having at least one memory cell including a trench capacitor and a surrounding gate transistor acting as a switching transistor of the trench capacitor.
2. Description of the Related Art
Recently, an SGT cell (Surrounding Gate Transistor Cell) having a capacitor and a transistor stacked in a vertical direction along a silicon column is proposed. The cell structure has an advantage that the element area of the memory cell can be set within one bit line contact.
However, if this type of cell structure is made with the dimensions (0.15 to 0.20 .mu.m) of 1-Gbit DRAM, the aspect ratio (height/width) of the silicon column is set to 50 to 60 (for example, the height is 9 .mu.m and the width is 0.15 .mu.m). Therefore, there occurs a possibility that the silicon column falls down and is destroyed by the stress generated in the process. Further, if the height is reduced with the width kept unchanged in order to reduce the aspect ratio, a sufficiently large capacitance cannot be obtained, and on the other hand, if the width is increased with the height kept unchanged, a sufficiently large capacitance can be obtained, but the cell area is increased.
As another structure, a memory cell structure as shown in Japanese Patent Disclosure (KOKAI) No. 63-29571 is known. In this structure, a vertical MOS transistor is formed on a trench capacitor. With this cell structure, it is possible to simultaneously attain reduction in the aspect ratio of the silicon column and formation of a capacitor of sufficiently large capacitance. However, in order to form the above cell structure, it is necessary to use the laminating technique using a laminated substrate, it is difficult to align the capacitor and the transistor with each other, and the manufacturing cost rises. Further, in this cell structure, since the channel portion of the transfer gate is set in an electrically floating state, generated holes have no place to escape, making it impossible to cut off the transistor.
Summary of the Invention
An object of this invention is to provide a semiconductor memory device which can be manufactured at low cost, prevent collapse or destruction of the silicon column by reducing the aspect ratio of the silicon column while maintaining a sufficiently large capacitance and prevent the substrate from being set into the electrically floating state.
In order to attain the above object, there is provided a semiconductor memory device comprising: a substrate having at least one trench and at least one semiconductor column formed in position adjacent to the trench; and at least one memory cell formed on the substrate, the memory cell being constructed by a trench capacitor and a vertical transistor, the trench capacitor being formed in the trench and the vertical transistor being formed in the semiconductor column.
In order to attain the above object, there is also provided a semiconductor memory device comprising: a substrate having a plurality of trenches and a plurality 10 of semiconductor columns, the trenches and the semiconductor columns being alternately arranged; a memory cell array having a plurality of memory cells formed on the substrate, each of the memory cells being constructed by a trench capacitor formed in each of the trenches and a vertical transistor, the vertical transistor being formed in semiconductor column lying adjacent to the trench capacitor; a plurality of bit line layers which are commonly connected to one of a drain and a source of the vertical transistors; and a plurality of word line layers which are each formed of two word line layer sections, the two word line layer sections put a side wall of each of the semiconductor columns.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a partial plan vie of a memory cell array according to a first embodiment of this invention;
FIG. 2A is a cross sectional view taken along the line A-A' of FIG. 1;
FIG. 2B is a cross sectional view taken along the line B-B' of FIG. 1;
FIGS. 3A, 3b are cross sectional views for illustrating the initial step of the manufacturing process of the memory cell according to the first embodiment;
FIGS. 4A, 4B are cross sectional views for illustrating the step succeeding to the step of FIGS. 3A, 3B;
FIGS. 5A, 5B are cross sectional views for illustrating the step succeeding to the step of FIGS. 4A, 4B;
FIGS. 6A, 6B are cross sectional views for illustrating the step succeeding to the step of FIGS. 5A, 5B;
FIGS. 7A, 7AB, 7C are cross sectional views for illustrating the step succeeding to the step of FIGS. 6A, 6B;
FIGS. 8A, 8B are cross sectional views for illustrating the step succeeding to the step of FIGS. 7A, 7B;
FIGS. 9A, 9B are cross sectional views for illustrating the step succeeding to the step of FIGS. 8A, 8B;
FIG. 10 is a partial plan view of a memory cell array according to a second embodiment of this invention;
FIG. 11A is a cross sectional view taken along the line A-A' of FIG. 10;
FIG. 11B is a cross sectional view taken along the line B-B' of FIG. 10;
FIG. 11C is a perspective view of the memory cell of FIG. 10;
FIGS. 12A, 12B are partial cross sectional views of a memory cell array according to a third embodiment of this invention; and
FIGS. 13A, 13B are partial cross sectional views of a memory cell array according to a fourth embodiment of this invention.
Detailed Description of the Preferred Embodiments
There will now be described an embodiment of this invention with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a partial plan view of a memory cell array of a semiconductor memory device according to a first embodiment of this invention. An area defined by chain line in FIG. 1 indicates one memory cell. In this example, the semiconductor memory device is a DRAM (Dynamic Random Access Memory) and the memory cell is a DRAM cell. A plurality of bit line layers 25 are arranged in a first direction with the width of minimum patterning dimension F at an interval of minimum patterning dimension F. A plurality of word line layers 22 are arranged in a second direction perpendicular to the first direction with the width of minimum patterning dimension F at an interval of minimum patterning dimension F. Each memory cell includes a trench capacitor and a vertical MOS transistor disposed adjacent to the trench capacitor. The trench capacitors are formed in trenches 12 which are formed in a substrate. The vertical MOS transistors are formed in a silicon column 20 as the semiconductor column of the substrate, for example. The silicon column 20 is formed in the second direction in position adjacent to the trench 12. The silicon column 20 has the height (equal to or less than 1 .mu.m) necessary for forming the vertical MOS transistor. As a result, the aspect ratio of the silicon column becomes small and collapse and destruction of the silicon column can be prevented.
A plurality of trenches 12 are discretely formed in a checkered configuration in the substrate. The opening of the trench 12 is formed with a rectangular form. One trench capacitor is formed in each of the trenches 12. The silicon columns 20 are formed adjacent to the respective trenches 12. The cross section of the silicon column 20 is made in a square form. One vertical MOS transistor is formed in each of the silicon columns 20. A plurality of silicon columns 20 and a plurality of trenches 12 are alternately arranged in each of the first and second directions. Each of the silicon columns 20 is surrounded by the adjacent four trenches 12. As a result, the vertical MOS transistor is isolated from another vertical MOS transistor.
Gate electrodes surrounding the side surfaces of the silicon column 20 are connected to word line layers 22. A drain layer formed on the top side of the silicon column 20 is connected to the bit line layer 25 via a contact hole.
The bit line layer 25 overlaps both of the trench capacitor and the adjacent vertical MOS transistor. The memory cell is disposed between the centers of the widths of the adjacent bit line layers 25. The center of the memory cell is set in alignment with the center between the adjacent bit line layers 25.
FIG. 2A is a cross sectional view taken along the line A-A' of FIG. 1. FIG. 2B is a cross sectional view taken along the line B-B' of FIG. 1. The upper portion of an n-type silicon substrate (which is hereinafter simply referred to as a substrate) 10 is converted into a p-type well 11 by diffusion of p-type impurity. Etching is effected from the surface of the p-type well 11 to the half-way portion of the substrate 10. As a result, the trenches 12 and silicon columns 20 are formed. A storage electrode 14 is buried in each of the trenches 12 with a capacitor insulation film 13 disposed therebetween. The trench capacitor is constructed by a plate electrode formed of the substrate 10, the storage electrode 14 buried in the trench 12 and the capacitor insulation film 13 disposed between the plate electrode and the storage electrode 14.
A vertical MOS transistor is formed in each of the p-type wells 11. A drain region 24 is formed in the top portion of the silicon column 20. The drain region 24 is connected to a bit line layer 25 via a bit line contact. The side surfaces of the silicon column 20 are surrounded by the word line layer 22 to form a gate region. A source region 18 is formed in the side portion of the silicon column 20 lying in position lower than the gate region. The source region 18 is connected to the storage electrode 14 via polysilicon films 16, 17. The polysilicon films 16, 17 are isolated from the p-type well 11 by a side wall insulation film 15.
Next, the manufacturing process of this embodiment is explained with reference to FIGS. 3A to 9A and 3B to 9B. FIGS. 3A to 9A are cross sectional views corresponding to the cross sectional view of FIG. 2A and FIGS. 3B to 9B are cross sectional views corresponding to the cross sectional view of FIG. 2B.
FIGS. 3A, 3B are cross sectional views for illustrating the initial step (first step) of the manufacturing process of the memory cell according to the first embodiment. The substrate 10 is etched to the depth of approx. 6 to 7 .mu.m from the surface thereof with an SiO.sub.2 film 31 and SiN film 32 used as a mask. Thus, the first trenches 12 are formed. As described before, the first trenches 12 are discretely arranged on the substrate surface in a checkered configuration and the opening thereof is made in a rectangular form. Then, p-type impurity is diffused from the surface of the substrate 10 to a depth of 2 .mu.m, for example, which is larger than the height (1 .mu.m) necessary for forming the vertical MOS transistor so as to form the p-type well 11 in the upper portion of the substrate 10.
FIGS. 4A, 4B are cross sectional views showing the second step. A polysilicon film used as the storage electrode 14 is buried in the trench 12 with the capacitor insulation film 13 disposed therebetween. The storage electrode 14 is formed to the bottom surface of the p-type well 11. Next, the insulation film 15 is formed on the side surface of the p-type well 11. Then, the polysilicon film 16 is buried on the storage electrode 14 to a position of a resist 32. The polysilicon films 14, 16 are formed by depositing polysilicon on the entire surface and then etching back the same to a preset depth.
FIGS. 5A, 5B are cross sectional views indicating the third step. The polysilicon film 16 is selectively etched with a resist 33 used as a mask. Next, the side wall insulation film 15 is removed by etching to expose part of the side surface of the p-type well 11.
FIGS. 6A, 6B are cross sectional views indicating the fourth step. A polysilicon film 17 including n-type impurities is buried in a concave portion surrounded by the exposed side surface of the p-type well 11, polysilicon film 16 and side wall insulation film 15. Next, the source region 18 is formed on one side surface of the p-type well 11 by diffusing n-type impurity from the polysilicon film 17. As a result, the source region 18 is connected to the storage electrode 14 via the polysilicon films 16, 17 and acts as a storage node contact. Next, an insulation film 19' is formed on the polysilicon films 16, 17 to a position higher than the p-type well 11.
FIGS. 7A, 7B, 7C are views indicating the fifth step. FIG. 7C is a perspective view. Second trenches 20 and silicon columns 20 with the height of 1 .mu.m or less are formed by etching the insulation film 19' and p-type wells 11 to the surface of the polysilicon films 16, 17 with the depth of approx. 0.5 to 1 .mu.m as shown in FIG. 7C. A vertical MOS transistor is formed at a SGT field of the silicon column 20 in the later steps. The vertical MOS transistor formed in the silicon column 20 is isolated from another vertical MOS transistor by the insulation film 19', trench capacitor and trench 28 acting as an element isolation region.
FIGS. 8A, 8B are cross sectional views indicating the sixth step. After an insulation film is formed on the inner wall of the trench 28, the insulation film 19 is formed on the polysilicon films 16, 17 by etching back the above insulation film to a depth to cover the source region 18 of the p-type well 11. The side surface of the silicon column 20 is exposed in the channel region.
FIGS. 9A, 9B are cross sectional views indicating the seventh step. A gate electrode 22 is formed around the exposed side surface of the silicon column 20 with a gate oxide film 21 disposed therebetween. More specifically, after the gate electrode 22 is formed around the exposed side surface of the silicon column 20, a polysilicon film used for forming the gate electrode 22 is buried in the trench 28 to the height which is at least higher than the surface of the silicon column 20. Then, the polysilicon film is etched with a resist (not shown) used as a mask so that the polysilicon film may remain around the silicon column 20. Next, the polysilicon film is etched to the surface of the silicon column 20 by use of the entire RIE method. Then, an insulation film 23 is buried in the trench 28.
As the later step succeeding the seventh step, the step of removing an SiO.sub.2 film 31 and SiN film 32 used as a trench mask member to expose the surface of the silicon column 20 is effected. Then, the drain region 24 of the vertical MOS transistor is formed on the top portion of the silicon column 20. Next, the bit line layer 25 is connected to the drain region 24 via a contact hole. As a result, the memory cell array shown in FIGS. 1, 2A, 2B is completed.
Thus, one memory cell (DRAM cell) is constructed by a trench capacitor and a vertical MOS transistor formed adjacent to the trench capacitor. Therefore, the height of the silicon column 20 on which the vertical MOS transistor is formed can be reduced and the aspect ratio thereof can be made small. As a result, collapse or destruction of the silicon column 20 by the stress caused in the manufacturing process can be prevented. Further, the trench 12 of the trench capacitor can be made sufficiently deep without considering the aspect ratio of the silicon column 20. Therefore, a sufficiently large capacitor area can be attained and necessary capacitance can be attained. Further, it is not necessary to form an element isolation region having normal LOCOS or insulation film buried in the trench between the memory cells. Therefore, the high integration density can be attained. [Second Embodiment]
FIG. 10 is a partial plan view of a memory cell array according to a second embodiment of this invention. FIG. 11A is a cross sectional view taken along the line A-A' of FIG. 10, FIG. 11B is a cross sectional view taken along the line B-B' of FIG. 10, and FIG. 11C is a perspective view of the main portion. In FIGS. 10, 11A, 11B, 11C, portions which are the same as those of FIGS. 1, 2A, 2B are denoted by the same reference numerals.
The inherent feature of the second embodiment over the first embodiment is that the word line layer 22 is not formed to surround the silicon column 20, but two word line layer portions 22a, 22b constructing the word line layer 22 put side wall of the silicon column 20. The other structure thereof is the same as that of the first embodiment. In the above structure, when the second trench 28 is formed in the step of FIGS. 7A, 7B, 7C of the first embodiment, the insulation film 19' is left in the second direction. Then, in the step of FIGS. 9A, 9B of the first embodiment, the word line layer portions 22a, 22b are formed on the exposed side surfaces of the silicon column 20 with gate oxide films 21 respectively disposed therebetween. More specifically, after the gate oxide films 21 are formed on the exposed side surfaces of the silicon column 20, a polysilicon film used for forming the word line layer portions 22a, 22b is buried in the trench 28 to the height which is at least higher than the surface of the silicon column 20. Then, the polysilicon film is etched with a resist (not shown) used as a mask so as to be left on the opposite side surfaces of the silicon column 20. Next, an insulation film 23 is buried in the trench 28.
With the above structure, the following effect can be obtained. In this embodiment, the lithography process for connecting the gates of the vertical transistors can be omitted and the number of steps can be reduced. [Third Embodiment]
FIGS. 12A, 12B are partial cross sectional views of a memory cell array according to a third embodiment of this invention. The third embodiment has a feature that a step portion is formed between the silicon column 20 in which the vertical MOS transistor is formed and the trench 12 in the trench capacitor and a storage node contact 29 is formed in this step portion.
The stepped structure is formed by forming the first trench 12 by use of two etching steps for attaining different etching amounts instead of the etching step of FIGS. 3A, 3B of the first embodiment. More specifically, after trenches are formed to the depth of approx. 0.5 to 0.7 .mu.m in the same trench pattern as that of the first embodiment and SiO.sub.2 side walls are formed, the trenches are further formed to the depth of 6 to 7 .mu.m. After a capacitor insulation film 13 and polysilicon film 14 for storage electrode are deposited and buried in each trench, the polysilicon film 14 is etched by use of a resist mask to expose part of the capacitor insulation film 13 on one side surface of the trench 12 and the exposed part of the capacitor insulation film 13 is removed.
After this, a polysilicon film is buried in the trench and n-type impurity is diffused from the polysilicon film so as to form a source region 18 of the vertical MOS transistor. Then, the polysilicon film is etched back from the substrate surface to the depth of approx. 0.5 to 0.7 .mu.m, an oxide film is buried therein, a second trench 28 is formed to form the silicon column 20, and the vertical MOS transistor is then formed therein.
In this embodiment, it is possible to prevent the side surface of a portion in which the vertical MOS transistor is formed from being damaged in the SN contact step and stably set the height of the SN contact portion. [Fourth Embodiment]
FIGS. 13A, 13B are partial cross sectional views of a memory cell array according to a fourth embodiment of this invention. The fourth embodiment is different from the first embodiment in the connection method for connecting the bit line layer 25 to the drain region 24 on the top portion of the silicon column 20 and the other structure in the fourth embodiment is the same as that of the first embodiment. In the first embodiment, the drain region 25 is connected to the bit line layer 25 via the contact hole. When the contact structure is used, there occurs a possibility that the contact becomes defective by misalignment or adjacent vertical MOS transistors will be short-circuited.
In the fourth embodiment, the tolerance for misalignment between the bit line contact and the drain region 24 is provided so as to prevent the contact from being defective and prevent the adjacent vertical MOS transistors from being short-circuited.
To serve the above purpose, in the fourth embodiment, a bit line contact 30 is deviated towards a corresponding bit line layer 25 by F/4 and arranged at a distance of F/4 from the end of the drain region 24.
Therefore, even if the bit line contact 30 is deviated in the first direction within the range of F/4 in the actual manufacturing process, the deviation can be tolerated and occurrence of defective contact and the short circuit between adjacent vertical MOS transistors can be prevented.
As described above, in this invention, the vertical MOS transistor is formed in position adjacent to the trench capacitor. With this structure, the height of the silicon column in which the vertical MOS transistor is formed can be set to a value of 1 .mu.m or less which is necessary for forming the transistor to reduce the aspect ratio of the silicon column, thereby making it possible to prevent collapse or destruction of the silicon column. Further, since the laminating technique is not necessary, it can be manufactured at low cost. In addition, since the substrate is not set in the electrically floating state, the problem that it cannot be cut off can be solved. Further, by disposing the trench to surround the vertical MOS transistor, it can be isolated from another vertical MOS transistor and the high integration density can be attained.
This invention is not limited to the above embodiments and can be variously modified without departing the technical scope thereof.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
What is claimed is:
1. A semiconductor memory device comprising: a substrate having at least one trench and at least one semiconductor column formed in position adjacent to said trench; at least one memory cell formed on said substrate, said memory cell being constructed by a trench capacitor and a vertical transistor having a source and drain, said trench capacitor being formed along an inside wall of said trench, with only one electrode of said trench capacitor being formed in the trench, and said vertical transistor being formed in said semiconductor column; bit line layers and word lines; wherein a plurality of memory cells are formed on said substrate, a plurality of trench capacitors and a plurality of vertical transistors are arranged in a checkerboard pattern, one electrode of said trench capacitor contacts one of said source and drain of said vertical transistor at only one side of the column, each of said trench capacitors includes a plate electrode formed of said substrate, a storage electrode buried in the trench, and a capacitor insulation film formed between said plate electrode and said storage electrode, and each of said vertical transistors includes a drain region formed in the top portion of said semiconductor column and connected to a corresponding one of said bit line layers, a gate electrode formed on the side surface of said semiconductor column and connected to a corresponding one of said word lines and a source region formed in said semiconductor column below said gate electrode and connected to said storage electrode.
2. The semiconductor memory device according to claim 1, wherein one of said trench capacitors and one of said vertical transistors which constitute one memory cell are disposed adjacent to each other along said word line layer.
3. The semiconductor memory device according to claim 1, wherein said bit line layers are arranged with the width of feature size determined by a minimum processing limit and at an interval of feature size determined by the minimum processing limit and said word line layers are arranged with the width of feature size determined by the minimum processing limit and at an interval of feature size determined by the minimum processing limit.
4. The semiconductor memory device according to claim 3, wherein each of said memory cells is formed at the center portion between adjacent two of said bit line layers.
5. The semiconductor memory device according to claim 3, wherein each of said bit line layer overlaps both of a corresponding one of said trench capacitors and an adjacent one of said vertical transistors.
6. The semiconductor memory device according to claim 3, wherein said drain region is connected to a corresponding one of said bit line layers via a bit line contact and said bit line contact is disposed separately from the end of said drain region.
7. A semiconductor memory device comprising: a substrate having a plurality of trenches and a plurality of semiconductor columns, aid trenches and said semiconductor columns being arranged in a checkerboard pattern; a memory cell array having a plurality of memory cells formed on said substrate, each of said memory cells being constructed by a trench capacitor formed in each of said trenches and a vertical transistor, said vertical transistor being formed in a semiconductor column lying adjacent to said trench capacitor; a plurality of bit line layers which are commonly connected to one of a drain and a source of the vertical transistors; and a plurality of word line layers which are each formed of two word line layer sections, between which each of said semiconductor columns is placed; wherein each of said trench capacitors includes a plate electrode formed of said substrate, a storage electrode buried in the trench, and a capacitor insulation film formed between said plate electrode and said storage electrode, and each of said vertical transistors includes a drain region formed in the top portion of said semiconductor column and connected to a corresponding one of said line layers, a gate electrode formed on the side wall of said semiconductor column and connected to a corresponding one of said word line layers and a source region formed in said semiconductor column below said gate electrode and connected to said storage electrode.
Patent Citations (5)
Non-Patent Literature (1)
- IEDM 91, 1991, A Surrounding Isolation-Merged Plate Electrode (Simple) Cell with checker layout for 256Mbit DRAMs and beyond, pp. 469-472.