Method and apparatus for efficient encoding of large data words at high code rates

[0002] This application claims priority from U.S. Provisional Application having ser. No. 60/210,641, filed on Jun. 9, 2000, and entitled EFFICIENT BLOCK CODE IMPLEMENTATION FOR VERY LARGE CODEWORDS and U.S. Provisional Application having ser. No. 60/212,547, filed on Jun. 20, 2000, and entitled SEQUENTIAL ENCODER/DECODER IMPLEMENTATION FOR BLOCK CODES WITH LARGE CODEWORDS.

[0003] The present invention relates to encoding systems. In particular, the present invention relates to encoding systems in disc drives.

[0004] In the field of digital communications, digital information is conveyed from a transmitter to a receiver through a channel. “Channel” is a generalized term that can include many things. For instance, in satellite communication systems, the channel consists of the atmosphere between an earth-bound transmitter and a satellite. In data storage devices, such as magnetic disc drives, the channel includes a storage medium where the signal is stored for some period of time before being delivered to the receiver.

[0005] All channels introduce noise into the signals they convey. To detect and sometimes to correct errors caused by this channel noise, the art has developed a large number of coding techniques. These coding techniques convert data words formed of “m” data bits into larger codewords formed of “n” code bits. The additional bits in the codewords permit the detection and sometimes the correction of errors in the signals received from the channel.

[0006] The ratio of the number of data bits to the number of code bits, m/n, is known as the code rate of the code. In general, the ability to detect and correct errors in a received signal increases as the code rate decreases because a lower code rate means a greater number of additional bits in the codeword. However, each additional bit added by the encoder increases the time and energy needed to transmit the signal through the channel. Thus, to minimize the time and energy needed to send the code, the code rate should be maximized.

[0007] In one type of coding, known as Non-Return-to-Zero Inverse (NRZI), every digital one in a codeword is represented by a transition in the transmitted signal, and every digital zero is represented by a lack of transitions in the transmitted signal. To allow the receiver to generate a clock signal from the received signal, the encoded signal is generally limited so that the number of consecutive zeros is no greater than a maximum number “k”. This kind of code is known as a run-length-limited (RLL) code with a “k” constraint.

[0008] It is also known to limit the number of consecutive ones codewords to limit the effects of inter-symbol interference, which occurs when consecutive transitions in the transmitted signal interfere with each other. This is sometimes done by requiring some number, d, of zeros between ones. An RLL code with a d and k constraint are usually referred to as a (d,k) RLL code.

[0009] To achieve higher code rates, the number of bits being encoded can be increased. For example, a 64/65 code has a higher code rate than a 17/18 code. However, with each additional bit in the input data word, the number of possible input data words increases by a multiple of 2. Thus, there are twice as many possible 64-bit data words(2⁶⁴) as there are 63-bit data words(2⁶³).

[0010] For even modest data word sizes, the number of available data words makes encoding through a simple table look-up inefficient. For example, for a word length of 20 bits, a table look-up encoding scheme would need to search a database of 2²⁰(1,048,576) entries. Thus, a system is needed for encoding and decoding large words without using a large look-up table.

[0011] The present invention addresses this and other problems, and offers other advantages over the prior art.

[0012] Methods of encoding and decoding as well as an encoder and decoder are provided for encoding data words into codewords and decoding codewords into data words. The data words are encoded by mapping each data word into a number of data segments. Each data segment is then encoded to form a codeword segment that has the same number of bits as the data word segment. The codeword segments are concatenated to form the codeword. The codewords are decoded by decoding individual codeword segments into data word segments that are the same size as the codeword segments. The data word segments are then mapped into the data word, which has fewer bits than the total number of bits across all data word segments.

[0013] FIG. 1 is a perspective view of disc drive in which aspects of the present invention may be practiced.

[0014] FIG. 2 is a block diagram of a read channel.

[0015] FIG. 3 is a block diagram of a parallel encoder under one embodiment of the present invention.

[0016] FIG. 4 is a block diagram of a parallel decoder under one embodiment of the present invention.

[0017] FIG. 5 is a more detailed block diagram of one embodiment of mapping unit 302 of FIG. 3.

[0018] FIG. 6 is a block diagram of one embodiment of inverse mapping unit 432 of FIG. 4.

[0019] FIG. 7 is a block diagram of one embodiment of a segment encoder under the present invention.

[0020] FIG. 8 is a block diagram of a second embodiment of a segment encoder under the present invention.

[0021] FIG. 9 is a block diagram of a second embodiment of a segment decoder under the present invention.

[0022] FIG. 10 is a block diagram of a sequential encoder under an embodiment of the present invention.

[0023] FIG. 11 is a block diagram of a sequential decoder under an embodiment of the present invention.

[0024] FIG. 1 is a perspective view of a disc drive 100 in which the present invention is useful. Disc drive 100 includes a housing with a base 102 and a top cover (not shown). Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown), by a disc clamp 108. Disc pack 106 includes a plurality of individual discs, which are mounted for co-rotation about central axis 109. Each disc surface has an associated disc head slider 110 which is mounted to disc drive 100 for communication with the disc surface. In the example shown in FIG. 1, sliders 110 are supported by suspensions 112 which are in turn attached to track accessing arms 114 of an actuator 116. The actuator shown in FIG. 1 is of the type known as a rotary moving coil actuator and includes a voice coil motor (VCM), shown generally at 118. Voice coil motor 118 rotates actuator 116 with its attached heads 110 about a pivot shaft 120 to position heads 110 over a desired data track along an arcuate path 122 between a disc inner diameter 124 and a disc outer diameter 126. Voice coil motor 118 is driven by servo electronics located in electronics 130 based on signals generated by heads 110 and a host computer (not shown).

[0025] FIG. 2 is a block diagram of a generalized communication system 148 used with the present invention. For the disc drive of FIG. 1, communication system 148 is formed by head 110, disc 106, and internal logic in electronics 130. Within communication system 148, an encoder 150 receives data samples 152 and produces codewords 153. Codewords 153 are provided to parallel-to-serial converter 155 in a parallel manner such that all of the bits of a respective codeword are provided to converter 155 at the same time. Parallel-to-serial converter 155 converts each parallel codeword 153 into a serial representation and concatenates the serial representations to produce a sequence of bits 154. The sequence of bits 154 meets several constraints discussed further below.

[0026] Transmitter/channel precoder 156 receives the sequence of bits 154 and conditions the sequence so that it is optimized for the type of detector used to recover the signal from the channel. Transmitter/channel precoder 156 produces write signal 158, which is provided to channel 160.

[0027] Channel 160, which is comprised of a write head, a disc, and a read head when the communication system is a disc drive, conveys the encoded information from transmitter/precoder 156 to receiver/detector 162 as a read signal 164. Receiver/detector 162 amplifies and filters read signal 164 and recovers an encoded signal from the read signal using one of several known detection methods. For instance, receiver/detector 162 may use a Viterbi detector, Decision Feedback Equalization (DFE), Fixed-Delay Tree Search with Decision Feedback (FDTS/DF) or Reduced State Sequence detection (RSSE).

[0028] After detecting and amplifying the signal from channel 160, receiver/detector 162 produces a recovered sequence of bits 165, which are provided to serial-to-parallel converter 163. Sequence of bits 165 is in a serial format at the input to serial-to-parallel converter 163. Serial-to-parallel converter 163 groups the bits into codewords and converts the codewords from a serial format to a parallel format. Serial-to-parallel converter 163 then outputs codewords 166 in a parallel format to decoder 168. Decoder 168 uses the inverse of the coding rules used by encoder 150 and converts the codewords 166 into recovered data stream 170.

[0029] The present invention provides an improved encoder and decoder that make it possible to encode large data words into large codewords while maintaining a rate of n/n+1, where n is the number of bits in the input data word. In addition, the present invention divides the task of encoding such that parallel encoders may be used or a single encoder may be used repeatedly to encode a single data word. The present invention allows for these benefits by performing an initial remapping of the data word from n bits to a collection of smaller data word segments that together have n+1 bits. Each data word segment is encoded to achieve the desired RLL constraints and the resulting codeword segments are then combined to form a single codeword of n+1 bits.

[0030] The encoding that is performed converts data segments with (n+1)/x bits into the codeword segments with (n+1)/x bits, where x is the number of segments. Because there are an equal number of bits on each side of the encoder, the data segments at the input to the encoder must be limited to only a subset of their possible values. Thus, the mapping of the data word into data segments is performed such that the data segments can only have a limited number of values. Under preferred embodiments, each of the data segments is limited to the same set of values so that the same segment block encoder may be used to encode each data segment.

[0031] The present inventors have found that the number of allowed values for each data segment when taken to the power of x, where x is the number of data segments, should be greater than but as close as possible to ½ the number of possible values for the n+1 bit codewords. The combination of the data segments must have at least ½ the values of the n+1 bit codewords so that they can represent each of the n data words. However, the number of possible values for the data segments should be as close to ½ as possible so as to maximize the number of extra codewords, thereby allowing greater flexibility in encoding the data segments to meet the RLL constraints.

[0032] FIG. 3 provides a general block diagram of a parallel encoder under one embodiment of the present invention. In FIG. 3, a data word 300 having n bits is provided to a mapping unit 302. Mapping unit 302 maps the data word into a collection of x data segments, which are represented in FIG. 3 by data segments 304, 306, 308, 310 and 312 (also designated as DSA, DSB, DSC, DSD, and DSX). Each of the data segments has (n+1)/x bits.

[0033] Each data segment is provided to a segment block encoder such as block encoders 314, 316, 318, 320 and 322. Each segment block encoder converts the data segment into a codeword segment, which also has (n+1)/x bits. In FIG. 3, this results in codeword segments 324, 326, 328, 330, and 332, which are concatenated to form a codeword 334 having n+1 bits.

[0034] Each segment block encoder is capable of enforcing a required RLL constraint. In addition, the encoders can maintain a minimum Hamming weight, which is a minimum number of ones in each codeword segment. As mentioned above, in preferred embodiments, each segment block encoder is identical to the other segment block encoders. This simplifies the design and manufacturing of the complete encoder.

[0035] FIG. 4 provides a block diagram of a parallel decoder under one embodiment of the present invention. In FIG. 4, a codeword 400 with n+1 bits is divided into x code segments each having (n+1)/x bits. These code segments are represented by segments 402, 404, 406, 408 and 410 in FIG. 4.

[0036] Each code segment is provided to a segment block decoder such as segment block decoders 412,,414, 416, 418, and 420 of FIG. 4. These segment block decoders decode the code segments into data segments such as data segments 422, 424, 426, 428 and 430. The segment block decoders perform the inverse coding function of the encoders shown in FIG. 3.

[0037] The decoded data segments are then provided to an inverse mapping unit 432, which provides an inverse of the mapping function of mapping unit 302 of FIG. 3. The results of the inverse mapping is an n-bit data word 434.

[0038] FIG. 5 provides one embodiment of mapping unit 302 of FIG. 3 for mapping the data word into data segments. In the embodiment of FIG. 5, a 64-bit data word is mapped into five 13-bit data segments. In FIG. 5, the 64-bit data word 500 is first divided into a 14-bit word 502 and a 50-bit word 504. Note that all 64 bits of data word 500 do not have to be present at the same time. Instead, the bits of the data word can appear serially. Also note that no particular set of the 64 bits must be divided to form 14-bit word 502 or 50-bit word 504 as long as the selection is consistently made for each 64-bit data word.

[0039] Fifty-bit word 504 is divided into five 10-bit words 506, 508, 510, 512, and 514. As with the 64-bit word, 50-bit word 504 does not need to have all of its bits present at the same time. Instead, the bits may appear serially and may be assigned to the 10-bit words as they appear.

[0040] Fourteen-bit word 502 is provided to a simplified mapping unit 516 when all 14 bits are present. Simplified mapping unit 516 maps the 14 bits into five 3-bit segments 518, 520, 522, 524, and 526. In performing the mapping, simplified mapping unit 516 limits each of the output 3-bit segments to a subset of the eight possible values for a 3-bit segment. For example, under one particular embodiment, simplified mapping unit 516 limits each 3-bit segment to seven of the eight possible values. In the embodiment of FIG. 5, any seven of the eight valid values may be used, although under some embodiments of the present invention a particular value is excluded from the set of valid values to achieve a coding benefit as described further below.

[0041] Each 3-bit segment is then concatenated with a respective 10-bit segment to form the 13-bit data segment. Thus, 3-bit segment 518 is concatenated with the 10-bit 506 to form 13-bit data segment 528. Similar concatenations result in 13-bit segments 530, 532, 534, and 536.

[0042] One method for performing the simplified mapping in simplified mapping unit 516 is to convert 14-bit value 502 into a base seven representation of the that value where each 3-bit segment represents a base seven digit. By converting the 14-bit input into a 15-bit base seven representation of that 14-bit value, the mapping ensures that each of the 3-bit digits will be limited to seven of eight values. In its simplest form, this mapping would exclude the value 111, which equals 8, from each of the 3-bit values. In other embodiments, after the base seven conversion, a different value is substituted for the 111 value as the invalid value. To perform this swap, any values that take on the newly designated invalid value are given the value of 111.

[0043] In other embodiments, the mapping from a 14-bit word to five 3-bit words is performed based on the strategy of mapping data bits directly to intermediate bits if the data words do not include three ones. Thus, for 14 bits of data (W13, W12, W11, W10, W9, W8, W7, W6, W5, W4, W3, W2, W1, W0) the five groups of output bits (I14, I13, I12) (I11, I10, I9) (I8, I7, I6)(I5, I4, I3) and (I2, I1, I0) are formed using the following mapping:

[0044] Thus, if none of the four groups (W11, W10, W9) (W8, W7, W6) (W5, W4, W3) or (W2, W1, W0) contain “111” the 14-bit data word can be mapped to the 15-bit codeword using table 1 above. If, however, one of these four groups contains “111” a valid value must be used in place of the invalid value. This mapping is defined through logical equations as follows:

[0045] G4=I13&I12

[0046] G3=I11&I10&I9

[0047] G2=I8&I7&I6

[0048] G1=I5&I4&I3

[0049] G0=I2&I1&I0

[0050] HH=!G3&!G2&!G1&!G0

[0051] H0=!G3&!G2&!G1&G0

[0052] H1=!G3&!G2&G1&!G0

[0053] H2=!G3&G2&!G1&!G0

[0054] H3=G3&!G2&!G1&!G0

[0055] H01=!G3&!G2&G1&G0

[0056] H02=!G3&G2&!G1&G0

[0057] H03=G3&!G2&!G1&G0

[0058] H12=!G3&G2&G1&!G0

[0059] H13=G3&!G2&G1&!G0

[0060] H23=G3&G2&!G1&!G0

[0061] H012=!G3&G2&G1&G0

[0062] H013=G3&!G2&G1&G0

[0063] H023=G3&G2&!G1&G0

[0064] H123=G3&G2&G1&!G0

[0065] H0123=G3&G2&G1&G0

[0066] JK=!HH

[0067] JJ=(JK&!G4)

[0068] KK=(JK&G4)

[0069] T2=(!H0&!H1&!H2&!H3)

[0070] T3=H012|H013|H023|H123|H0123

[0071] J6d9=(H0|H1|H2)

[0072] J3d9=(H01|H02|H12)

[0073] J3d6=(H0|H1|H03|H13)

[0074] J3d3=(H2|H3|H23)

[0075] J0d6=(H01|H013)

[0076] J0d3=(H0|H02|H03|H023)

[0077] J0d0=(H1|H2|H3|H12|H13|H23|H123)

[0078] J11=T2

[0079] J10=(H2|H3)

[0080] J9=(H1|H3)

[0081] J8=(I11&J6d9)|(I8 &H3)|H13|H23| T3

[0082] J7=(I10&J6d9)|(I7 &H3)|H03|H12| T3

[0083] J6=(I9 &J6d9)|(I6 &H3)|H02|H12|H23

[0084] J5=(I11&J3d9)|(I8 &J3d6)|(I5 &J3d3)|H0123

[0085] J4=(I10&J3d9)|(I7 &J3d6)|(I4 &J3d3)|H012|H013

[0086] J3=(I9 &J3d9)|(I6 &J3d6)|(I3 &J3d3)|H012|H023

[0087] J2=(I11&H012)|(I8 &J0d6)|(I5 &J0d3)|(I2 &J0d0)

[0088] J1=(I10&H012)|(I7 &J0d6)|(I4 &J0d3))|(I1 &J0d0)

[0089] J0=(I9 &H012)|(I6 &J0d6)|(I3 &J0d3)|(I0 &J0d0)

[0090] W14=JK

[0091] W13=(I13&(HH|JJ))|(KK&T2)

[0092] W12=(I12&(HH|JJ))|(KK&(H2|H3))

[0093] W11=(I11&HH)|(J11&JJ)|(KK)

[0094] W10=(I10&HH)|(J10&JJ)|(KK&(H1|H3))

[0095] W9=(I9 &HH)|(J9 &JJ)|(KK&(H0|H2|T2))

[0096] W8=(I8 &HH)|(J8 &JK)

[0097] W7=(I7 &HH)|(J7 &JK)

[0098] W6=(I6 &HH)|(J6 &JK)

[0099] W5=(I5 &HH)|(J5 &JK)

[0100] W4=(I4 &HH)|(J4 &JK)

[0101] W3=(I3 &HH)|(J3 &JK)

[0102] W2=(I2 &HH)|(J2 &JK)

[0103] W1=(I1 &HH)|(J1 &JK)

[0104] W0=(I0 &HH)|(J0 &JK)

[0105] Where “&” indicates a logical AND operation, “|” indicates a logical OR operation, and “!” indicates a logical NOT operation.

[0106] The mapping defined by the logical equations above is described by two tables. Each table is associated with a value for the group (D13, D12). If this group has a value that is not equal to “11” then the mapping is described by table 2 below as:

[0107] If grouping (D13, D12) is equal to “11”, then the mapping is:

[0108] FIG. 6 provides a block diagram of one embodiment of inverse mapping unit 430 of FIG. 4. In FIG. 6, five data segments 600, 602, 604, 606, and 608 that each have 13 bits are received from the segment decoders of FIG. 4. Each data segment has its first three bits separated from its remaining 10 bits to produce 3-bit segments 610, 612, 614, 616, and 618 and 10-bit segments 620, 622, 624, 626, and 628.

[0109] Three-bit segments 610, 612, 614, 616, and 618 are provided to a simplified inverse mapping unit 630 which maps the 15 bits into a 14-bit portion 632 of the data word. This inverse mapping is the inverse of the mapping performed by simplified mapping unit 516 of FIG. 5.

[0110] Ten-bit segments 620, 622, 624, 626 and 628 are combined to form a 50-bit portion 634. Fourteen-bit portion 632 is then combined with 50-bit portion 634 to form 64-bit data word 636. During the combination, the bits of 14-bit portion 632 and 50-bit portion 634 are assigned bit locations in the 64-bit word based on an inverse of the mapping used in FIG. 5 to divide the data word into a 14-bit portion and a 50-bit portion. The resulting bits of the 64-bit data word may be produced in a parallel manner or serially.

[0111] The operation of one embodiment of inverse mapping unit 630 is described below with logical equations where the 15-bit input to inverse mapping unit 630 is represented by W14-W0 and the 14-bit output is represented by I13-I0. This mapping represents the inverse of the mapping unit described above by tables 2 and 3. The logical equations describing the inverse mapping are:

[0112] HH=!W14

[0113] JK=W14

[0114] JJ=(!W11|(!W10&!W9))&JK

[0115] KK=!JJ&JK

[0116] H0=(!W11&!W10&!W9&JJ)|(!W13&!W12& W11&!W10& W9&KK)

[0117] H1=(!W11&!W10& W9&JJ)|(!W13&!W12& W11& W10&!W9&KK)

[0118] H2=(!W11& W10&!W9&JJ)|(!W13&W12& W11&!W10& W9&KK)

[0119] H3=(!W11& W10& W9&JJ)|(!W13& W12& W11& W10&!W9&KK)

[0120] T2=(W11&!W10&!W9&JJ)|(W13&!W12& W11&!W10& W9&KK)

[0121] H01=!W8&!W7&!W6&T2

[0122] H02=!W8&!W7& W6&T2

[0123] H03=!W8& W7&!W6&T2

[0124] H12=!W8& W7& W6&T2

[0125] H13=W8&!W7&!W6&T2

[0126] H23=W8&!W7& W6&T2

[0127] T3=W8& W7&!W6&T2

[0128] H012=!W5& W4& W3&T3

[0129] H013=!W5& W4&!W3&T3

[0130] H023=!W5&!W4& W3&T3

[0131] H123=!W5&!W4&!W3&T3

[0132] H0123=W5&!W4&!W3&T3

[0133] J9c6=(H0|H1|H2)

[0134] J9c3=(H01|H02|H12)

[0135] J9c0=H012

[0136] J9ca=(H3|H03|H13|H23|H123|H023|H013|H0123)

[0137] J6c6=H3

[0138] J6c3=(H0|H1|H03|H13)

[0139] J6c0=(H01|H013)

[0140] J6ca=(H2|H02|H12|H23|H123|H023|H012|H0123)

[0141] J3c3=(H2|H3|H23)

[0142] J3c0=(H0|H02|H03|H023)

[0143] J3ca=(H1|H01|H12|H13|H123|H013|H012|H0123)

[0144] J0c0=(H1|H2|H3|H12|H13|H23|H123)

[0145] J0ca=(H0|H01|H02|H03|H023|H013|H012|H0123)

[0146] J11=(W8 &J9c6)|(W5 &J9c3)|(W2 &J9c0)|J9ca

[0147] J10=(W7 &J9c6)|(W4 &J9c3)|(W1 &J9c0)|J9ca

[0148] J9=(W6 &J9c6)|(W3 &J9c3)|(W0 &J9c0)|J9ca

[0149] J8=(W8 &J6c6)|(W5 &J6c3)|(W2 &J6c0)|J6ca

[0150] J7=(W7 &J6c6)|(W4 &J6c3)|(W1 &J6c0)|J6ca

[0151] J6=(W6 &J6c6)|(W3 &J6c3)|(W0 &J6cO)|J6ca

[0152] J5=(W5 &J3c3)|(W2&J3c0)|J3ca

[0153] J4=(W4 &J3c3)|(W1&J3c0)|J3ca

[0154] J3=(W3 &J3c3)|(W0&J3c0)|J3ca

[0155] J2=(W2 &J0c0)|J0ca

[0156] J1=(W1 &J0c0)|J0ca

[0157] J0=(W0 &J0c0)|J0ca

[0158] I13=(W13&(HH|JJ))|(KK)

[0159] I12=(W12&(HH|JJ))|(KK)

[0160] I11=(W11&HH)|(J11&JK)

[0161] I10=(W10&HH)|(J10&JK)

[0162] I9=(W9 &HH)|(J9 &JK)

[0163] I8=(W8 &HH)|(J8 &JK)

[0164] I7=(W7 &HH)|(J7 &JK)

[0165] I6=(W6 &HH)|(J6 &JK)

[0166] I5=(W5 &HH)|(J5 &JK)

[0167] I4=(W4 &HH)|(J4 &JK)

[0168] I3=(W3 &HH)|(J3 &JK)

[0169] I2=(W2 &HH)|(J2 &JK)

[0170] I1=(W1 &HH)|(J1 &JK)

[0171] I0=(W0 &HH)|(J0 &JK)

[0172] The segment block encoder may be used to enforce any number of desired RLL constraints and Hamming weights. The k constraint for a RLL code can be determined as:

[0173] k=max (k_b+k_e, k_m)

[0174] where k_bequals the maximum run of zeros at the beginning of the code segment; k_mequals the maximum run of zeros at the middle of the code segment; and k_eequals the maximum run of zeros at the end of the code segment.

[0175] Table 4 below shows the number of 13-bit code segment values available for a number of different k constraints and Hamming weights.

[0176] In order to provide a 1-to-1 mapping, the constraints must allow for at least 7,168 code values. Thus, from Table 4, it can be seen that all of the constraints except the constraints in the first row may be applied to a segment block encoder under the present invention.

[0177] Under one embodiment of the present invention, a code is implemented that has a (0,7) RLL constraint with km equal to 6 and a minimum Hamming weight of 4. For this particular encoder, a simplified mapping unit is assumed that sets the first three bits of the 13-bit word using a base 7 conversion as discussed above. This base 7 conversion eliminates the value of “000” for each 3-bit segment. Thus, in a 13-bit pattern constructed of (I₁₂, I₁₁, I₁₀, I₉, I₈, I₇, I₆, I₅, I₄, I₃, I₂, I₁, I₀) the string (I₁₂, I₁₁, I₁₀) cannot equal “000”. Given this simplified mapping, the input values are then converted into an output string O₁₂-O₀according to table 5 below:

[0178] where “!0” indicates that none of the values are equal to zero and φ indicates that the value of the bit does not matter.

[0179] Codewords encoded using the segment block encoding table of Table 5 can be decoded using table 6 below:

[0180] where I₁₂-I₀are the input values to the decoder and O₁₂-O₀are the output decoded values from the decoder.

[0181] Note that the encoding of Table 5 is simplified because the simplified mapping unit has removed “000” as a possible value for the string (I₁₂, I₁₁, I₁₀). Because of this, many of the data words can be used directly as codewords because they do not violate the k constraint for the RLL code.

[0182] In alternative embodiments, the segment block encoder is formed to work in conjunction with the simplified mappings of Tables 2 and 3 above and the logic equations associated with those tables instead of the base 7 mapping.

[0183] FIG. 7 is a block diagram showing elements of such an encoder. In FIG. 7, the 13-bit data segment appears on a 13-bit line 700 that is input to a bit inverter 702 and an encoder 704. Bit inverter 702 generates two 13-bit outputs 706 and 708. Output 706 is identified by the letter N and output 708 is identified by the letter P. The operation of bit inverter 702 is described by the following logical equations where variables N0-N12 represent bits 0-12 of N output 706, variables P0-P12 represent bits 0 to 12 of P output 708, and variables D0-d12 represent bits 0-12 of D input 700. The operation of bit inverter 702 is thus described as:

[0184] N12=!D12

[0185] N11=!D11

[0186] N10=!D10

[0187] N9=!D9

[0188] N8=!D8

[0189] N7=!D7

[0190] N6=!D6

[0191] N5=!D5

[0192] N4=!D4

[0193] N3=!D3

[0194] N2=!D2

[0195] N1=!D1

[0196] N0=!D0

[0197] P12=0

[0198] P11=0

[0199] P10=0

[0200] P9=1

[0201] P8=N12

[0202] P7=N11

[0203] P6=N10

[0204] P5=N9

[0205] P4=N8

[0206] P3=N7

[0207] P2=N6

[0208] P1=N5

[0209] P0=N4

[0210] N output 706 of bit inverter 702 is provided to a codeword tester 710. Output N12-N0 are represented as input values A12-A0 within code tester 710. P output values 708 of bit inverter 702 are provided to a code tester 712 that is identical to code tester 710. In code tester 712, values P12-P0 are represented as input values A12-A0. The operation of codeword testers 710 and 712 is represented by logical equations:

[0211] Input: A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 (13 bits)

[0212] Output: T

[0213] UA0=A12 | A11 | A10 | A9 | A8

[0214] UA1=A11 | A10 | A9 | A8 | A7 | A6 | A5

[0215] UA2=A10 | A9 | A8 | A7 | A6 | A5 | A4

[0216] UA3=A9 | A8 | A7 | A6 | A5 | A4 | A3

[0217] UA4=A8 | A7 | A6 | A5 | A4 | A3 | A2

[0218] UA5=A7 | A6 | A5 | A4 | A3 | A2 | A1

[0219] UA6=A3 | A2 | A1 | A0

[0220] {VA=A12+A11+A10+A9+A8+A7+A6+A5+A4+A3+A2+A1+A0 if (VA>3) UA7=1 else UA7=0}

[0221] T=UA0&UA1&UA2&UA3&UA4&UA5&UA6&UA7

[0222] where T is the single bit output of the codeword tester. Output T of codeword tester 710 is provided to encoder 704 and appears as input TT in encoder 704. Output T of codeword tester 712 is also provided to encoder 704 and appears as input TP in encoder 704. Note that TP and TT are single bit inputs.

[0223] Encoder 704 uses the 13-bit input, D, and the single-bit inputs TP and TT to generate a 13-bit codeword 714. The operation of the encoder is described by the following logical equations where bits 0-12 of the codeword are represented by C0-C12:

[0224] Tn=!TT

[0225] Ha=TP&D3&D2&D1&D0

[0226] Ha9=Ha

[0227] Ha8=Ha & N12

[0228] Ha7=Ha & N11

[0229] Ha6=Ha & N10

[0230] Ha5=Ha & N9

[0231] Ha4=Ha & N8

[0232] Ha3=Ha & N7

[0233] Ha2=Ha & N6

[0234] Ha1=Ha & N5

[0235] Ha0=Ha & N4

[0236] G1=(D11&D10)|(D12&(D11|D10))

[0237] Hb=!Ha&G1&((D2&D1&D0)|( D3&((D2&(D1|D0))|(D1&D0))))

[0238] Hb9=Hb &( !D10 & !D3 )

[0239] Hb8=Hb &( D10 | D3 )

[0240] Hb7=Hb&(!D11 |( D12 & D3))

[0241] Hb6=Hb&(!D12 |( D11 & D3))

[0242] Hb5=Hb &D3

[0243] Hb4=Hb &( D2 & D0 )

[0244] Hb3=Hb &( D2 & D1 )

[0245] Hb2=Hb &( !D7 | !D6 | !D5 | !D4 )

[0246] Hb1=Hb &( D9 & D6 & D5 )

[0247] Hb0=Hb &( D8 & D6 & D4 )

[0248] Hc=!Ha&!Hb&D11&D10

[0249] Hc9=0

[0250] Hc8=Hc

[0251] Hc7=0

[0252] Hc6=0

[0253] Hc5=Hc &( D9 & D4 )

[0254] Hc4=Hc & !D4

[0255] Hc3=Hc &( !D9 | !D3 )

[0256] Hc2=Hc &( !D9 | !D2 )

[0257] Hc1=Hc &( D9 & !D1 )

[0258] Hc0=Hc & !D0

[0259] Hd=!Ha&!Hb&D12&(D11|D10)

[0260] Hd9=0

[0261] Hd8=Hd

[0262] Hd7=Hd &( D11 & D9 )

[0263] Hd6=Hd &( D10 & D9 )

[0264] Hd5=0

[0265] Hd4=0

[0266] Hd3=Hd &( !D9 | !D3 )

[0267] Hd2=Hd &( !D9 | !D2 )

[0268] Hd1=Hd & !D1

[0269] Hd0=Hd&(!D0 &( D11 | D9))

[0270] G2=!G1&!Ha

[0271] He=G2&D3&D2

[0272] He9=He & D12

[0273] He8=He & !D12

[0274] He7=He &( D11 | D10 )

[0275] He6=He &( D11 | D10 )

[0276] He5=He &( D11 & !D10 )

[0277] He4=He & !D10

[0278] He3=He & D8

[0279] He2=He &( D9 | !D8 )

[0280] He1=He&( D1 &( D9 | D8 ))

[0281] He0=He & D0

[0282] Hf=G2&!He&((D12|D11)|(D3&!D2))

[0283] Hf9=Hf & !D3

[0284] Hf8=Hf & D3

[0285] Hf7=Hf&( D3 &( D12 | D11))

[0286] Hf6=Hf &( !D12 &!D11 )

[0287] Hf5=Hf &( !D12 &!D3 )

[0288] Hf4=Hf & D3

[0289] Hf3=Hf &( !D12 & !D10 & !D1 & !D0 )

[0290] Hf2=Hf &( D12 | D10 | !D3 )

[0291] Hf1=Hf & D1

[0292] Hf0=Hf & D0

[0293] Hg=G2&!He&!Hf&(!D12|!D11)

[0294] Hg9=Hg &( D1 & !D2 )

[0295] Hg8=Hg &( D2 | !D1 )

[0296] Hg7=Hg & D2

[0297] Hg6=Hg & D2

[0298] Hg5=Hg & !D2

[0299] Hg4=Hg &( D1 | !D2 )

[0300] Hg3=0

[0301] Hg2=0

[0302] Hg1=Hg

[0303] Hg0=Hg & D0

[0304] C12=(TT&N12)

[0305] C11=(TT&N11)

[0306] C10=(TT&N10)

[0307] C9=(TT&N9) |(Tn&(Ha9|Hb9|Hc9|Hd9|He9|Hf9|Hg9))

[0308] C8=(TT&N8) |(Tn&(Ha8|Hb8|Hc8|Hd8|He8|Hf8|Hg8))

[0309] C7=(TT&N7) |(Tn&(Ha7|Hb7|Hc7|Hd7|He7|Hf7|Hg7))

[0310] C6=(TT&N6) |(Tn&(Ha6|Hb6|Hc6|Hd6|He6|Hf6|Hg6))

[0311] C5=(TT&N5) |(Tn&(Ha5|Hb5|Hc5|Hd5|He5|Hf5|Hg5))

[0312] C4=(TT&N4) |(Tn&(Ha4|Hb4|Hc4|Hd4|He4|Hf4|Hg4))

[0313] C3=(TT&N3) |(Tn&(Ha3|Hb3|Hc3|Hd3|He3|Hf3|Hg3))

[0314] C2=(TT&N2) |(Tn&(Ha2|Hb2|Hc2|Hd2|He2|Hf2|Hg2))

[0315] C1=(TT&N1) |(Tn&(Ha1|Hb1|Hc|Hd1|He|Hf1|Hg1))

[0316] C0=(TT&N0) |(Tn&(Ha0|Hb0|Hc0|Hd0|He0|Hf0|Hg0))

[0317] Codewords encoded using the logical equations described above may be decoded using the following logical equations where the input to the decoder is represented by bits C0-C12, the output of the decoder is represented by D0-D12, and a flag output indicative of an invalid codeword is represented by F. Thus, the segment decoder is described in logical equations as:

[0318] TT=C12|C11|C10

[0319] Tn=!TT

[0320] N12=!C12

[0321] N11=!C11

[0322] N10=!C10

[0323] N9=!C9

[0324] N8=!C8

[0325] N7=!C7

[0326] N6=!C6

[0327] N5=!C5

[0328] N4=!C4

[0329] N3=!C3

[0330] N2=!C2

[0331] N1=!C1

[0332] N0=!C0

[0333] Ha=Tn&((C9&C8)|(C9&(C7|C6)))

[0334] Ha12=Ha & N8

[0335] Ha11=Ha & N7

[0336] Ha10=Ha & N6

[0337] Ha9=Ha & N5

[0338] Ha8=Ha & N4

[0339] Ha7=Ha & N3

[0340] Ha6=Ha & N2

[0341] Ha5=Ha & N1

[0342] Ha4=Ha & N0

[0343] Ha3=Ha

[0344] Ha2=Ha

[0345] Ha1=Ha

[0346] Ha0=Ha

[0347] Hb=Tn&!Ha&(((C7|C6)&C5)|((C9|(C7{circumflex over ( )}C6))&!C5&C4&C3&(C2|C1|C0)))

[0348] Hb12=Hb &( C9 | C7 )

[0349] Hb11=Hb &( C9 | C6 )

[0350] Hb10=Hb &( C7 {circumflex over ( )} C6 )

[0351] Hb9=Hb &( C2 | C1 )

[0352] Hb8=Hb &( C2 | C0 )

[0353] Hb7=Hb &( !C2 | !C1 | !C0 )

[0354] Hb6=Hb &( C1 | C0 | !C2 )

[0355] Hb5=Hb &( C1 | !C2 | !C0 )

[0356] Hb4=Hb &( C0 | !C2 | !C1 )

[0357] Hb3=Hb & C5

[0358] Hb2=Hb &( C4 | C3 )

[0359] Hb1=Hb &( C3 | !C4 )

[0360] Hb0=Hb &( C4 | !C3 )

[0361] Hc=Tn&!Ha&C8&!C7&!C6&((C5{circumflex over ( )}C4)|(!C5&!C4&!C1))

[0362] Hc12=0

[0363] Hc1=Hc

[0364] Hc10=Hc

[0365] Hc9=Hc &( C5 | C4 )

[0366] Hc8=Hc

[0367] Hc7=Hc

[0368] Hc6=Hc

[0369] Hc5=Hc

[0370] Hc4=Hc & !C4

[0371] Hc3=Hc&(!C3 |( !C5 & !C4))

[0372] Hc2=Hc&(!C2 |( !C5 & !C4))

[0373] Hc1=Hc&(!C1 &( C5 | C4))

[0374] Hc0=Hc & !C0

[0375] Hd=Tn&!Ha&C8&!C5&!C4&((C7{circumflex over ( )}C6)|(!C7&!C6&C3&C2&C1))

[0376] Hd12=Hd

[0377] Hd11=Hd&( C7 |( C0 & !C6))

[0378] Hd10=Hd&( C6 |( !C7 & !C0))

[0379] Hd9=Hd &( C7 |C6)

[0380] Hd8=Hd

[0381] Hd7=Hd

[0382] Hd6=Hd

[0383] Hd5=Hd

[0384] Hd4=Hd

[0385] Hd3=Hd&(!C3 |( !C7 & !C6))

[0386] Hd2=Hd&(!C2 |( !C7 & !C6))

[0387] Hd1=Hd &!C1

[0388] Hd0=Hd&(!C0 &( C7 | C6))

[0389] He=Tn&!Ha&!Hb&!Hc&((C7&C6)|(C5&C4))&(C3|C2)

[0390] He12=He & C9

[0391] He1=He &( C7 & C4 )

[0392] He10=He & !C4

[0393] He9=He &( C2 &( C3 | C1))

[0394] He8=He & C3

[0395] He7=He

[0396] He6=He

[0397] He5=He

[0398] He4=He

[0399] He3=He

[0400] He2=He

[0401] He1=He &( C1 | !C3 )

[0402] He0=He & C0

[0403] Hf=Tn&!Ha&!Hb&!Hc&!Hd&!He&((C9&!C8&!C4)|((C7{circumflex over ( )}C6)&!C5&C4))

[0404] Hf12=Hf &( C2 & !C6 & !C5 )

[0405] Hf11=Hf &( C5 |( C7 & !C2))

[0406] Hf10=Hf &( C6 & C2 )

[0407] Hf9=Hf

[0408] Hf8=Hf

[0409] Hf7=Hf

[0410] Hf6=Hf

[0411] Hf5=Hf

[0412] Hf4=Hf

[0413] Hf3=Hf & !C9

[0414] Hf2=Hf & C9

[0415] Hf1=Hf & C1

[0416] Hf0=Hf & C0

[0417] Hg=Tn&!Ha&!Hb&!Hc&!Hd&!He&!Hf&((C7&C6)|(C5&C4))

[0418] Hg12=0

[0419] Hg11=0

[0420] Hg10=Hg

[0421] Hg9=Hg

[0422] Hg8=Hg

[0423] Hg7=Hg

[0424] Hg6=Hg

[0425] Hg5=Hg

[0426] Hg4=Hg

[0427] Hg3=0

[0428] Hg2=Hg & C7

[0429] Hg1=Hg&( C9 |(C7 & C4))

[0430] Hg0=Hg & C0

[0431] F=(Tn&!Ha&!Hb&!Hc&!Hd&!He&!Hf&!Hg)

[0432] D12=(TT&N12) |(Tn&(Ha12|Hb12|Hc12|Hd12|He12|Hf12|Hg12))

[0433] D11=(TT&N11) |(Tn&(Ha11|Hb11|Hc11|Hd11|He11|Hf11|Hg11))

[0434] D10=(TT&N10) |(Tn&(Ha10|Hb10|Hc10|Hd10|He10|Hf10|Hg10))

[0435] D9=(TT&N9) |(Tn&(Ha9|Hb9|Hc9|Hd9|He9|Hf9|Hg9))

[0436] D8=(TT&N8) |(Tn&(Ha8|Hb8|Hc8|Hd8|He8|Hf8|Hg8))

[0437] D7=(TT&N7) |(Tn&(Ha7|Hb7|Hc7|Hd7|He7|Hf7|Hg7))

[0438] D6=(TT&N6) |(Tn&(Ha6|Hb6|Hc6|Hd6|He6|Hf6|Hg6))

[0439] D5=(TT&N5) |(Tn&(Ha5|Hb5|Hc5|Hd5|He5|Hf5|Hg5))

[0440] D4=(TT&N4) |(Tn&(Ha4|Hb4|Hc4|Hd4|He4|Hf4|Hg4))

[0441] D3=(TT&N3) |(Tn&(Ha3|Hb3|Hc3|Hd3|He3|Hf3|Hg3))

[0442] D2=(TT&N2) |(Tn&(Ha2|Hb2|Hc2|Hd2|He2|Hf2|Hg2))

[0443] D1=(TT&N1) |(Tn&(Ha1|Hb1|Hc1|Hd1|He1|Hf1|Hg1))

[0444] D0=(TT&N0) |(Tn&(Ha0|Hb0|Hc0|Hd0|He0|Hf0|Hg0))

[0445] The encoder and decoders described above by logical equations can be summarized by the following codeword table where the first column of the table indicates the first two hexadecimal digits of the data word and the last hexadecimal digit of the data word is found across the top row of each table. The codeword associated with the complete data word is then found by finding the intersection of the first two hexadecimal values for the data word and the third hexadecimal value for the data word. For example, the data word 0F7 has an associated codeword of 1F08 in the following tables.

[0446] Although the encoder and decoder described above have been described with reference to a rate 64/65 encoder, any rate may be used with appropriate changes to the simplified mapping and the segment block encoders. For example, a 99/100 rate encoder can be constructed by separating the 99 bits of the data word into a 14-bit segment and an 85-bit segment. The 14-bit segment is then mapped into five 3-bit segments using the same process as described above. The 85-bit segment is divided into five 17-bit subsegments. These subsegments are combined with the 3-bit segments to form five 20-bit segments that are then encoded by a 20 bit to 20 bit encoder. The resulting code segments are concatenated to form the 100-bit codeword.

[0447] FIG. 8 provides a block diagram of one embodiment of a segment encoder for encoding 20-bit data segments into 20-bit code segments. In FIG. 8, each 20-bit data segment 800 is divided into an 8-bit segment 802 and a 12-bit segment 804. The 12-bit segment is further divided into two 6-bit segments 806 and 808.

[0448] Eight-bit section 802 is mapped into two 4-bit sections 810 and 812 by a mapping unit 814. Under one embodiment, this mapping is performed by representing the 8-bit value as a base 15 number, where 4-bit value 810 and 812 are each binary representations of base-15 digits.

[0449] One of the embodiments of the mapping performed by mapping unit 814 can be summarized by:

[0450] Where I7-I0 represents the 8-bit input segment G3-G0 represents one 4-bit output segment and F3-F0 represents another output segment. Note that the mapping in Table 14 assumes that a simplified mapping unit such as simplified mapping unit 516 has been used to designate input bits I7, I6, and I5 and that the simplified mapping unit will not set (I7, I6, I5) equal to “000”.

[0451] Four-bit section 810 is combined with 6-bit section 806 to form a 10-bit segment 816 that is input to a 10-bit encoder 818. Similarly, 4-bit section 812 is combined with 6-bit section 808 to form a 10-bit section 820 that is input to 10-bit encoder 822. Ten-bit encoders 818 and 822 are identical and each generates a 10-bit code section. The two 10-bit code sections are combined to form a 20-bit code segment 824.

[0452] Under one embodiment that works with the mapping of table 14, each 10-bit encoder converts the 10-bit data segments into 10-bit codeword sub-segments as found in Table 15 below:

[0453] In table 15, the 10-bit word input to the encoder is designated by bits I9-I0 and the 10-bit output word is designated by bits O9-O0. In table 15 input bits I9-I6 are provided by mapping unit 814.

[0454] FIG. 9 provides a block diagram of a 20-bit segment decoder that performs the inverse of the encoding operation performed by the encoder of FIG. 8. In FIG. 9, a 20-bit codeword segment 900 is divided into two 10-bit codeword sub-segments 902 and 904. The two 10-bit codeword sub-segments are provided to 10-bit decoders 906 and 908, respectively, which decode the sub-segments using an inverse function of the encoding function applied by encoders 818 and 822 of FIG. 8. The 10-bit decoded values 910 and 912 provided by the decoders are each separated into a 4-bit segment and a 6-bit segment. The two 4-bit segments 914 and 916 are provided to an inverse mapping unit 918 that provides an inverse of the mapping provided by mapping unit 814 of FIG. 8. This results in an 8-bit output section 920.

[0455] The two 6-bit values that are split off from 10-bit decoded values 910 and 912 are combined to form a 12-bit value 922 that is then combined with 8-bit section 920 to form a 20-bit data segment 924.

[0456] In the embodiments discussed above, the segment block encoders and decoders operate in a parallel fashion. In other embodiments, the segment block encoders operate in a sequential fashion. Under such embodiments, a single segment block encoder is used repeatedly to encode the entire data word.

[0457] FIG. 10 provides a block diagram of such a sequential encoder. Table 16 below shows a timing table that illustrates the location of certain values within the encoder during different parts of the encoding process.

[0458] Where p equals the number of bits (n−SM) not provided to simplified mapping unit 1002 and the designation D_s:D_erepresents the bits spanning from starting bit D_sto ending bit D_e.

[0459] As shown in FIG. 10 and Table 16, during a first encoding cycle, a first section 1000 of the data word is applied to a simplified mapping unit 1002. In FIG. 10 and table 16, the number of bits applied to simplified mapping unit 1002 is represented generically by “SM”. Using the simplified mapping units described above, SM would be equal to 14.

[0460] Simplified mapping unit 1002 maps the SM bits at its input into x sections that each have (SM+1)/x bits. Each of the sections is output in parallel as shown by output lines 1004, 1006, 1008, 1010, and 1012, which are also designated as A, B, C, D, and X in Table 16.

[0461] The parallel outputs provided by simplified mapping unit 1002 are input to a multiplexer 1014, which selects a different one of the parallel inputs as its output at each encoding cycle. The output of multiplexer 1014 is shown as output 1016, which is provided to a segment encoder 1018. The value on output 1016 is shown in Table 16 in the row identified as MUX_OUT.

[0462] During the first encoding cycle, segment encoder 1018 also receives the next (n−SM)/x bits in the input data word where n is the number of total bits in the data word, SM is the number of bits provided to the simplified mapping, and x is the number of encoding cycles. This input is provided to encoder 1018 along encoding line 1020.

[0463] Given the values on encoder input lines 1016 and 1020, encoder 1018 generates a single codeword during the first encoding cycle. Since encoder input line 1016 has (SM+1)/x bits and encoder input line 1020 has (n−SM)/x bits, the total number of input bits is equal to (n+1)/x. Thus, segment encoder 1018 is encoding an (n+1)/x data segment into an (n+1)/x codeword segment. As such, any of the segment encoders described above may be used as segment encoder 1018.

[0464] With the production of the codeword, designated as CSA in Table 16, the first encoding cycle is complete and the second encoding cycle may begin. During the second encoding cycle, the next (n−SM)/x bits in the data word is applied to encoder 1018 along encoding line 1020. At the same time, multiplexer 1014 passes the value on input line 1006 to its output 1016. Using the values on input lines 1016 and 1020, encoder 1018 then encodes this value to produce a codeword designated as CSB in Table 16.

[0465] This process of sequentially encoding the data word continues until the last (n−SM)/x bits in the data word and the last parallel output of simplified mapping unit 1002 have been applied to encoder 1018 to produce a codeword segment. In Table 16, this last encoding step is shown as encoding cycle x.

[0466] An additional aspect of the present invention is a sequential decoder that provides an inverse of the mapping provided by the sequential encoder of FIG. 10. FIG. 11 provides a block diagram of such a sequential decoder. In FIG. 11, each codeword is divided into x segments with each segment having (n+1)/x bits. During a first decoding cycle, the first (n+1)/x bits appear on input line 1100 as input to a segment decoder 1102. Segment decoder 1102 provides an inverse of the coding function provided by segment encoder 1018 of FIG. 10.

[0467] Segment decoder 1102 divides the resulting decoded data segment into a first section 1104 having (SM+1)/x bits and a second section 1106 having (n−SM)/x bits.

[0468] The (SM+1)/x bits on line 1104 is provided to a multiplexer 1108 which routes the bits to an appropriate output line based on the current decoding cycle. In FIG. 11, five decoding lines 1110, 1112, 1114, 1116, and 1118 are shown that each carry (SM+1)/x bits. At each decoding cycle, multiplexer 1108 places the output from segment decoder 1102 on a different one of the output lines. Thus, after an entire codeword has been provided to segment decoder 1102, each of the output lines from multiplexer 1108 has carried a portion of a decoded segment.

[0469] With each decoding cycle, segment decoder 1102 produces a different portion of the data word on output line 1106. Under one embodiment, these individual portions of the data word are stored for later combination with the remaining portions of the data word before any further operations are performed on these decoded portions. In other embodiments, additional operations are performed on the individual portions of the data word before the entire data word has been decoded.

[0470] Once the entire codeword has been decoded by segment decoder 1102, inverse simplified mapping unit 1120 converts the values it has received on inputs 1110, 1112, 1114, 1116, and 1118 into a section 1122 of the data word having SM bits. The inverse mapping performed by inverse simplified mapping unit 1120 is the inverse of the mapping performed by mapping unit 1002 of FIG. 10. In one embodiment, section 1122 is then combined with the remaining portions of the data word to form a complete data word.

[0471] Note that the sequential encoder of FIG. 10 does not require that a sequential decoder be used to decode the codewords. A parallel decoder may be used to decode the codewords. Similarly, the sequential decoder of FIG. 11 may be used to decode codewords that have been formed by a parallel encoder.

[0472] The sequential encoder and decoder of FIGS. 10 and 11 may be used to encode and decode data words and codewords of any size. In one embodiment of the present invention, the sequential encoder was used to encode 64-bit data words into 65-bit codewords. In other embodiments, the sequential encoder is used to encode 99-bit data words into 100-bit codewords.

[0473] In summary, a method of encoding data words 300 into code words 334 is provided. The method includes mapping the data words 300 into a number of data segments 304, 306, 308, 310, and 312, each data segment having a number of bits equal to the number of bits in a codeword 334 (n+1) divided by the number (x) of data segments 304, 306, 308, 310, and 312. Each data segment 304, 306, 308, 310, and 312 is then encoded into a codeword segment 324, 326, 328, 330, and 332 having the same number of bits as the data segment. The codeword segments 324, 326, 328, 330, and 332 are then concatenated to form the codeword.

[0474] A decoder 168 is also provided for a disc drive 100. The decoder 168 decodes codewords 400 into data words 434 and includes at least one segment decoder 412, 414, 416, 418, and 420 for decoding each of a plurality of equally sized segments 402, 404, 406, 408, and 410 of the codeword 400. The decoding performed by segment decoder 412, 414, 416, 418 and 420 results in a plurality of data segments 422, 424, 426, 428, and 430 that are each the same size as the codeword segments. An inverse mapping unit 432 maps the plurality of data segments 422, 424, 426, 428, and 430 into a single data word 434.

[0475] It is to be understood that even though numerous characteristics and advantages of various embodiments of the invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the read channel while maintaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, although the preferred embodiment described herein is directed to a read channel for a disc drive system, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to other systems, like communication systems or other storage systems, without departing from the scope and spirit of the present invention.