Method and Apparatus for Implementing Run Length Limited Codes in Partial Response Channels

The present invention relates in general to information storage systems, and more particularly, to a method and apparatus for implementing run length limited codes in partial response channels in a digital magnetic recording system.

In digital magnetic recording systems, data is recorded in a moving magnetic media layer by a storage, or "write" electrical current-to-magnetic field transducer, or "head", positioned immediately adjacent thereto. The data is stored or written to the magnetic media by switching the direction of flow of a substantially constant magnitude write current which flows through windings in the write transducer. Each write current direction transition results in a reversal of the magnetization direction in that portion of the magnetic media just passing by the transducer during current flow in the new direction, with respect to the magnetization direction in the media induced by the previous current flow in the opposite direction. In one scheme, a magnetization direction reversal over a portion of the media moving past the transducer represents a binary digit "1", and the lack of any reversal in that portion represents a binary digit "0".

When data is to be recovered, a retrieval, or "read" magnetic field-to-voltage transducer, (which may be the same as the write transducer if both are inductive) is positioned to have the magnetic media, containing previously stored data, pass thereby such that flux reversal regions in that media either induce, or change a circuit parameter to provide, a voltage pulse to form an output read signal for that transducer. In the scheme described above, each such voltage pulse due to the magnetizations in corresponding media portions represents a binary digit "1" and the absence of a pulse in correspondence with such portions represents a binary digit "0".

In digital magnetic recording systems using peak detection of such voltage pulses as the data recovery method to digitize the read signal, the times between voltage pulses are used to reconstruct the timing information used in recording the data previously stored in the magnetic media to define the path portions described above. More specifically, the output of such a peak detector is used as an input signal to a phase-locked loop forming a controlled oscillator, or phase-lock oscillator (PLO), or synchronizer, which produces an output clock signal from the positions of the detected peaks of the read signal. Absolute time is not used in operating the data retrieval system portion since the speed of the magnetic media varies over time which results in nonuniform time intervals between read signal voltage pulses.

A data encoding scheme known as run-length-limited (RLL) coding is commonly used to improve the PLO's reconstructed clock signal accuracy based on avoiding drift in the frequency thereof because of too much time between voltage read signal pulses. When RLL code is employed, the time durations between read signal voltage pulse transitions is bounded, that is, the number of binary digits of value "0" that can separate binary digits of value "1" in the read signal is limited. This constraint is known overall as a (d,k) constraint where the individual constraint "d" represents the minimum run length of zeros, or the number thereof between ones, while the individual constraint "k" represents the maximum run length of zeros permitted. The "d" portion of the constraint can be chosen so as to avoid crowding of voltage pulses in the read signals which can reduce intersymbol interference problems in which portions of read signal voltage pulses overlap. By limiting the number of consecutive zeros, the "k" constraint maintains the reliability of the PLO in providing an accurate clock signal for the retrieval system. An automatic gain control (AGC) system is used to maintain signal amplitude for the PR4 channel, and the "k" restraint also maintains the reliability of the AGC.

In digital magnetic recording systems employing partial response (PR) signaling, which involves the acceptance of intersymbol interference, data recovery is achieved by periodically sampling the amplitude of the read transducer output signal, as initiated by clock pulses of the PLO, to digitize that signal. In this scheme, each clock pulse of the PLO initiates a sample which has value contributed to it by more than one pulse in the transducer read signal. Thus, a partial response detection system is designed to accommodate the effects of such intersymbol interference, and therefore the "d" constraint may not be necessary (i.e. d=0). The "k" constraint is still necessary in PR signalling because the PLO is still used to provide timing for sampling the read signal, and because the AGC is used to maintain sample amplitude in connection with the PR channel.

A selected frequency response is chosen for the signal channel through which the read signal passes prior to detection thereof, termed a class 4 response, that is particularly suitable for magnetic recording with typical pulse characteristics because the channel requires very little equalization to achieve an overall match of this class 4 response. In a class 4 PR channel for typical pulse characteristics, signal samples are independent of their immediately neighboring samples, but are dependent on samples 2 clock samples away. Therefore, read samples can be divided into 2 subsequences, one of odd indexed samples and one of even indexed samples. Each such subsequence is submitted independently to a Viterbi Algorithm decoder which generates the data that most likely reproduces the original stored values. To limit the delay and increase the accuracy and reliability of the Viterbi Algorithm decoder, another individual constraint, "i", is incorporated in the RLL code for a class 4 partial response channel. The "i" constraint represents the maximum run length of zeros in each subsequence, and the overall constraint for a class 4 PR channel is denoted as (d, k/i), where "d" and "k" represent the same constraints as mentioned above with respect to (d,k) code, and where "d" is set to zero as indicated above.

In order to satisfy the (d, k/i) constraint, "m" data symbols or bits are mapped into "n" code symbols, where "m" is less than "n". The rate of the code to transmit information bits out of the total bits transmitted is given by the formula r=m/n, and for ease of implementation "m" and "n" are usually chosen to be small integers. Since a unit of 8 bits per byte is widely used in the computer and electronic industry, reasonable choices of "m" are 8 and 16. In order to keep the code rate high, "n" is chosen to be equal to "m+1" and so code rates of 8/9 and 16/17 are popular for class 4 partial response channels.

The "m" data symbols, or binary data bits are mapped into the "n" code symbols, or binary data bits, by selecting 2.sup.m different n-bit patterns which satisfy the (d, k/i) constant. Since Boolean logic is used to implement such bit pattern mapping, the larger the "m" and "n" are, the more complex the Boolean logic that is required. In recent years the 8/9 rate for such run length codes has been the most popular rate since it only requires 2.sup.8 or 256 different 9-bit patterns which satisfy the (0, k/i) constraint which simplifies the encoder and decoder Boolean logic required to implement the pattern mapping. However, the 16/17 rate in such codes is 5.8% higher than the 8/9 rate for encoding a given set of data. In order to develop a rate of 16/17 for a (0, k/i) RLL code using such bit pattern mapping to encode the data symbols, there is needed 2.sup.16 or 65,536 17-bit patterns which must satisfy the (0, k/i) constraint. This large number of possible 17-bit codeword combinations requires very complex, and thus undesirable, encoder and decoder logic, compared to the rate 8/9 RLL code. Thus, it would be desirable to provide a 16/17 rate RLL code which is easier to implement than one otherwise obtained through pattern mapping 2.sup.16 possible 17-bit code symbol or codeword combinations.

The present invention relates to a method and apparatus for implementing run length limited codes for partial response channels employing maximum likelihood detection. The present invention relates to an apparatus for encoding data segments having therein a selected number of ordered bits of binary data obtained from a sequence of ordered bits of binary data. These data segments are encoded into corresponding codewords having a selected number of ordered bits of binary data such that the sequence of ordered bits of binary data is encoded into a corresponding sequence of codewords. The apparatus comprises receiver means for receiving the data segments, separating means for separating the selected number of ordered bits of binary data of each segment into a corresponding first group and a corresponding second group, encoder mapping means for mapping the first group into a corresponding word having a selected number of ordered bits of binary data, and interleaving means for interleaving the bit of each corresponding second group with the selected number of ordered bits of binary data of each corresponding word to obtain the corresponding codewords. Each such codeword has no more than a first pre-selected number of consecutive zeros therein. Adjacent ones of these codewords in the sequence of codewords have no more than the first pre-selected number of consecutive zeros bridging across the boundary between them. Each such codeword comprises two subsequences, one of these subsequence consisting only of every other bit of the selected number of ordered bits of binary data of the codeword and the other subsequence consisting only of the remaining bits. Each of the subsequences has no more than a second pre-selected number of consecutive zeros therein. Adjacent ones of these subsequences of codewords within the sequence of codewords have no more than the second pre-selected number of zeros bridging across the boundary between them.

Run length limited codes under the present invention are suitable for partial response channels for which Viterbi detection is employed in decoding transmissions therethrough, and which are characterized by d, k, and i constraints. According to the present invention, the alternative overall constraints provided for a RLL code having a 16/17 rate are (0, 8/6) and (0, 6/6). The present invention is characterized by sequential Boolean logic equations and look-up tables for encoding and decoding 16/17 rate RLL codes having these constraints. Although the present invention is particularly related to partial response maximum likelihood detection code constraints for use in magnetic recording of digital data in disc memory devices, the code constraints and the equations for encoding and decoding data in accordance herewith are applicable to any PR signalling system including magnetic-optic and optical recording systems.

FIG. 1 is a block diagram of a system employing a 16/17 rate RLL code modulation scheme under a (0, 8/6) constraint in accordance with the principals of the present invention;

FIG. 2 is a table of 256 hexadecimal numbers equivalent to 9-bit binary sequences for 8/9 rate RLL code for use in deriving a 16/17 rate RLL code under a (0, 8/6) constraint in accordance with the principals of the present invention;

FIG. 3 is a diagram of the table of FIG. 2 showing a partition grouping pattern for a 16/17 rate RLL code under a (0, 8/6) constraint;

FIG. 4 is a block diagram of a system employing a 16/17 rate RLL code modulation scheme under a (0, 6/6) constraint in accordance with the principals of the present invention;

FIGS. 5A and 5B are tables of 512 hexadecimal numbers equivalent to 10-bit binary sequences for 9/10 rate RLL code for use in deriving a 16/17 rate RLL code under a (0, 6/6) constraint in accordance with the principals of the present invention; and

FIG. 6 is a diagram of the table of FIG. 4 showing a partition grouping pattern for a 16/17 rate RLL code under a (0, 6/6) constraint.

Referring to FIG. 1, a magnetic recording storage and retrieval system 10 utilizes a 16/17 rate RLL code scheme for writing bits of coded binary data to magnetic media in system 10 from a binary data stream received from a storage using system (not shown), system 10 thereafter permitting selective reading of such data therefrom. The original sequence binary data is considered as groups of 16 bits of data, such a group being denoted D.sub.16 in FIG. 1, and the encoded data is represented by a corresponding group of 17 bits of data denoted D.sub.17 in that figure. System 10 includes an encoder 14 for receiving and encoding the groups of ordered bits of binary data into corresponding codewords, a precoder 16, having a 1/(1.sym.D.sup.2) transfer function suitable for use with a class 4 partial response (PR 4) read signal channel to aid in the subsequent decoding of the data sent therethrough. This partial response read signal channel is formed by the magnetic media, the heads used for reading and writing the encoded data to and from the media (the media and head together form a structure denoted by the reference number 18) and an equalizer 20. The PR4 signal channel, if formed by head structure 18 and equalizer 20, has the desired 1-D.sup.2 class 4 response. A Viterbi algorithm detector 22 determines, from the read signal provided by the read head in media and head structure 18, the most likely sequence of recorded data codewords which produced that read signal. These results are provided to a decoder 24 for receiving and decoding the sequences of codewords to obtain the original ordered bits of binary data.

In accordance with the present invention, an RLL code having a 16/17 rate and a (0, 8/6) overall (d,k/i) constraint is derived from an RLL code having an 8/9 rate as will be explained below, to provide a simpler way of encoding and decoding received data into a 16/17 rate RLL code than by mapping the data groups received into corresponding ones of 2.sup.16 different 17-bit codeword patterns. The encoder 14 includes an input latch 30, an 8/9 encoder 32, an output latch 34, and a parallel-to-series converter 36. A sequence of binary data bits from some system making use of recording system 10, which data may have been previously encoded for other purposes, is supplied to input latch 30 in encoder 14. These data bits are synchronously entered therein 8 bits (1 byte) of binary data at a time by a clocking signal supplied from an electronic clock oscillator (not shown) based on a phase-lock loop provided elsewhere in system 10 as described above. After 16 bits (two bytes) of binary have been clocked into input latch 30, the 16 bits of binary data are treated as being grouped into a first group of 8 bits, here denoted byte A, and a second group of 8 bits, here denoted byte B, wherein:

The logic gates in 8/9 encoder 32 perform certain logic functions (given below) on byte A that effectively "maps" byte A into a 9-bit initial codeword, C, wherein:

following the requirements for the selected run length constraint (0,8/6). Output latch 34 interleaves 9-bit word C with byte B to form a 17-bit codeword, W, which satisfies the (0, 8/6) overall constraint and which is denoted as:

Parallel-to-series converter 36 serially provides the 17 bits of the codeword W to the precoder 16 which, in turn, provides a further coded version of them to the media portion of media and head structure 18.

The encoded data (codewords W) can thereafter be selectively read as desired from this media to form a read signal which passes through the rest of the PR 4 signal channel, as maintained by equalizer 20, to reach Viterbi algorithm detector 22. Precoder 16, media and head structure 18, equalizer 20, Viterbi algorithm detector 22, input latch 30, output latch 34 and parallel-to-serial converter 36 are well known components to those skilled in the art. Those skilled in the art will recognize that there are many ways to configure digital magnetic recording system 10, but the present invention is directed to the encoding scheme established by the logic structure of encoder 14 which uses a relatively simple technique to provide RLL coding of incoming data at an information symbol rate of 16/17 through interleaving the 9 code bits of word C with the data bits of byte B to form codeword W.

Each codeword W includes two subsequences of alternating bits, wherein a first subsequence, W.sub.1, consists only of every other bit in a codeword W, and the second subsequence, W.sub.2, consists of the remaining bits of that codeword W. Typically, the first subsequence, W.sub.1, is denoted as an odd sequence because of having therein the bits from the odd numbered bit positions in codeword W wherein:

The remaining bits form the second sequence, W.sub.2, which is typically denoted as an even sequence wherein:

It is necessary for proper operation of the system phase-lock loop, as described above, to ensure that within each codeword W, and across the boundary between adjacent codewords W in a sequence thereof, the maximum number of consecutive zeros is 8. Similarly, within each subsequence W.sub.1 and W.sub.2 and (a) across the boundary between adjacent subsequences W.sub.1 in a sequence thereof, and (b) across the boundary between adjacent subsequences W.sub.2 in a sequence thereof, the maximum number of consecutive zeros is 6. Also, it is undesirable to constrain the bits of byte B (which would effectively place a constraint on the user system since byte B is not being encoded). Thus, the structure of 8/9 encoder 32 must effectively map byte A into codeword C so, in the worst case scenario (when byte B is all zeros), the codeword W will still satisfy the (0,8/6) constraint mentioned above. Since d=0, the following conditions ensure that the "k" and "i" limits in this constraint are satisfied:

Equations 7 and 8 above ensure that the k=8 constraint is satisfied at the boundary between adjacent codewords W since a 1 value for any of bits C.sub.8, C.sub.7, and C.sub.6, and bits C.sub.1, and C.sub.0 of any codeword W.sub.n (see equation 4 above) effectively limits the length of a string of zeros possible over any 8 consecutive bits (assuming the worse case scenario where byte B is all zeros) across the boundary between codeword W and either of adjacent codewords W.sub.n.+-.1. Equations 9-12 ensure that within each codeword W the k=8 constraint is satisfied, since a 1 value for any of bits C.sub.7, C.sub.6, C.sub.s, C.sub.4, C.sub.3, C.sub.2 and C.sub.1 of codeword W (again see equation 4 above) effectively limits the length of a string of zeros possible over any 8 consecutive bits (assuming the worst scenario where byte B is all zeros) within each codeword W. Equation 13, in combination with equations 7 and 8, ensures that within each odd subsequence W.sub.1, and at the boundary between odd subsequences W.sub.1 of codewords adjacent to W, the i=6 constraint is satisfied, since a 1 value for any of bits C.sub.8, C.sub.7, C.sub.6, C.sub.1 and C.sub.0 of codeword W effectively limits the length of a string of zeros possible over any 6 consecutive bits within any odd subsequence W.sub.1:n and over any 6 consecutive bits across the boundary between odd subsequence W.sub.1:n and either of adjacent odd subsequences W.sub.1n.+-.1. Equation 14, in combination with equations 1 and 2, ensures that within each even subsequence W.sub.2, and at the boundary between even subsequences W.sub.2 of codewords adjacent to W, the i=6 constraint is satisfied, since a 1 value for any of bits C.sub.8, C.sub.7, C.sub.6, C.sub.5, C.sub.4, C.sub.3, C.sub.2, C.sub.1 and C.sub.0 of codeword W effectively limit the length of a string of zeros possible over any 6 consecutive bits within any even subsequence W.sub.2:n, and over any 6 consecutive bits across the boundary between each even subsequence W.sub.2:n and either of adjacent even subsequences W.sub.2:n.+-.1.

There are 256 different 9-bit patterns which satisfy the conditions in equations 7-14 which exactly matches the number of all possible 8-bit patterns (i.e. 2.sup.8). FIG. 2 shows a table representing a one-to-one mapping of any possible value of a byte A, taken as a two-digit hexadecimal number, into the corresponding 9-bit word C taken as a three digit hexadecimal number such that equations 7-14 are satisfied. The bit patterns are shown in hexadecimal form in FIG. 2 for simplicity with the least significant (LS) digit in the byte A hexadecimal number represented in the top line and the most significant (MS) digit represented in the leftmost column of the table of FIG. 2. Thus, 8/9 encoder 32 effectively converts a value of byte A, represented by a digit in the top row and one in the leftmost column of the table in FIG. 2, to the corresponding C word value at the corresponding row and column interaction.

In order to simplify the implementation of the Boolean logic equations of 8/9 encoder 32 based on the table of FIG. 2, the 256 different values for 9-bit initial codeword C shown in the table of FIG. 2 can be grouped by various partitioning schemes, including being grouped into the six partitions thereof shown in FIG. 3. In other words, FIG. 3 is a diagram of the table of FIG. 2 in which the various partitions, denoted by one of the capital letters G, H, J, K, L and M, represent groups of 9-bit C words in Table 2 having a predetermined relationship to each other described below. All of the definitions of logic structure of 8/9 encoder 32 can be expressed in Boolean logic expressions, wherein ".multidot." denotes an AND gate, "+" denotes an OR gate, .sym. denotes an exclusive OR gate, and " " denotes a NOT gate or logic invertor.

Referring to FIG. 3, the first partition of word assignments, denoted G, comprises the set of data bytes correspondingly shown in FIG. 2 in which the first and last 4 bits of the 8-bit binary data byte A are mapped without change into the first and last 4 bits, respectively, of the 9-bit word C. The middle bit, i.e. the 5th bit position, of the 9-bit word C in this partition is always 1. Partition G comprises 8 groups of 18 different 9-bit words C as shown in FIG. 3, which total 144 separate C words and which can be identified by the equation:

A second partition, H, comprises 8 groups of 6 different 9-bit C words as shown in FIG. 3, which total 48 separate C words, which can be identified by the equation:

A third partition, J, comprises 8 groups of 3 different 9-bit C words as shown in FIG. 3, which total 24 separate C words, and which can be identified by the equation:

A fourth partition, K, comprises 6 groups of 3 different 9-bits C words as shown in FIG. 3, which total 18 separate C words and which can be identified by the equation:

A fifth partition, L, comprises 16 individual C words as shown in FIG. 3, which can be identified by the equation:

A sixth partition, M, comprises the remaining 2 groups of 3 9-bit words C, as shown in FIG. 3, which total 6 separate C words and which can be identified by the equation:

The Boolean logic equations for 8/9 encoder 32 for encoding data bits A.sub.7 -A.sub.0 into codeword bits C.sub.8 -C.sub.0 based on the table of FIG. 2 are simplified using these partitions, and so the following equations for this encoder are presented utilizing the six partitions equations G, H, J, K, L and M described above in equations 15-20:

Those skilled in the art will recognize that other partitions are possible, that Boolean expressions further reduced, or other equivalent expressions perhaps more conducive to implementing the particular logic gate circuits chosen for use, may be obtained for the present logic expressions described in equations 15-29, and thus, that there are other possible forms for the logic equations (equations 15-29) used in constructing 8/9 encoder 32. As mentioned above, the 9 bits of word C are interleaved with the 8 bits of byte B to form the 17-bit codeword W which is written to and read from the magnetic media in media and head structure 18.

Referring back to FIG. 1, decoder 24 functions to reconstruct the original data bits A.sub.7 -A.sub.0 and B.sub.7 -B.sub.0 from the codeword W signal read from the media in media and structure 18, after this signal is transmitted over the equalized channel to reach Viterbi detector 22. Decoder 24 includes serial parallel converter 50, input latch 52, 9/8 decoder 54, and output latch 56. Input latch 52 separates the interleaved 17 bits of codeword W into 9-bit word C and byte B. Here, 9/8 decoder 54 effectively converts a value of word C represented in a row-column intersection of the table in FIG. 2 to the corresponding value of byte A represented in the corresponding top row digit position and leftmost column digit position. In doing so, 9/8 decoder 54 identifies six partition groupings G, H, J, K, L and M similar to those used in the 8/9 encoder 32 (See FIG. 3 in terms of the location and number of the 9-bit words C in each partition). Each partition group in 9/8 decoder 54 can be expressed as a function of code bits C.sub.8 -C.sub.0 as follows:

The Boolean logic equations for 9/8 decoder 54 for decoding code bits C.sub.8 -C.sub.0 into data bits A.sub.7 -A.sub.0 are given by the following equations utilizing the six partition equations G, H, J, K, L and M described above in equations 30-35:

Output latch 56 provides as an output the original data bits A.sub.7 -A.sub.0 which were decoded by 9/8 decoder 54, and the data bits B.sub.7 -B.sub.0 which were recovered in input latch 52. Those skilled in the art will recognize that further reductions in the Boolean expressions, or other equivalent expressions more helpful in implementing the logic gate circuits chosen, may be obtained for the present logic expressions described in equations 30-43, and thus, that there are other possible forms for the logic equations (equations 30-43) used for constructing 9/8 decoder gating 54.

In accordance with another embodiment of the present invention, as illustrated in FIGS. 4-6, there is provided a system 10' utilizing an RLL code having a 16/17 rate and (0, 6/6) overall (d, k, i) constraint which is derived from an RLL code having a 9/10 rate as will be explained below, to provide another way of encoding and decoding received data into a 16/17 RLL rate code again by the method of bit pattern mapping. This rate code has a smaller "k" constraint, compared to the previously described 16/17 rate RLL code with a (0, 8/6) constraint, and is likely to increase update information to the PLO and ACG to thereby provide better performance by system 10', as compared to system 10. Unless otherwise stated, the components hereinafter described with respect to the embodiment illustrated in FIGS. 4-6 are the same as and will operate in the same manner as those components described above with respect to the embodiment illustrated in FIGS. 1-3. Components in FIGS. 4-6 which differ from corresponding ones in FIGS. 1-3 are designated with the same number in FIGS. 4-6 but with a prime symbol placed thereafter. Referring to FIGS. 4-6, encoder 14' is supplied with 16 binary data bit groups as before which are then synchronously entered in latch 30' by the clocking signal where they are treated as being in a first word having 9 bits therein, here denoted A, and a second word having 7 bits therein, here denoted B, wherein:

The logic gates in 9/10 encoder 32' perform certain logic functions (given below) on byte A that effectively "maps" that 9-bit word into a 10-bit word, C, wherein:

following the requirements for the selected overall run length constraint (0, 6/6).

Output latch 34' interleaves word C with 7-bit word B to form a 17-bit codeword W which satisfies the (0,6/6) constraint, and which is denoted as:

Each codeword W includes two subsequences of alternating bits, W.sub.1 and W.sub.2, wherein the first subsequence W.sub.1 consists only of every other bit in a codeword W, and the second subsequence W.sub.2 consists of the remaining bits of that codeword W. The first subsequence W.sub.1 is denoted as an odd sequence because of having therein the bits from the odd numbered bit positions in codeword W wherein:

The remaining bits form the second subsequence W.sub.2 which is denoted as an even sequence wherein:

In order to ensure that each codeword W satisfies the (0, 6/6) constraint, the maximum number of consecutive zeros within each codeword W, and across the boundary between adjacent codewords W in a sequence thereof, is 6. Again, the maximum number of consecutive zeros within each subsequence W.sub.1 and W.sub.2, and (a) across the boundary between adjacent subsequences W.sub.1 in a sequence thereof, and (b) across the boundary between adjacent subsequences W in a sequence thereof, is 6. Since, again, it is undesirable to constrain the bits of word B (which would also effectively place a constraint on the user system since word B is not being encoded), it is necessary for 9/10 encoder 32' to map word A into word C such that, in the worst case scenario (when word B is all zeros), the codeword W will satisfy the (0, 6/6) constraint mentioned above. Since d=0, the following conditions ensure that the "k" and "i" constraints are satisfied within each codeword and between consecutive codewords:

Equations 50 and 51 above ensure that the k=6 constraint is satisfied at the boundary between codeword W and codewords adjacent thereto since a 1 value for any of C.sub.9, C.sub.8, and C.sub.7 of a codeword W.sub.n and bits C.sub.1 and C.sub.0 of codeword W.sub.n.+-.1 (see equation 47 above) effectively limits the length of a string of zeros possible over any 6 consecutive bits (assuming the worst case scenario where word B is zero) across the boundary between codeword W.sub.n and either of adjacent codewords W.sub.n.+-.1. Equations 52.+-.55 ensure that within each codeword W the k=6 constraint is satisfied, since a 1 value of any of bits C.sub.8, C.sub.7, C.sub.6, C.sub.5, C.sub.4, C.sub.3, C.sub.2 and C.sub.1 of codeword W (equation 47) effectively limits the length of a string of zeros possible over any 6 consecutive bits (assuming the worst scenario where word B is al zeros) within that codeword. Equation 54, in combination with equations 50 and 51, ensures that within each odd subsequence W.sub.1 and each even subsequence W.sub.2, and at the boundary between each successive pair of odd subsequence W.sub.1, and between each successive pair of even subsequence W.sub.2, the i=6 constraint is satisfied, since, a 1 value for any of bits C.sub.9, C.sub.8, C.sub.7, C.sub.1 and C.sub.0 of a codeword W effectively limits the length of a string of zeros possible over any 6 consecutive bits within such subsequences, and over any 6 consecutive bits bridging across the boundary between an odd subsequence W.sub.1:n and the subsequences W.sub.1:n.+-.1 adjacent thereto, and between an even subsequence W.sub.2:n and the subsequences W.sub.2:n.+-.1 adjacent thereto.

There are 524 different 10-bit patterns which satisfy the conditions in equations 50-56, which is more than the necessary number of 512 (i.e. 2.sup.9) for all possible 9-bit patterns. FIGS. 5A and 5B show a table representing a one-to-one mapping of any possible value of a 9-bit word A, taken as a three digit hexadecimal number, into the corresponding 10-bit word C, taken as a three digit hexadecimal number, such that equations 50-56 are satisfied. The bit patterns are shown in hexadecimal form in FIG. 4 for simplicity with the least significant (LS) digit in the word A hexadecimal number represented in the top line and the two most significant (MS) digits represented in the leftmost column of the table of FIGS. 5A and 5B.

In order to simplify the implementations of 9/10 encoder 32', the 512 different values for 10-bit initial words C shown in the table of FIGS. 5A and 5B can be grouped into eight partitions thereof, G, H, J, K, L, M, P and Q, as shown in FIG. 6 among possible partitioning schemes. In other words, FIG. 6 is a diagram of the table of FIGS. 5A and 5B in which the various partitions denoted by one of the capital letters G, H, J, K, L, M, N, P and Q represent groups of 10-bit C words having a predetermined relationship to each other described below. All of the definitions of the logic structure of 9/10 encoder 32' can again be expressed in Boolean logic expressions wherein ".multidot." denotes an AND gate, "+" denotes an OR gate, .sym. denotes as exclusive OR gate, and " " denotes a NOT gate.

Referring to FIG. 6, eight partitions of word assignments are identified by Boolean logic expressions as follows:

The logical equations for 9/10 encoder 32' for encoding data bits A.sub.8 -A.sub.0 into word bits C.sub.9 -C.sub.0 are given by the following equations utilizing the eight partitions equations G, H, J, K, L, M, N, P and Q described above in equations 57-64:

Referring to FIG. 4, decoder 24' functions to reconstruct the original data bits A.sub.8 -A.sub.0 and B.sub.6 -B.sub.0 from the codewords W.sub.n Decoder logic gating 24' identifies the same partition groups as those used in the encoder (see FIG. 6). Each partition group in 10/9 decoder 54' can be expressed as a function of code bits C.sub.9 -C.sub.0 as follows:

The Boolean logic equations for 10/9 decoder 54' for decoding code bits C.sub.9 -C.sub.0 into data bits A.sub.7 -A.sub.0 are given by the following equations utilizing the eight partition equations G, H, I, J. K, L and M described above in equations 75-82:

Those skilled in the art will recognize that other partitions may be chosen, and that further reduced Boolean expressions or other equivalent expressions, may be obtained from the present logic expressions described in equations 57-91, and thus that there are other possible logic equations for both 9/10 encoder 32' and 10/9 decoder 54'.

Although the present invention has been described with reference to preferred embodiments involving a 16/17 rate RLL code under a (0, 8/6) constraint and a 16/17 rate RLL code under a (0, 6/6) constraint, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.