Variable color complementary display device using anti-parallel light emitting diodes

[0002] This relates to my copending application Ser. No. 09/109,948, filed on Jul. 6, 1998, entitled Continuously Variable Color Display System, which is a division of my application Ser. No. 08/910,080, filed on Aug. 12, 1997, entitled Variable Color Display System, which is a division of my application Ser. No. 08/571,246, filed on Dec. 12, 1995, entitled Variable Color Display System, now U.S. Pat. No. 5,656,935 issued on Aug. 12, 1997, which is a division of my application Ser. No. 08/187,350, filed on Jan. 27, 1994, entitled Variable Color Digital Multimeter, now U.S. Pat. No. 5,475,300 issued on Dec. 12, 1995, which is a division of my application Ser. No. 07/865,460, filed on Apr. 9, 1992, entitled Variable Color Digital Multimeter, now U.S. Pat. No. 5,283,517 issued on Feb. 1, 1994, which is a division of my application Ser. No. 07/628,328, filed on Dec. 14, 1990, entitled Variable Color Digital Multimeter, now U.S. Pat. No. 5,122,733 issued on Jun. 16, 1992, which is a division of my application Ser. No. 07/197,322, filed on May 23, 1988, entitled Variable Color Digital Multimeter, now abandoned, which is a division of my application Ser. No. 06/819,111, filed on Jan. 15, 1986, entitled Variable Color Digital Multimeter, now U.S. Pat. No. 4,794,383 issued on Dec. 27, 1988.

[0003] Reference is also made to my related applications Ser. No. 06/817,114, filed on Jan. 8, 1986, entitled Variable Color Digital Timepiece, now U.S. Pat. No. 4,647,217 issued on Mar. 3, 1987, Ser. No. 06/919,425, filed on Oct. 16, 1986, entitled Electronic Timepiece with Transducers, now U.S. Pat. No. 4,687,340 issued on Aug. 18, 1987, Ser. No. 06/926,511, filed on Nov. 3, 1986, entitled Electronic Timepiece with Physical Transducer, now U.S. Pat. No. 4,705,406 issued on Nov. 10, 1987, Ser. No. 07/150,913, filed on Feb. 1, 1988, entitled Variable Color Display Typewriter, now U.S. Pat. No. 4,824,269 issued on Apr. 25, 1989, Ser. No. 07/336,080, filed on Apr. 11, 1989, entitled Variable Color Display Typewriter, now U.S. Pat. No. 4,934,852 issued on Jun. 19, 1990, Ser. No. 06/839,526, filed on Mar. 14, 1986, entitled Variable Color Display Telephone, now U.S. Pat. No. 4,726,059 issued on Feb. 16, 1988, Ser. No. 06/940/100, filed on Dec. 10, 1986, entitled Digital Voltmeter with Variable Color Background, now U.S. Pat. No. 4,831,326 issued on May 16, 1989, Ser. No. 06/882,430, filed on Jul. 7, 1986, entitled Display Device with Variable Color Background, now U.S. Pat. No. 4,734,619 issued on Mar. 29, 1988, Ser. No. 07/518,779, filed on May 4, 1990, entitled Measuring Device with Variable Color Background, now U.S. Pat. No. 5,003,247 issued on Mar. 26, 1991, Ser. No. 07/528,229, filed on May 24, 1990, entitled Measuring Device with Variable Color Display, now U.S. Pat. No. 5,057,768 issued on Oct. 15, 1991, Ser. No. 08/422,090, filed on Mar. 31, 1995, entitled Digital Color Display System, now U.S. Pat. No. 5,561,365 issued on Oct. 1, 1996, Ser. No. 06/922,847, filed on Oct. 24, 1986, entitled Continuously Variable Color Display Device, now U.S. Pat. No. 4,845,481 issued on Jul. 4, 1989, Ser. No. 07/322,341, filed on Mar. 13, 1989, entitled Continuously Variable Color Optical Device, now U.S. Pat. No. 4,965,561 issued on Oct. 23, 1990, Ser. No. 07/379,616, filed on Jul. 14, 1989, entitled Variable Color Digital Display for Emphasizing Position of Decimal Point, now U.S. Pat. No. 5,003,298 issued on Mar. 26, 1991, Ser. No. 06/925,543, filed on Oct. 31, 1986, entitled Variable Color Complementary Display Device, now U.S. Pat. No. 4,804,890, issued on Feb. 14, 1989, Ser. No. 06/920,740, filed on Oct. 20, 1986, entitled Step Variable Color Display Device, now abandoned, Ser. No. 06/931,626, filed on Nov. 17, 1986, entitled Variable Color Hybrid Display Device, now abandoned, Ser. No. 07/157,603, filed on Feb. 19, 1988, entitled Variable Color Multiplexed Display System, now abandoned, and Ser. No. 07/000,478, filed on Jan. 5, 1987, entitled Variable Color Digital Tachometer, now abandoned, which describe the devices employing a variable color display.

[0004] 1. Field of the Invention

[0005] This invention relates to a variable color complementary display device.

[0006] 2. Description of the Prior Art

[0007] A display device described in U.S. Pat. No. 3,740,570, issued on Jun. 19, 1973 to George R. Kaelin et al., uses special LEDs that exhibit different colors when subjected to different currents. The LEDs are biased by pulses of different amplitudes, to achieve different colors of the display, and by the length inversely proportional to the pulse amplitude, to compensate for variable brightness of the display caused by different amplitudes of the pulses.

[0008] A circuit employing a dual-color LED driven by a dual timer is described in the article by Bill Wagner entitled 2-color LED+driver=versatile visual effects, published on Oct. 2, 1980 in EDN volume 25, No. 19, page 164. Since dual-color LEDs are connected to conduct currents in opposite directions, it would be impossible to forwardly bias them simultaneously.

[0009] A luminescent solid state status indicator is disclosed in U.S. Pat. No. 3,873,979 issued on Mar. 25, 1975 to Magnus G. Craford et al. The status indicator includes two light emitting diodes inverted in parallel, which may be of different colors or of the same color.

[0010] An electronic display having segments wherein each segment is capable of selectively illuminating two colors is disclosed in U.S. Pat. No. 4,488,149 issued on Dec. 11, 1984 to William A. Givens, Jr. Two AND gates are provided for biasing, in each display segment, either a first light emitting diode, for emitting a first color, or a second light emitting diode, for emitting a second color. It is not contemplated to illuminate both light emitting diodes in each segment simultaneously for blending the colors.

[0011] A multi-color LED display for seven segment figures is disclosed in German Patent No. 3,009,416 issued on Sep. 17, 1981 to Klaus Gillessen. The LED circuit consists of seven group of diodes, each group made up of two diodes, one red and one green. The cathodes of all red diodes are terminated in a common connection, and the green ones likewise, the anodes of each pair of diodes being common for that pair. Two transistors connected in cascade are utilized for activating either all green LEDs, or all red LEDs, but not both simultaneously. When a low level signal is applied to the base of the first transistor, the first transistor is blocked, and the second transistor is turned ON to illuminate the second set of the diodes. When a high level signal is applied to the input of the first transistor, the first transistor is turned ON, while the second transistor is blocked, whereby the first set of the diodes is illuminated. Since the first transistor cannot be simultaneously turned ON and OFF, it would be impossible to illuminate the two sets of the diodes simultaneously. In another embodiment is shown a multi-color LED display utilizing three sets of LEDs: red, green, and blue, which are respectively commonly. connected and may be activated by manual switches. It is not contemplated that the three sets of LEDs be activated in selective combinations to blend the colors.

[0012] A digital electrooptical display with anti-parallel light emitting diodes is disclosed in East German Patent No. 220,844 issued on Apr. 10, 1985 to Thomas Hoffmann et al. Two light emitting diodes for emitting light of different colors are connected in each segment back-to-back. Since the light emitting diodes are connected to conduct currents in opposite directions, it would be impossible to illuminate them simultaneously, because the opposite currents attempting to pass through a single conductor would cancel.

[0013] A method and apparatus for independent color control of alphanumeric display and background therefor are disclosed in U.S. Pat. No. 3,911,418, issued on Oct. 7, 1975 to Minoru Takeda. Two color control signals, for the foreground area and for the background area, are provided separately from a computer and are processed separately, by means of a foreground selector and background selector. The two color control signals are then merged at a CRT display in raster fashion.

[0014] An error detection for multi-segmented indicia display is disclosed in U.S. Pat. No. 4,301,450, issued on Nov. 17, 1981 to Gerald D. Smoliar. A contiguous “OFF” segment of one color is provided next to each “ON” segment so as to indicate unambiguously that each non-illuminated “ON” segment is in fact indicating “OFF”.

[0015] The prior art does not contemplate a variable color complementary display device using anti-parallel (back-to-back connected) light emitting diodes, on which a selective display unit may be exhibited in a desired color, by activating the display areas which correspond by their positions to the display unit, and on which the remaining display areas automatically illuminate in a complementary, or otherwise contrasting, color, without the need for conversion of the color control signals to complementary color control signals.

[0016] In a broad sense, it is the principal object of this invention to provide an improved variable color complementary display device.

[0017] It is another object of the invention to provide a variable color display device having improved readability of the exhibited display unit.

[0018] It is still another object of the invention to provide a variable color display device in which the display unit, exhibited in a selective color, is enhanced by a substantially complementary or otherwise contrasting color.

[0019] It is still another object of the invention to provide a variable color complementary display device for illuminating certain display areas in a selected color, and for automatically illuminating the remaining display areas in a color substantially complementary, without the need for converting the color control signals.

[0020] It is still another object of the invention to provide a variable color complementary display device using the pairs of anti-parallel (back-to-back connected) light emitting diodes of respective primary colors, the light emitting diodes in each pair being of the same color.

[0021] It is still another object of the invention to provide a variable color complementary display device including a decoder for developing output signals for illuminating the light emitting diodes in certain display areas in a display color, and for developing opposite output signals for illuminating the light emitting diodes in the remaining display areas in a complementary, or otherwise contrasting, color to the display color.

[0022] In summary, a variable color complementary display device of the invention includes a plurality of display areas arranged in a pattern for selectively exhibiting a plurality of display units. Each display area includes a plurality of pairs of light emitting diodes for emitting, when forwardly biased, light signals of respective primary colors and a device for combining the light signals in the display area to obtain a light signal of a composite color. Each pair includes a first light emitting diode and a second light emitting diode of the same color.

[0023] The invention resides in the anti-parallel connecting of the first light emitting diode and the second light emitting diode in each pair, such that their polarities are opposite. An activation device is provided for forwardly biasing the selective ones of the first light emitting diodes in the selected display areas, for illuminating them in a desired display color. As a result of the anti-parallel arrangement, a new and unexpected result is obtained: the second light emitting diodes in the remaining display areas are automatically illuminated in the remaining primary colors, resulting in a color which is substantially complementary to the display color. In the preferred embodiment, the activation device includes a decoder for developing active output signals, for selecting the display areas that correspond by their arrangement to the desired display unit, and for developing the opposite output signals, -for selecting the remaining display areas. The activation device further includes a plurality of buses, equal in number to the plurality of primary colors and respectively associated therewith, to which the first light emitting diodes are commonly coupled in accordance with their colors, for being forwardly biased when the respective bus is energized.

[0024] In the drawings in which are shown several possible embodiments of the invention,

[0025] FIG. 1 is a block diagram of a typical prior art monochromatic digital display system.

[0026] FIG. 2 is a generalized block diagram of a variable color digital display system for the practice of the present invention.

[0027] FIG. 3 is a block diagram of a step variable color display system.

[0028] FIG. 4 is a block diagram of a continuously variable color display system.

[0029] FIG. 5 is a block diagram of 2-primary color digital display.

[0030] FIG. 6 is a block diagram of 3-primary color digital display.

[0031] FIG. 7 is an enlarged detail of one digit of 2-primary color digital display.

[0032] FIG. 8 is an enlarged cross-sectional view of one display segment in FIG. 7, taken along the line 8—8.

[0033] FIG. 9 is an enlarged detail of one digit of 3-primary color digital display.

[0034] FIG. 10 is an enlarged cross-sectional view of one display segment in FIG. 9, taken along the line 10—10.

[0035] FIG. 11 is a schematic diagram of one digit of two-primary color control circuit of this invention.

[0036] FIG. 12 is a schematic diagram of one digit of 3-primary color control circuit of this invention.

[0037] FIG. 13 is a block diagram of a color control logic circuit for controlling 2-primary color display.

[0038] FIG. 14 is a block diagram of a color control logic circuit for controlling 3-primary color display.

[0039] FIG. 15 is a schematic diagram of a color control logic circuit for controlling 2-primary color display.

[0040] FIG. 16 is a schematic diagram of a color control logic circuit for controlling 3-primary color display.

[0041] FIG. 17 is a simplified schematic diagram, similar to FIG. 11, showing how the number ‘7’ can be displayed in three different colors.

[0042] FIG. 18 is a simplified schematic diagram, similar to FIG. 12, showing how the number ‘1’ can be displayed in seven different colors.

[0043] FIG. 19 is a block diagram of 2-primary color 4-digit display.

[0044] FIG. 20 is a block diagram of 3-primary color 4-digit display.

[0045] FIG. 21 is a block diagram of a signal converter for 2-primary color display.

[0046] FIG. 22 is a block diagram of a signal converter for 3-primary color display.

[0047] FIG. 23 is a schematic diagram of a comparator circuit for 2-primary color display.

[0048] FIG. 24 is a graph showing the relationship between the inputs and outputs of the comparator circuit in FIG. 23.

[0049] FIG. 25 is a schematic diagram of a comparator circuit for 3-primary color display.

[0050] FIG. 26 is a graph showing the relationship between the inputs and outputs of the comparator circuit in FIG. 25.

[0051] FIG. 27 is a block diagram of a continuously variable color display system utilizing two primary colors.

[0052] FIG. 28 is a block diagram of a continuously variable color display system utilizing three primary colors.

[0053] FIG. 29 is an expanded block diagram of FIG. 27.

[0054] FIG. 30 is an expanded block diagram of FIG. 28.

[0055] FIG. 31 is a schematic diagram of a scaling circuit.

[0056] FIG. 32 is a schematic diagram of an A/D converter and memory combination of FIGS. 29 and 30.

[0057] FIG. 33 is a schematic diagram of a memory and color converter combination of FIG. 29.

[0058] FIG. 34 is a timing diagram of the circuit shown in FIG. 33.

[0059] FIG. 35 is a schematic diagram of a memory and color converter combination of FIG. 30.

[0060] FIG. 36 is a timing diagram of the circuit shown in FIG. 35.

[0061] FIG. 37 is a continuation of the timing diagram of FIG. 36.

[0062] FIG. 38 is a graphic representation of TABLE 1.

[0063] FIG. 39 is a graphic representation of TABLE 2.

[0064] FIG. 40 is a graph of the ICI chromaticity diagram.

[0065] FIG. 41 is a schematic diagram of one digit variable color complementary display device of this invention.

[0066] FIG. 42 is an enlarged cross-sectional view of one display segment in FIG. 41, taken along the line 42—42.

[0067] Throughout the drawings, like characters indicate like parts.

[0068] In the tables which show examples of the relationship between an input voltage, memory contents, and resulting color in the color converter of the present invention,

[0069] TABLE 1 shows the characteristic of a step variable 2-primary color converter.

[0070] TABLE 2 shows a rainbow-like characteristic of a continuously variable 3-primary color converter.

[0071] Throughout the tables, memory addresses and data are expressed in a well known hexadecimal notation.

[0072] Referring now, more particularly, to the drawings, in FIG. 1 is shown a block diagram of a typical prior art digital display system which usually includes a device 10afor developing digital data, a suitable decoder 20 for converting the digital data into a displayable code, and a monochromatic digital display 30 for indicating the digital data visually.

[0073] As shown in FIG. 2, the present invention resides in the substitution of a commercially well known monochromatic digital display with a variable color digital display 40, and in the addition of a color control circuit 50 for controlling the color of display 40. The variable color digital display system of this invention can simultaneously indicate the values of two different quantities, from the outputs of respective devices 10b, 10c, by causing the value of the first quantity to be indicated on display 40 in digital format, and by controlling the color of display 40 in accordance with the value of the second quantity.

[0074] In FIG. 3 is shown a block diagram of another embodiment of a variable color digital display system of the present invention, characterized by a step variable color control circuit 51.

[0075] In FIG. 4 is shown a block diagram of still another embodiment of variable color digital display system, characterized by a continuously variable color control circuit 56.

[0076] In FIG. 5 is shown a block diagram of a 2-primary color display system including a commercially well known 7-segment display decoder driver 22, a variable color 7-segment display element 42, and a 2-primary color control logic circuit 52. The decoder driver 22 accepts a 4-bit BCD (binary coded decimal) code at its inputs A0, A1, A2, A3 and develops output drive signals at its outputs a, b, c, d, e, f, g, and DP (decimal point) to drive respective segments of 7-segment display element 42. The color control circuit 52 accepts color control logic signals at its inputs R (red), Y (yellow), and G (green) and develops at its outputs drive signals for red bus 5 and green bus 6, respectively, to illuminate display element 42 in a selected color.

[0077] In FIG. 6 is shown a block diagram of a 3-primary color display system including a 7-segment display decoder driver 22, variable color 7-segment display element 43, and a 3-primary color control logic circuit 53. The color control circuit 53 accepts color control logic signals at its inputs R (red), Y (yellow), G (green), BG (blue-green), B (blue), P (purple), and W (white) and develops at its outputs drive signals for red bus 5, green bus 6, and blue bus 7, respectively, to illuminate display element 43 in a selected color.

[0078] In FIG. 7, the 2-primary color display element includes seven elongated display segments a, b, c, d, e, f, and g, arranged in a conventional pattern, which may be selectively energized in different combinations to display the desired digits. Each display segment includes a pair of LEDs (light emitting-diodes): red LED 2 and green LED 3, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon each other to mix the colors. To facilitate the illustration, the LEDs are designated by segment symbols, e. g., the red LED in the segment a is designated as 2a, etc.

[0079] In FIG. 8, red LED 2eand green LED 3eare placed on the base of a segment body 15awhich is filled with a transparent light scattering material 16. When forwardly biased, LEDs 2eand 3eemit light signals of red and green colors, respectively, which are scattered within transparent material 16, thereby blending the red and green light signals into a composite light signal that emerges at the upper surface of segment body 15a. The color of the composite light signal may be controlled by varying the portions of the red and green light signals.

[0080] In FIG. 9, each display segment of the 3-primary color display element includes a triad of LEDs: red LED 2, green LED 3, and blue LED 4, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon one another to mix the colors.

[0081] In FIG. 10, red LED 2e, green LED 3e, and blue LED 4eare placed on the base of a segment body 15bwhich is filled with a transparent light scattering material 16. Red LEDs are typically manufactured by diffusing a p-n junction into a GaAsP epitaxial layer on a GaAs substrate; green LEDs typically use a GaP epitaxial layer on a GaP substrate; blue LEDs are typically made from SiC material.

[0082] When forwardly biased, LEDs 2e, 3e, and 4eemit light signals of red, green, and blue colors, respectively, which are scattered within transparent material 16, thereby blending the red, green, and blue light signals into a composite light signal that emerges at the upper surface of segment body 15b. The color of the composite light signal may be controlled by varying the portions of the red, green, and blue light signals.

[0083] In FIG. 11 is shown a schematic diagram of a 2-primary color common cathodes 7-segment display element 42 which can selectively display various digital fonts in different colors on display segments a, b, c, d, e, f, g, and DP (Decimal Point). The anodes of all red and green LED pairs are interconnected in each display segment and are electrically connected to respective outputs of a commercially well known common-cathode 7-segment decoder driver 23. The cathodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g, and 2iare interconnected to a common electric path referred to as a red bus 5. The cathodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3iare interconnected to a like common electric path referred to as a green bus 6.

[0084] The red bus 5 is connected to the output of a tri-state inverting buffer 63a, capable of sinking sufficient current to forwardly bias all red LEDs 2ato 2iin display element 42. The green bus 6 is connected to the output of a like buffer 63b. The two buffers 63a, 63bcan be simultaneously enabled by applying a low logic level signal to the input of inverter 64a, and disabled by applying a high logic level signal thereto. When buffers 63a, 63bare enabled, the conditions of red bus 5 and green bus 6 can be selectively controlled by applying suitable logic control signals to the bus control inputs RB (red bus) and GB (green bus), to illuminate display element 42 in a selected color. When the buffers 63a, 63bare disabled, both red bus 5 and green bus 6 are effectively disconnected to cause display element 42 to be completely extinguished.

[0085] In FIG. 12 is shown a schematic diagram of a 3-primary color common anodes 7-segment display element 43 which can selectively display digital fonts in different colors. The cathodes of all red, green, and blue LED triads in each display segment are interconnected and electrically connected to respective outputs of a commercially well known common anode 7-segment decoder driver 24. The anodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, and 2gare interconnected to form a common electric path referred to as a red bus 5. The anodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, and 3gare interconnected to form a like common electric path referred to as a green bus 6. The anodes of all blue LEDs 4a, 4b, 4c, 4d, 4e, 4f, and 4gare interconnected to form a like common electric path referred to as a blue bus 7.

[0086] The red bus 5 is connected to the output of a non-inverting tri-state buffer 62a, capable of sourcing sufficient current to illuminate all red LEDs 2ato 2gin display element 43. The green bus 6 is connected to the output of a like buffer 62b. The blue bus 7 is connected to the output of a like buffer 62c. The three buffers 62a, 62b, and 62ccan be simultaneously enabled, by applying a low logic level signal to the input of inverter 64b, and disabled by applying a high logic level signal thereto. When buffers 62a, 62b, and 62care enabled, the conditions of red bus 5, green bus 6, and blue bus 7 can be selectively controlled by applying valid combinations of logic level signals to the bus control inputs RB (red bus), GB (green bus), and BB (blue bus), to illuminate display element 43 in a selected color. When buffers 62a, 62b, and 62care disabled, red bus 5, green bus 6, and blue bus 7 are effectively disconnected to cause display element 43 to be completely extinguished.

[0087] In FIG. 13 is shown a logic circuit 69afor developing drive signals for red bus 5 and green bus 6, to control the color of display element 42 shown in FIG. 11. Two voltage levels, referred to as logic high and low, are used throughout the description of the digital circuits. The color of display element 42 may be controlled by applying valid combinations of logic level signals to its color control inputs R (red), Y (yellow), and G (green) . The logic circuit 69acombines the input signals in a logic fashion and develops output drive signals RB (red bus) and GB (green bus), for activating red bus 5 and green bus 6, respectively, of display element 42.

[0088] In FIG. 14 is shown a like logic circuit 69bfor developing drive signals for red bus 5, green bus 6, and blue bus 7, to control the color of display element 43 shown in FIG. 12. The color of display element 43 may be controlled by applying valid combinations of logic level signals to its color control inputs B (blue), P (purple), BG (blue-green), G (green), Y (yellow), W (white), and R (red). The logic circuit 69bcombines the input signals in a logic fashion and develops output drive signals RB (red bus), GB (green bus), and BB (blue bus), for activating red bus 5, green bus 6, and blue bus 7, respectively, of display element 43.

[0089] Exemplary schematic diagrams of the color control logic circuits shown in FIGS. 15 and 16 consider active high logic levels, which means that only the selected color control input is maintained at a high logic level, while all remaining color control inputs are maintained at a low logic level. The circuit in FIG. 15 is a detail of the color control logic circuit 69aemploying 2-input logic OR gates 60aand 60b, interposed between the color control inputs R, Y, G and bus control outputs RB, GB, in a manner which will become more apparent from the description below. A like circuit in FIG. 16 is a detail of the color control logic circuit 69bemploying 4-input logic OR gates 61a, 61b, and 61csimilarly interposed between the color control inputs B, P, BG, G, Y, W, R and bus control outputs RB, GB, BB. It will be obvious to those skilled in the art that other types of logic devices may be effectively used.

[0090] The operation of display element 42 shown in FIG. 11 will be now explained by the example of illuminating a digit ‘7’ in three different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 17. Any digit between 0 and 9 can be selectively displayed by applying the appropriate BCD code to the inputs A0, A1, A2, and A3 of common-cathode 7-segment decoder driver 23. The decoder driver 23 develops at its outputs a, b, c, d, e, f, g, and DP drive signals for energizing selected groups of the segments to thereby visually display the selected number, in a manner well known to those having ordinary skill in the art. To display decimal number ‘7’, a BCD code 0111 is applied to the inputs A0, A1, A2, and A3. The decoder driver 23 develops high voltage levels at its outputs a, b, and c, to illuminate equally designated segments a, b, and c, and low voltage levels at all remaining outputs (not shown), to extinguish all remaining segments d, e, f, and g. To illuminate display element 42 in red color, the color control input R is raised to a high logic level, and the color control inputs Y and G are maintained at a low logic level. As a result, the output of OR gate 60arises to a high logic level, thereby causing the output of buffer 63ato drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2aand red bus 5, to current sinking output of buffer 63a. Similarly, the current flows from the output b of decoder driver 23, via red LED 2band red bus 5, to the output of buffer 63a. The current flows from the output c of decoder driver 23, via red LED 2cand red bus 5, to the output of buffer 63a. As a result, segments a, b, and c illuminate in red color, thereby causing a visual impression of a character ‘7’. The green LEDs 3a, 3b, 3cremain extinguished because the output of buffer 63bis at a high logic level, thereby disabling green bus 6.

[0091] To illuminate display element 42 in green color, the color control input G is raised to a high logic level, while the color control inputs R and Y are maintained at a low logic level. As a result, the output of OR gate 60brises to a high logic level, thereby causing the output of buffer 63bto drop to a low logic level. The current flows from the output a of decoder driver 23, via green LED 3aand green bus 6, to current sinking output of buffer 63b. Similarly, the current flows from the output b of decoder driver 23, via green LED 3band green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via green LED 3cand green bus 6, to the output of buffer 63b. As a result, segments a, b, and c illuminate in green color. The red LEDs 2a, 2b, and 2cremain extinguished because the output of buffer 63ais at a high logic level, thereby disabling red bus 5.

[0092] To illuminate display element 42 in yellow color, the color control input Y is raised to a high logic level, while the color inputs R and G are maintained at a low logic level. As a result, the outputs of both OR gates 60aand 60brise to a high logic level, thereby causing the outputs of both buffers 63aand 63bto drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2aand red bus 5, to current sinking output of buffer 63a, and, via green LED 3aand green bus 6, to current sinking output of buffer 63b. Similarly, the current flows from the output b of decoder driver 23, via red LED 2band red bus 5, to the output of buffer 63a, and, via green LED 3band green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via red LED 2cand red bus 5, to the output of buffer 63a, and, via green LED 3cand green bus 6, to the output of buffer 63b. As a result of blending light of red and green colors in each segment, segments a, b, and c illuminate in substantially yellow color.

[0093] The operation of display element 43 shown in FIG. 12 will be now explained by the example of illuminating a digit ‘1’ in seven different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 18. To display decimal number ‘1’, a BCD code 0001 is applied to the inputs A0, A1, A2, and A3 of common anode 7-segment decoder driver 24. The decoder driver 24 develops low voltage levels at its outputs b and c, to illuminate equally designated segments b and c, and high voltage levels at all remaining outputs (not shown), to extinguish all remaining segments a, d, e, f, and g.

[0094] To illuminate display element 43 in red color, the color control input R is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of OR gate 61arises to a high logic level, thereby causing the output of buffer 62ato rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. As a result, segments b and c illuminate in red color, thereby causing a visual impression of a character ‘1’. The green LEDs 3b, 3cand blue LEDs 4b, 4cremain extinguished because green bus 6 and blue bus 7 are disabled.

[0095] To illuminate display element 43 in green color, the color control input G is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of OR gate 61brises to a high logic level, thereby causing the output of buffer 62bto rise to a high logic level. The current flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. As a result, segments b and c illuminate in green color.

[0096] To illuminate display element 43 in blue color, the color control input B is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of OR gate 61crises to a high logic level, thereby causing the output of buffer 62cto rise to a high logic level. The current flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result, segments b and c illuminate in blue color.

[0097] To illuminate display element 43 in yellow color, the color control input Y is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61aand 61brise to a high logic level, thereby causing the outputs of buffers 62aand 62bto rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. As a result of blending light of red and green colors in each segment, the segments b and c illuminate in substantially yellow color.

[0098] To illuminate display element 43 in purple color, the color control input P is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61aand 61crise to a high logic level, thereby causing the outputs of buffers 62aand 62cto rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red and blue colors in each segment, segments b and c illuminate in substantially purple color.

[0099] To illuminate display element 43 in blue-green color, the color control input BG is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61band 61crise to a high logic level, thereby causing the outputs of buffers 62band 62cto rise to a high logic level. The current flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of green and blue colors in each segment, segments b and c illuminate in substantially blue-green color.

[0100] To illuminate display element 43 in white color, the color control input W is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a, 61b, and 61crise to a high logic level, thereby causing the outputs of respective buffers 62a, 62b, and 62cto rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red, green, and blue colors in each segment, segments b and c illuminate in substantially white color.

[0101] Since the outputs of decoder driver 24 may be overloaded by driving a triad of LEDs in parallel in display element 43, rather than a single LED in a monochromatic display, it would be obvious to employ suitable buffers to drive respective color display segments (not shown).

[0102] To illustrate how the present invention can be utilized in a multi-element variable color display configuration, in FIG. 19 is shown a detail of the interconnection in a 2-primary color 4-digit display having display segments 1a, 1b, 1c, and 1darranged in a 7-segment font. The color control inputs R, Y, and G of color controls 52a, 52b, 52c, and 52dof all display elements 46a, 46b, 46c, and 46dare interconnected, respectively, and enable inputs E1, E2, E3, and E4 are used to control the conditions of respective display elements 46a, 46b, 46c, and 46d. A high logic level at the enable input E extinguishes the particular display element 46a,. 46b, 46c, or 46d; a low logic level therein illuminates display element 46a, 46b, 46c, or 46din a color determined by the instant conditions of the color control inputs R, Y, and G.

[0103] In FIG. 20 is shown a like detail of the interconnection in a 3-primary color 4-digit display having display segments 1a, 1b, 1c, and 1darranged in a 7-segment font. Similarly, the color control inputs B, P, BG, G, Y, W, and R of color controls 53a, 53b, 53c, and 53dof all display elements 47a,47b,47c, and 47dare interconnected, and the conditions of respective display elements 47a,47b,47c, and 47dare controlled by enable inputs E1, E2, E3, and E4. A high logic level at the enable input E extinguishes the particular display element 47a,47b,47c, or 47d; a low logic level therein illuminates display element 47a,47b,47c, or 47din a color determined by the instant conditions of the color control inputs B, P, BG, G, Y, W, and R.

[0104] The exemplary color control circuits described herein will cooperate equally well with a multi-element variable color display constructed either in common cathodes or in common anodes configuration.

[0105] The enable inputs E1, E2, E3, E4 may be utilized to control the variable color multi-digit display in a multiplexed configuration, wherein the color codes for the display digits are presented in a sequence, one at a time, at a relatively fast rate, while the particular display digit is enabled.

[0106] In FIG. 21 is shown a block diagram of a signal converter for developing color control logic signals for 2-primary color display. The signal converter 85aaccepts at its input voltage from a variable analog voltage source 11 and develops at its outputs color control logic signals R, Y, G, having relation to the magnitude of instant input analog voltage, for controlling the color of variable color display element 42, shown in FIGS. 11 and 15, in accordance with the magnitude of input voltage.

[0107] In FIG. 22 is shown a block diagram of a like signal converter for developing color control logic signals for 3-primary color display. The signal converter 85baccepts at its inputs voltage from source 11 and develops output color control logic signals B, P. BG, G. Y. W. R. related to the magnitude of instant input analog voltage, for controlling the color of variable color display element 43, shown in FIGS. 12 and 16, in accordance with the magnitude of input voltage.

[0108] In FIG. 23, the output voltage of variable analog voltage source 11 is applied to interconnected inputs of two analog comparators 82a, 82b, in a classic ‘window’ comparator configuration. When the voltage developed by source 11 is lower than the low voltage limit Vlo, set by a potentiometer 92a, the output of comparator 82adrops to a low logic level, thereby forcing the output of inverter 65ato rise to a high logic level, to activate the color control logic input Y, to thereby illuminate display element 42, shown in FIGS. 11 and 15, in yellow color.

[0109] When the voltage developed by source 11 is higher than the high voltage limit Vhi, set by a potentiometer 92b, the output of comparator 82b. drops to a low logic level, thereby forcing the output of inverter 65bto rise to a high logic level, to activate the color control logic input R, to thereby illuminate display element 42 in red color.

[0110] When the voltage developed by source 11 is between the low voltage limit Vlo and high voltage limit Vhi, the outputs of comparators 82a, 82brise to a high logic level, thereby causing the output of AND gate 66 to rise to a high logic level, to activate the color control logic input G, to thereby illuminate display element 42 in green color.

[0111] FIG. 24 is a graph depicting the relationship between the input voltage of the comparator circuit shown in FIG. 23 and the color of the display element shown in FIG. 11. The display element illuminates in yellow color for the input voltage lower than the limit Vlo, in green color for the input voltage between the limits Vlo and Vhi, and in red color for the input voltage higher than the limit Vhi.

[0112] In FIG. 25, the output voltage of variable analog voltage source 11 is applied to interconnected ‘+’ inputs of six analog comparators 82c, 82d, 82e, 82f, 82g, 82h, connected in a well known ‘multiple aperture window’ configuration. There are six progressively increasing voltage limits V1 to V6, set by respective potentiometers 92cto 92h. The outputs of comparators 82cto 82hare respectively connected, via inverters 65cto 65h, to the inputs I1 to I7 of a priority encoder 67. Each of the inputs I1 to I7 has assigned a certain priority (from I1 being the lowest priority progressively to I7 being the highest one). The priority encoder 67 develops at its outputs 00, 01, 02 a code identifying the highest priority input activated. The outputs of encoder 67 are respectively connected, via inverters 65jto 65m, to the inputs A0, A1, A2 of a 3-to-8 line decoder 68, to decode the outputs of encoder 67 into seven mutually exclusive active logic low outputs Y1 to Y7. The outputs Y1 to Y7 are respectively connected, via inverters 65pto 65v,to the color control logic inputs B, P, BG, G, Y, W, R of display element 43 shown in FIGS. 12 and 16.

[0113] When the output voltage of source 11 is lower than the lowest voltage limit V1, the output of comparator 82cdrops to a low logic level, thereby activating the input I1 of priority encoder 67. The code 110 developed at the outputs 00, 01, 02 is inverted by inverters 65jto 65mto yield the code 001 which produces a low logic level at the output Y1, to force, via inverter 65p,the color control input B to a high logic level for causing display element 43 to illuminate in blue color.

[0114] When the output voltage of the source 11 is between the adjacent voltage limits, e. g., V4 and V5, the output of comparator 82frises to a high logic level, thereby activating the input I5 of priority encoder 67. The code 100 developed at the inputs of decoder 68 produces a high logic level at the color control logic input Y, and display element 43 illuminates in yellow color.

[0115] FIG. 26 is a graph depicting the relationship between the input voltage of the comparator circuit shown in FIG. 25 and the color of display element 42 shown in FIG. 12. The display element illuminates in blue color for the input voltage lower than the limit V1, in purple color for the input voltage between the limits V1 and V2, in blue-green color for the input voltage between the limits V2 and V3, in green color for the input voltage between the limits V3 and V4, in yellow color for the input voltage between the limits V4 and V5, in white color for the input voltage between the limits V5 and V6, and in red color for the input voltage higher than the limit V6.

[0116] It would be obvious to those having ordinary skill in the art, in the view of this disclosure, that the color sequences could be readily changed by differently interconnecting the outputs of the comparator circuit with the color control logic inputs of display element 43.

[0117] FIG. 27 is a block diagram of a 2-LED continuously variable color display system, which includes a device 10 for developing electric signals and 2-LED color converter 57 for controlling red bus 5 and green bus 6, respectively, of 2-LED variable color display element 42 in accordance with the electric signals.

[0118] FIG. 28 is a block diagram of a 3-LED continuously variable color display system which differs from the like system shown in FIG. 27 in that a 3-LED color converter circuit 58 is utilized to control red bus 5, green bus 6, and blue bus 7, respectively, of 3-LED variable color display element 43, in accordance with the electric signals developed by device 10.

[0119] The display system shown in FIG. 29 utilizes a scaling circuit 80awhich scales input analog voltage levels to a voltage range suitable for an A/D converter 74a, which in turn develops at its outputs a digital code having relation to the value of the input analog voltage. The output lines of A/D converter 74aare connected to the address inputs of a memory 76 having a plurality of addressable locations which contain data indicating the portions of red color for several different values of the input analog voltage. The output data of memory 76 are applied to the inputs of a color converter 57 which will develop control signals for red bus 5 and green bus 6, respectively, of variable color display element 42.

[0120] The display system shown in FIG. 30 utilizes a scaling circuit 80band an A/D converter 74bfor converting the instant value of an input analog voltage to a digital code. The outputs of A/D converter 74bare connected, in parallel, to the address inputs of memory 76a, which contains data indicating the portions of red color, to the address inputs of memory 76b, which contains data indicating the portions of green color, and to the address inputs of memory 76c, which contains data indicating the portions of blue color. The output data of memory 76aare applied to red color converter 59awhich will develop control signals for red bus 5 of variable color display element 43. The output data of memory 76bare applied to green color converter 59bwhich will develop control signals for green bus 6 of display element 43. The output data of memory 76care applied to blue color converter 59cwhich will develop control signals for blue bus 7 of display element 43.

[0121] FIG. 31 is a schematic diagram of a scaling circuit capable of shifting and amplifying the input voltage levels. The circuit utilizes two operational amplifiers 81aand 81bin a standard inverting configuration. The amplifier 81ais set for a unity gain by using resistors 90aand 90bof equal values; potentiometer 92ais adjusted to set a desired offset voltage. The amplifier 81bsets the gain by adjusting feedback potentiometer 92bto a desired value with respect to resistor 90c. As a result, an input voltage, which may vary between arbitrary limits Vlow and Vhigh, may be scaled and shifted to the range between 0 Volts and 9.961 Volts, to facilitate the use of a commercially available A/D converter.

[0122] FIG. 32 is a schematic diagram of an A/D (analog-to-digital) converter 75 which is capable of converting input analog voltage, applied via resistor 90eto its input Vin, to 8-bit digital data for addressing a memory 77. The conversion may be initiated from time to time by applying a short positive pulse 99ato the Blank and Convert input B&C. A/D converter 75 will thereafter perform a conversion of the instant input voltage to 8-bit data indicative of its value. When the conversion is completed, the Data Ready output DR drops to a low logic level, thereby indicating that the data are available at the outputs Bit 1 to Bit 8, which are directly connected to respective address inputs A0 to A7 of memory 77. When the DR output drops to a low logic level, the Chip Select input CS of memory 77 is activated, memory 77 is enabled, and the data, residing at the address selected by the instant output of A/D converter 75, will appear at its data outputs D0 to D7.

[0123] The description of the schematic diagram in FIG. 33 should be considered together with its accompanying timing diagram shown in FIG. 34. A clock signal 99bof a suitable frequency (e. g., 10 kHz), to provide a flicker-free display, is applied to the Clock Pulse inputs CP of 8-bit binary counters 71eand 71fto step them down. At the end of each counter cycle, which takes 256 clock cycles to complete, the Terminal Count output TC of counter 71edrops to a low logic level for one clock cycle, to thereby indicate that the lowest count was reached. The negative pulse 99cat the TC output of counter 71e, which is connected to the Parallel Load input PL of counter 71f, causes the instant data at the outputs of memory 76 to be loaded into counter 71f. The data at memory 76 represent the portion of red color; the portion of green color is complementary. The rising edge of the TC pulse 99ctriggers flip-flop 73 into its set condition wherein its output Q rises to a high logic level.

[0124] The counter 71fwill count down, from the loaded value, until it reaches zero count, at which moment its TC output drops to a low logic level. The negative pulse at the TC output of counter 71f, which is connected to the Clear Direct input CD of flip-flop 73, causes the latter to be reset and to remain in its reset condition until it is set again at the beginning of the next 256-count cycle. It is thus obvious that the Q output of flip-flop 73 is at a high logic level for a period of time proportional to the data initially loaded into counter 71f. The complementary output {overscore (Q)} is at a high logic level for a complementary period of time.

[0125] The Q and {overscore (Q)} outputs of flip-flop 73 are connected to red bus 5 and green bus 6, respectively, via suitable buffers 63aand 63b, shown in detail in FIG. 11, to respectively energize red bus 5 and green bus 6 for variable time periods, depending on the data stored in memory 76.

[0126] By referring now, more particularly, to the timing diagram shown in FIG. 34, in which the waveforms are compressed to facilitate the illustration, the EXAMPLE 1 considers the memory data ‘FD’, in a standard hexadecimal notation, to generate light of substantially red color. At the beginning of the counter cycle, pulse 99cloads data ‘FD’ into counter 71f. Simultaneously, flip-flop 73 is set by the rising edge of pulse 99c. The counter 71fwill be thereafter stepped down by clock pulses 99b, until it reaches zero count, 2 clock cycles before the end of the counter cycle. At that instant a short negative pulse 99dis produced at its output TC to reset flip-flop 73, which will remain reset for 2 clock cycles and will be set again by pulse 99cat the beginning of the next counter cycle, which will repeat the process. It is readily apparent that flip-flop 73 was set for 254 clock cycles, or about 99% of the time, and reset for 2 clock cycles, or about 1% of the time. Accordingly, red bus 5 of display element 42 is energized for about 99% of the time, and green bus 6 is energized for the remaining about 1% of the time. As a result, display element 42 illuminates in substantially red color.

[0127] The EXAMPLE 2 considers the memory data ‘02’ (HEX) to generate light of substantially green color. At the beginning of the counter cycle, data ‘02’ are loaded into counter 71f, and, simultaneously, flip-flop 73 is set. The counter 71fwill count down and will reach zero count after 2 clock cycles. At that instant it produces at its output TC a negative pulse 99eto reset flip-flop 73. It is readily apparent that flip-flop 73 was set for 2 clock cycles, or about 1% of the time, and reset for 254 clock cycles, or about 99% of the time. Accordingly, red bus 5 of display element 42 is energized for about 1% of the time, and green bus 6 is energized for the remaining about 99% of the time. As a result, display element 42 illuminates in substantially green color.

[0128] The EXAMPLE 3 considers the memory data ‘80’ (HEX) to generate light of substantially yellow color. At the beginning of the counter cycle, data ‘80’ are loaded into counter 71f, and, simultaneously, flip-flop 73 is set. The counter 71fwill count down and will reach zero count after 128 clock cycles. At that instant it produces at its output TC a negative pulse 99fto reset flip-flop 73. It is readily apparent that flip-flop 73 was set for 128 clock cycles, or about 50% of the time, and reset for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 42 is energized for about 50% of the time, and green bus 6 is energized for the remaining about 50% of the time. As a result of blending substantially equal portions of red and green colors, display element 42 illuminates in substantially yellow color.

[0129] The description of the schematic diagram of a 3-LED color converter in FIG. 35 should be considered together with its accompanying timing diagrams shown in FIGS. 36 and 37. A clock signal 99bis applied to the CP inputs of counters 71d, 71a, 71b, and 71cto step them down. Every 256 counts a negative pulse 99cis generated at the TC output of counter 71d, to load data into counters 71a, 71b, and 71cfrom respective memories 76a, 76b, and 76c, and to set flip-flops 73a, 73b, and 73c. The data in red memory 76arepresent the portions of red color, the data in green memory 76brepresent the portions of green color, and the data in blue memory 76crepresent the portions of blue color to be blended.

[0130] The counters 71a, 71b, and 71cwill count down, from the respective loaded values, until zero counts are reached. When the respective values of the loaded data are different, the length of time of the count-down is different for each counter 71a, 71b, and 71c. When a particular counter 71a, 71b, or 71creaches zero count, its TC output momentarily drops to a low logic level, to reset its associated flip-flop (red counter 71aresets its red flip-flop 73a, green counter 71bresets its associated green flip-flop 73b, and blue counter 71cresets its associated blue flip-flop 73c). Eventually, all three flip-flops 73a, 73b, and 73cwill be reset. The Q outputs of flip-flops 73a, 73b, and 73care connected to red bus 5, green bus 6, and blue bus 7, respectively, via suitable buffers 62a, 62b, and 62c, as shown in FIG. 12, to respectively energize red bus 5, green bus 6, and blue bus 7 for variable periods of time.

[0131] By referring now more particularly to the timing diagram shown in FIGS. 36 and 37, the EXAMPLE 4 considers red memory data ‘80’, green memory data ‘00’, and blue memory data ‘80’, all in hexadecimal notation, to generate light of substantially purple color. At the beginning of the counter cycle, pulse 99csimultaneously loads data ‘80’ from red memory 76ainto red counter 71a, data ‘00’ from green memory 76binto green counter 71b, and data ‘80’ from blue memory 76cinto blue counter 71c. The counters 71a, 71b, and 71cwill be thereafter stepped down. The red counter 71awill reach its zero count after 128 clock cycles; green counter 71bwill reach its zero count immediately; blue counter 71cwill reach its zero count after 128 clock cycles.

[0132] It is readily apparent that red flip-flop 73awas set for 128 clock cycles, or about 50% of the time, green flip-flop 73bwas never set, and blue flip-flop 73cwas set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 43 is energized for about 50% of the time, green bus 6 is never energized, and blue bus 7 is energized for about 50% of the time. As a result of blending substantially equal portions of red and blue colors, display element 43 illuminates in substantially purple color.

[0133] The EXAMPLE 5 considers red memory data ‘00’, green memory data ‘80’, and blue memory data ‘80’, to generate light of substantially blue-green color. At the beginning of the counter cycle, data ‘00’ are loaded into red counter 71a, data ‘80’ are loaded into green counter 71b, and data ‘80’ are loaded into blue counter 71c. The red counter 71awill reach its zero count immediately, green counter 71bwill reach its zero count after 128 clock periods, and so will blue counter 71c.

[0134] The red flip-flop 73awas never set, green flip-flop 73bwas set for 128 clock pulses, or about 50% of the time, and so was blue flip-flop 73c. Accordingly, green bus 6 of display element 43 is energized for about 50% of the time, and so is blue bus 7. As a result, display element 43 illuminates in substantially blue-green color.

[0135] The EXAMPLE 6 considers red memory data ‘40’, green memory data ‘40’, and blue memory data ‘80’, to generate light of substantially cyan color. At the beginning of the counter cycle, the data ‘40’ are loaded into red counter 71a, data ‘40’ are loaded into green counter 71b, and data ‘80’ are loaded into blue counter 71c. The red counter 71awill reach its zero count after 64 clock cycles, and so will green counter 71b. The blue counter 71cwill reach its zero count after 128 clock cycles.

[0136] The red flip-flop 73awas set for 64 clock cycles, or about 25% of the time, and so was green flip-flop 73b. The blue flip-flop 73cwas set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 and green bus 6 of display element 43 are energized for about 25% of the time, and blue bus 7 is energized for about 50% of the time. As a result of blending about 50% of blue color, 25% of red color, and 25% of green color, display element 43 illuminates in substantially cyan color.

[0137] The EXAMPLE 7 considers red memory data ‘80’, green memory data ‘40’, and blue memory data ‘40’, to generate light of substantially magenta color. At the beginning of the counter cycle, the data ‘80’ are loaded into red counter 71a, data ‘40’ are loaded into green counter 71b, and data ‘40’ are loaded into blue counter 71c. The red counter 71awill reach its zero count after 128 clock cycles, green counter 71bwill reach its zero count after 64 clock cycles, and so will blue counter 71c.

[0138] The red flip-flop 73awas set for 128 clock cycles, or about 50% of the time, green flip-flop 73band blue flip-flop 73cwere set for 64 clock cycles, or about 25% of the time. Accordingly, red bus 5 of display element 43 is energized for about 50% of the time, green bus 6 and blue bus 7 are energized for about 25% of the time. As a result, display element 43 illuminates in substantially magenta color.

[0139] By referring now more particularly to FIGS. 38 and 39, which are graphic representations of TABLES 1 and 2, respectively, the data at each memory address are digital representation of the portion of the particular primary color. All examples consider an 8-bit wide PROM (Programmable Read Only Memory) . However, the principles of the invention could be applied to other types of memories.

[0140] In FIG. 38, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color. The RED PORTION for a particular memory address was calculated by dividing the actual value of data residing at that address by the maximum possible data ‘FF’ (HEX) . The GREEN PORTION for the same memory address is complementary; it was obtained by subtracting the calculated value of the RED PORTION from number 1.0.

[0141] In FIG. 38 is shown the characteristic of a 2-primary color converter, defined in TABLE 1, for developing color variable in steps: pure green for input voltages less than 0.625 V, substantially yellow for voltages between 1.25 V and 1.875 V, pure red for voltages between 2.5 V and 3.125 V, and of intermediate colors therebetween, this sequence being repeated three times over the voltage range.

[0142] In FIG. 39, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color; BLUE PORTION indicates the portion of blue primary color. The RED PORTION for a particular memory address was calculated by dividing the value of red data residing at such address by the maximum possible data ‘FF’ (HEX). Similarly, the GREEN PORTION for that memory address was obtained by dividing the value of green data by ‘FF’ (HEX) . The BLUE PORTION was obtained by dividing the value of blue data by ‘FF’ (HEX).

[0143] In FIG. 39 is shown the characteristic of 3-primary color converter, defined in TABLE 2, for developing color continuously variable from pure red, through substantially orange and yellow, pure green, pure blue, to substantially purple, in a rainbow-like fashion.

[0144] In the examples of the characteristics of color converters shown in TABLE 1 and TABLE 2, the data values stored in red memory 76a, green memory 76b, and blue memory 76care so designed that the sums of the red data, green data, and blue data are constant for all memory addresses, to provide uniform light intensities for all colors. It is further contemplated that data stored in red memory 76a, green memory 76b, and blue memory 76cmay be modified, in order to compensate for different efficiencies of red, green, and blue LEDs. By way of an example, data values for a low efficiency LED may be proportionally incremented such that the time of energization is proportionally increased, to effectively provide equal luminances for LEDs of unequal efficiencies.

[0145] With reference to FIG. 40 there is shown the ICI (International Committee on Illumination) chromaticity diagram designed to specify a particular color in terms of x and y coordinates. Pure colors are located along the horseshoe-like periphery. Reference numbers along the periphery indicate wavelength in nanometers. When relative portions of three primary colors are known, the color of light produced by blending their emissions can be determined by examining the x and y values of ICI coordinates.

[0146] In FIG. 41 is shown schematic diagram of a preferred embodiment of a variable color complementary display device of the invention, which is capable of exhibiting a selected display unit, by illuminating the display areas that correspond by their positions to the selected display unit, in a selective display color, and of automatically illuminating the remaining display areas in a color which is substantially complementary to the display color, without the need for converting display color control signals to complementary color control signals. The invention is achieved by using anti-parallel (back-to-back) connected light emitting diodes of three primary colors in each display area of the display device, as will be pointed out subsequently.

[0147] It will be recalled that complementary colors are those colors that produce a neutral color when additively mixed in suitable proportions. Generally, red colors are complementary to blue-green colors, green colors are complementary to purple colors, and blue colors are complementary to yellow colors. However, it would be obvious to persons of ordinary skill, in the view of this disclosure, that the principles of the invention are also applicable to other contrasting colors.

[0148] In the schematic diagram in FIG. 41 is shown a 3 -primary color 7-segment display element 43bwhich can selectively exhibit digital fonts in different colors on display segments a, b, c, d, e, f, and g. Each display segment includes six LEDs: two anti-parallel red LEDs 2 and 2′, two anti-parallel green LEDs 3 and 3′, and two anti-parallel blue LEDs 4 and 4′, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon one another to mix the colors. To facilitate the illustration, the LEDs are designated by segment symbols, e. g., the two red LEDs in segment a are designated as 2aand 2a′, etc.

[0149] In the display segment a, the anode of red LED 2ais connected to the cathode of red LED 2a′, and the cathode of red LED 2ais connected to the anode of red LED 2a′. The two green LEDs 3aand 3a′ are similarly connected back-to-back. The two blue LEDs 4aand 4a′ are connected back-to-back in a similar fashion. In all remaining display segments b, c, d, e, f, and g, the pairs of LEDs of the same primary color are also connected back-to-back in the same fashion.

[0150] As a consequence of the back-to-back connecting of the light emitting diodes, each pair has two terminals which are functionally equivalent, because the rectifying effect of the light emitting diode has been practically eliminated. However, it may be advantageous for facilitating the description of the schematic diagram in FIG. 41, to refer to the interconnected terminals of the pair which are on the top of segments a, g, and d and on the right of segments b, c, e, and f, as the first terminals of the pairs. Similarly, the other terminals, on the bottom of segments a, g, and d and on the left of segments b, c, e, and f, will be referred to as the second terminals of the pairs.

[0151] The first terminals of the pairs of all red LEDs are commonly coupled to red bus 5, the first terminals of the pairs of all green LEDs are commonly coupled to green bus 6, and the first terminals of the pairs of all blue LEDs are commonly coupled to blue bus 7. Thus all LEDs in display element 43bare coupled to red bus 5, green bus 6, and blue bus 7 in accordance with their colors.

[0152] The second terminals of the pair of all three pairs of LEDs are interconnected in each display segment. The interconnected second terminals of the pairs in segment a are coupled, via current limiting resistor 36a, to the output of non-inverting buffer 33a, which has its input coupled to the output a of 7-segment decoder 24b.In a similar fashion, the interconnected second terminals in all remaining segments b, c, d, e, f, and g are respectively coupled to the remaining outputs b, c, d, e, f, and g of 7-segment decoder 24b, via respective current limiting resistors 36b, 36c, 36d, 36e, 36f, and 36g, and via the remaining non-inverting buffers 33b, 33c, 33d, 33e, 33f, and 33g. Thus all display segments a, b, c, d, e, f, and g are effectively coupled to the equally designated outputs of 7-segment decoder 24b, in accordance with their positions in display element 43b. The purpose of non-inverting buffers 33a, 33b, 33c, 33d, 33e, 33f, and 33gis to provide sufficient current needed for forwardly biasing all LEDs in display element 43b. The purpose of current limiting resistors 36a, 36b, 36c, 36d, 36e, 36f, and 36gis to constrain the current flow through the LEDs to provide uniform brightness.

[0153] The red bus 5 is connected to the output of a tri-state non-inverting buffer 34a, capable of sourcing or sinking sufficient current to forwardly bias all red LEDs 2ato 2gand 2a′ to 2g′ in display element 43b. The green bus 6 is connected to the output of a like tri-state non-inverting buffer 34b. The blue bus 7 is connected to the output of a like tri-state non-inverting buffer 34c.

[0154] The tri-state non-inverting buffers 34a, 34b, and 34ccan be simultaneously enabled by applying a low logic level signal to enable input E of an inverter 35, and disabled by applying a high logic level signal thereto. When tri-state non-inverting buffers 34a, 34b, and 34care jointly enabled, the conditions of red bus 5, green bus 6, and blue bus 7 can be selectively controlled by applying valid combinations of logic level signals to bus color control inputs RB (red bus), GB (green bus), and BB (blue bus), for illuminating display element 43bin a selected color. When tri-state non-inverting buffers 34a, 34b, and 34care jointly disabled, all three buses are effectively disconnected, and display element 43bis extinguished.

[0155] The operation of display element 43bshown in FIG. 41 will be now explained by the example of illuminating a digit ‘4’ in six different colors. To display decimal number ‘4’, a BCD code 0100 is applied to the inputs A0, A1, A2, and A3 of common anode 7-segment decoder 24b. The decoder 24bdevelops low voltage levels at its outputs c, f and g, thereby causing the outputs of non-inverting buffers 33c, 33f, and 33gto drop to a low logic level, and high voltage levels at all remaining outputs a, b, d, and e, thereby causing the outputs of non-inverting buffers 33a, 33b, 33d, and 33eto rise to a high logic level. As a consequence, as will be pointed out in more detail subsequently, the equally designated segments c, f, and g illuminate in a desired color, and the remaining segments a, b, d, and e automatically illuminate in a color substantially complementary to the desired color.

[0156] To illuminate display element 43bin red color, the bus color control input RB (red bus) is raised to a high logic level, while both remaining bus color control inputs GB (green bus) and BB (blue bus) are maintained at a low logic level. As a result, the output of buffer 34arises to a high logic level, while the outputs of buffers 34band 34cremain at a low logic level. The current flows from the output of buffer 34a, via red bus 5, red LED 2c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34a, via red bus 5, red LED 2f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34a, via red bus 5, red LED 2g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34a, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. As a result, segments c, f and g illuminate in red color, thereby causing a visual impression of a character ‘4’.

[0157] At the same time, current flows from the output of buffer 33a, via resistor 36a, green LED 3a, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33a, via resistor 36a, blue LED 4a, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33b, via resistor 36b, green LED 3b, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33b, via resistor 36b, blue LED 4b, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33d, via resistor 36d, green LED 3d, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33d, via resistor 36d, blue LED 4d, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33e, via resistor 36e, green LED 3e, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33e, via resistor 36e, blue LED 4e, and blue bus 7, to the output of buffer 34c. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the outputs of buffers 34band 34c, because these are also at a low logic level. As a consequence, segments a, b, d, and e illuminate in a substantially blue-green color, which is obtained by blending equal portions of blue and green light signals in each segment a, b, d, and e.

[0158] The overall effect is a visual impression of a character ‘4’ exhibited in red color on a background of a substantially blue-green color, which has an effect of enhancing the exhibited character and improve its readability, in a visually pleasing and harmonious manner.

[0159] To illuminate display element 43bin green color, the bus color control input GB is raised to a high logic level, while both remaining bus color control inputs RB and BB are maintained at a low logic level. As a result, the output of buffer 34brises to a high logic level, while the outputs of buffers 34aand 34cremain at a low logic level. The current flows from the output of buffer 34b, via green bus 6, green LED 3c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34b, via green bus 6, green LED 3f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34b, via green bus 6, green LED 3g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34b, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. As a result, segments c, f and g illuminate in green color, thereby causing a visual impression of a character ‘4’.

[0160] At the same time, current flows from the output of buffer 33a, via resistor 36a, red LED 2a, and red bus 5, to the output of buffer 34a. The current also flows from the output of 33a, via resistor 36a, blue LED 4a, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33b, via resistor 36b, red LED 2b, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33b, via resistor 36b, blue LED 4b, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33d, via resistor 36d, red LED 2d, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33d, via resistor 36d, blue LED 4d, and blue bus 7, to the output of buffer 34c. The current also flows from the output of 33e, via resistor 36e, red LED 2e, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33e, via resistor 36e, blue LED 4e, and blue bus 7, to the output of buffer 34c. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the outputs of buffers 34aand 34c, because these are also at a low logic level. As a consequence, segments a, b, d, and e illuminate in a substantially purple color, which is obtained by blending equal portions of red and blue light signals in each segment a, b, d, and e.

[0161] The overall effect is a visual impression of a character ‘4’ exhibited in green color on a background of a substantially purple color.

[0162] To illuminate display element 43bin blue color, the bus color control input BB is raised to a high logic level, while both remaining bus color control inputs RB and GB are maintained at a low logic level. As a result, the output of buffer 34crises to a high logic level, while the outputs of buffers 34aand 34bremain at a low logic level. The current flows from the output of buffer 34c, via blue bus 7, blue LED 4c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34c, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. As a result, segments c, f and g illuminate in blue color, thereby causing a visual impression of a character ‘4’.

[0163] At the same time, current flows from the output of buffer 33a, via resistor 36a, red LED 2a, and red bus 5, to the output of buffer 34a. The current also flows from the output of 33a, via resistor 36a, green LED 3a, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33b, via resistor 36b, red LED 2b, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33b, via resistor 36b, green LED 3b, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33d, via resistor 36d, red LED 2d, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33d, via resistor 36d, green LED 3d, and green bus 6, to the output of buffer 34b. The current also flows from the output of 33e, via resistor 36e, red LED 2e, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33e, via resistor 36e, green LED 3e, and green bus 6, to the output of buffer 34b. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the outputs of buffers 34aand 34b, because these are also at a low logic level. As a consequence, segments a, b, d, and e illuminate in a substantially yellow color, which is obtained by blending equal portions of red and green light signals in each segment a, b, d, and e.

[0164] The overall effect is a visual impression of a character ‘4’ exhibited, in blue color on a background of a substantially yellow color.

[0165] To illuminate display element 43bin yellow color, the bus color control inputs RB and GB are raised to a high logic level, while the remaining bus color control input BB is maintained at a low logic level. As a result, the outputs of buffers 34aand 34brise to a high logic level, while the output of buffer 34cremains at a low logic level. The current flows from the output of buffer 34a, via red bus 5, red LED 2c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34a, via red bus 5, red LED 2f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34a, via red bus 5, red LED 2g′, and resistor 36g, to the output of buffer 33g. The current flows from the output of buffer 34b, via green bus 6, green LED 3c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34b, via green bus 6, green LED 3f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34b, via green bus 6, green LED 3g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34a, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. For the same reason, the current cannot flow from the output of buffer 34b, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e. As a result of blending equal portions of red and green light signals in each segment, segments c, f and g illuminate in a substantially yellow color, thereby causing a visual impression of a character ‘4’.

[0166] At the same time, current flows from the output of buffer 33a, via resistor 36a, blue LED 4a, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33b, via resistor 36b, blue LED 4b, and blue bus 7, to the output of buffer 34c. The current also flows from the output of buffer 33d, via resistor 36d, blue LED 4d, and blue bus 7, to the output of buffer 34c. The current also flows from the output of 33e, via resistor 36e, blue LED 4e, and blue bus 7, to the output of buffer 34c. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the output of buffer 34c, because that is also at a low logic level. As a consequence, segments a, b, d, and e illuminate in blue color.

[0167] The overall effect is a visual impression of a character ‘4’ exhibited in a substantially yellow color on a background of blue color.

[0168] To illuminate display element 43bin purple color, the bus color control inputs RB and BB are raised to a high logic level, while the remaining bus color control input GB is maintained at a low logic level. As a result, the outputs of buffers 34aand 34crise to a high logic level, while the output of buffer 34bremains at a low logic level. The current flows from the output of buffer 34a, via red bus 5, red LED 2c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34a, via red bus 5, red LED 2f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34a, via red bus 5, red LED 2g′, and resistor 36g, to the output of buffer 33g. The current flows from the output of buffer 34c, via blue bus 7, blue LED 4c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34a, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. For the same reason, the current cannot flow from the output of buffer 34c, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e. As a result of blending equal portions of red and blue light signals in each segment, segments c, f and g illuminate in a substantially purple color, thereby causing a visual impression of a character ‘4’.

[0169] At the same time, current flows from the output of buffer 33a, via resistor 36a, green LED 3a, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33b, via resistor 36b, green LED 3b, and green bus 6, to the output of buffer 34b. The current also flows from the output of buffer 33d, via resistor 36d, green LED 3d, and green bus 6, to the output of buffer 34b. The current also flows from the output of 33e, via resistor 36e, green LED 3e, and green bus 6, to the output of buffer 34b. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the output of buffer 34b, because that is also at a low logic level. As a consequence, segments a, b, d, and e illuminate in green color.

[0170] The overall effect is a visual impression of a character ‘4’ exhibited in a substantially purple color on a background of green color.

[0171] To illuminate display element 43bin blue-green color, the bus color control inputs GB and BB are raised to a high logic level, while the remaining bus color control input RB is maintained at a low logic level. As a result, the outputs of buffers 34band 34crise to a high logic level, while the output of buffer 34aremains at a low logic level. The current flows from the output of buffer 34b, via green bus 6, green LED 3c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34b, via green bus 6, green LED 3f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34b, via green bus 6, green LED 3g′, and resistor 36g, to the output of buffer 33g. The current flows from the output of buffer 34c, via blue bus 7, blue LED 4c′, and resistor 36c, to the output of buffer 33c. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4f′, and resistor 36f, to the output of buffer 33f. The current also flows from the output of buffer 34c, via blue bus 7, blue LED 4g′, and resistor 36g, to the output of buffer 33g. The current cannot flow from the output of buffer 34b, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e, because their outputs are also at a high logic level. For the same reason, the current cannot flow from the output of buffer 34c, which is at a high logic level, to the outputs of buffers 33a, 33b, 33d, and 33e. As a result of blending equal portions of green and blue light signals in each segment, segments c, f and g illuminate in a substantially blue-green color, thereby causing a visual impression of a character ‘4’.

[0172] At the same time, current flows from the output of buffer 33a, via resistor 36a, red LED 2a, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33b, via resistor 36b, red LED 2b, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33d, via resistor 36d, red LED 2d, and red bus 5, to the output of buffer 34a. The current also flows from the output of buffer 33e, via resistor 36e, red LED 2e, and red bus 5, to the output of buffer 34a. The current cannot flow from the outputs of buffers 33c, 33f, and 33g, which are at a low logic level, to the output of buffer 34a, because that is also at a low logic level. As a consequence, segments a, b, d, and e illuminate in red color.

[0173] The overall effect is a visual impression of a character ‘4’ exhibited in a substantially blue-green color on a background of red color.

[0174] In FIG. 42, red LEDs 2c, 2c′, green LEDs 3c, 3c′, and blue LEDs 4c, 4c′ are placed on the base of a segment body 15cwhich is filled with a transparent light scattering material 16. When forwardly biased, either LEDs 2c, 3c, and 4c, or LEDs 2c′, 3c′, and 4c′ emit light signals of red, green, and blue colors, respectively, which are scattered within transparent material 16, thereby blending the red, green, and blue light signals into a composite light signal that emerges at the upper surface of segment body 15c. The color of the composite light signal may be controlled by varying the portions of the red, green, and blue light signals.

[0175] It would be obvious to persons of ordinary skill that the described variable color complementary display device is not limited to a 7-segment display font, but may have any other suitable shape or arrangement, such as a dot matrix or the like. It would be further obvious, in the view of this disclosure, that other display colors, and their automatically generated complementary colors, may be obtained by applying pulses to bus color control inputs RB, GB, and BB.

[0176] In brief summary, the invention describes a variable color complementary display device which includes a plurality of display areas arranged in a pattern for exhibiting, upon selective activation, a plurality of display units. Each said display area includes a first pair of light emitting diodes for emitting, when forwardly biased, light signals of a first color, a second pair of light emitting diodes for emitting, when forwardly biased, light signals of a second color, a third pair of light emitting diodes for emitting, when forwardly biased, light signals of a third color, and a device for combining the light signals in the display area to obtain a light signal of a composite color. Each pair includes a first light emitting diode and a second light emitting diode connected in an anti-parallel fashion such that their polarities are opposite, thereby defining a first terminal of the pair and a second terminal of the pair. A decoder is provided which includes a decoder input, for receiving an input code defining a selected display unit, and a plurality of decoder outputs. The decoder outputs are coupled to the first terminals in accordance with the positions of the display areas in the pattern. The decoder outputs produce selective decoder output signals, for selecting the first light emitting diodes in certain of the display areas, corresponding by their positions in the pattern to the selected display unit, in response to a specific input code. The decoder also produces opposite output signals on the remaining decoder outputs, for selecting the second light emitting diodes in the remaining display areas. A first bus is provided to which the second terminals of all pairs of the first primary color are commonly coupled such that the first light emitting diodes in each pair of the first primary color in each display area selected by the decoder outputs are forwardly biased when the first bus is energized. Similarly, a second bus is provided to which the second terminals of all pairs of the second primary color are commonly coupled such that the first light emitting diodes in each pair of the second primary color in each display area selected by the decoder outputs are forwardly biased when the second bus is energized. In a similar fashion, a third bus is provided to which the second terminals of all pairs of the third primary color are commonly coupled such that the first light emitting diodes in each pair of the third primary color in each display area selected by the decoder outputs are forwardly biased when the third bus is energized. The display device is activated by selectively energizing the buses, for forwardly biasing certain ones of the first light emitting diodes, in accordance with the output signals of the decoder, for illuminating in a selective display color the display areas corresponding by their positions to one of said display units. As a consequence, certain ones of the second light emitting diodes are forwardly biased, in accordance with the opposite output signals of the decoder, for illuminating the remaining display areas in a color substantially complementary to the display color.

[0177] It would be obvious, in the view of the present disclosure, that the hardware design of the present invention may be also implemented by software. It would be further obvious that persons skilled in the art may resort to modifications in the construction of the preferred embodiment described herein, without departing from the spirit and scope of the invention as defined in the appended claims. It is contemplated that the principles of the invention are also applicable to numerous diverse types of display devices, such as luminescent devices, liquid crystal display devices, plasma display devices, cathode ray tube display devices, and the like.

[0178] The examples of commercially available components should be considered as merely illustrative. It will be appreciated that other components may be readily and effectively used. The integrated circuits used in the description of the invention are manufactured by several known companies, such are Analog Devices, Inc., Fairchild Camera and Instrument Corporation, Intel Corporation, Intersil, Inc., Motorola Semiconductor Products Inc., National Semiconductor Incorporated, Precision Monolithics Incorporated, Teledyne Semiconductor, Texas Instruments Inc., etc.