US 4,488,149 AGrant
Electronic Display Having Segments Wherein Each Segment Is Capable of Selectively Illuminating Two Colors
Issue Date:1984-12-11
•7 Claims
•4 Drawing Sheets
Abstract
An electronic display including a first light emitting diode emitting a first color when biased in the forward direction, a second light emitting diode emitting a second color when biased in the forward direction, and means to selectively bias one of the first and the second light emitting diodes in the forward direction so the electronic display emits one of the first and the second colors.
Metadata
Inventor
- William A. Givens, Jr.
Application Information
Application Number:US 2385538
Filing Date:1981-02-26
Priority Date:1981-02-26
Art Unit:264
Classifications
IPC:
G09G 314
Field of Search:
340715;762;782;701;702;703;704
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates generally to electronic displays and, more particularly, but not by way of limitation, to an electronic display having segments which can be selectively biased to emit one of a first and a second color.
2. Brief Description of the Prior Art
U.S. Pat. No. 3,531,585, issued to Strain, disclosed a display device having an electroluminescent device with a plurality of layers of phosphorus, each being respectively capable of electroluminescence of differing colors.
U.S. Pat. No. 3,909,788, issued to Kaelin, et al., disclosed a driving circuit for light emitting diodes arranged to achieve a selectable color display. This device included a control for controlling the brightness of the biased light emitting diode to emit predetermined colors.
U.S. Pat. No. 3,740,570, issued to Kaelin, et al., disclosed light emitting diodes arranged in a matrix with a brightness control for selectively controlling the emitted color.
U.S. Pat. No. 3,875,473, issued to Lebailly, disclosed a device capable of emitting different colors.
U.S. Pat. No. 3,927,399, issued to Fuzzell, disclosed a circuit with light emitting diodes, lenses being used to obtain different colors.
Brief Description of the Drawings
FIG. 1 is a diagrammatic, schematic view of an electronic display constructed in accordance with the present invention.
FIG. 2 is a diagrammatic, schematic view of a modified driving network which can be utilized in conjunction with the seven segment display shown in FIG. 1 to construct a modified electronic display.
FIG. 3 is a diagrammatic, schematic view of a modified electronic display which is constructed in accordance with the present invention.
FIG. 4 is a diagrammatic, schematic view of a modified driving network which can be utilized in conjunction with the seven segment display shown in FIG. 3 to construct a modified electronic display.
FIG. 5 is a schematic view of a modified seven segment display which is constructed in accordance with the present invention.
Description of the Preferred Embodiments
Referring to the drawings in general and to FIG. 1 in particular, shown therein and designated by the general reference numeral 10 is an electronic display which is constructed in accordance with the present invention. The electronic display 10 includes a seven segment display 12 and a driving network 14.
The seven segment display 12 includes seven segments 16, each of the seven segments 16 being identical in construction and designated respectively in FIG. 1 by the reference numerals 16a, 16b, 16c, 16d, 16e, 16f, and 16g. The seven sgements 16 are arranged to form the seven segment display 12 such that, by activating selected ones of the seven segments 16, the seven segment display 12 will display a predetermined indicia, such as a predetermined numeral or letter of the alphabet. The arrangement and operation of seven segment displays generally are well known in the art and a detailed description of such is not required herein.
Each segment 16 includes a first light emitting diode 18 having a cathode 20 and an anode 22, a second light emitting diode 24 having a cathode 26 and an anode 28. The first light emitting diodes are designated in FIG. 1 by the reference numerals 18a, 18b, 18c, 18d, 18e, 18f, and 18g, and the respective cathodes and anodes are designated in FIG. 1 by the reference numerals 20a, 20b, 20c, 20d, 20e, 20f, and 20g, and 22a, 22b, 22c, 22d, 22e, 22f, and 22g. The second light emitting diodes are designated in FIG. 1 by the reference numerals 24a, 24b, 24c, 24d, 24e, 24f, and 24g, and the respective cathodes and anodes are designated in FIG. 1 by the reference numerals 26a, 26b, 26c, 26d, 26e, 26f, and 26 g, and 28a, 28b, 28c, 28d, 28e, 28f, and 28g.
In each segment 16, the cathode 20 of the first light emitting diode 18 is connected to the anode 28 of the second light emitting diode 24 by a signal path 30, and the anode 22 of the first light emitting diode 18 is connected to the cathode 26 of the second light emitting diode 24 by a signal path 32, the respective signal paths 30 being designated by the reference numerals 30a, 30b, 30c, 30d, 30e, 30f, and 30g in the drawings and the respective signal paths 32 being designated by the reference numerals 32a, 32b, 32c, 32d, 32e, 32f, and 32g in the drawings.
Each of the first light emitting diodes 18 is constructed to emit a first color when biased in the forward direction or, in other words, when a positive potential is applied to the anode 22 and a negative potential is applied to the cathode 20. Each of the second light emitting diodes 24 is constructed to emit a second color when biased in the forward direction or, in other words, when a positive potential is applied to the anode 28 and a negative potential is applied to the cathode 26.
The driving network 14 is connected to each of the segments 16 and the driving network 14 is constructed to selectively bias one of the first and the second light emitting diodes 18 and 24 of predetermined or selected ones of the segments 16 to cause the seven segment display 12 to display a predetermined indicia in the first or the second color. It should be noted that the driving network 14 could be constructed to rapidly and alternately bias the first and the second light emitting diodes 18 and 24 in the forward direction to cause the seven segment display 12 to display a predetermined indicia in the illusion of a third color resulting from the alternating emitting of the first and the second colors.
The driving network includes a four bit binary to seven segment decoder 34 which is constructed to receive an input binary code on the input signal paths 36, 38, 40, and 42 indicative of a predetermined indicia. In response to receiving the input binary code, the seven segment decoder 34 decodes the input binary code and provides output signals on the output signal paths 44, 46, 48, 50, 52, 54, and 56 indicative of the predetermined indicia for causing selected ones of the seven segments 16 to display the predetermined indicia indicated by the input binary code. Decoders which are constructed to receive input binary codes indicative of predetermined indicia and to provide output signals indicative of the predetermined indicia for causing a seven segment display to display the predetermined indicia are well known in the art and a detailed description of the construction and the operation of such decoders is not required herein.
The driving network 14 also includes seven inverting buffers 58a, 58b, 58c, 58d, 58e, 58f, and 58g, and a color control 60. The color control 60 is constructed to provide a color control signal on an output signal path 62 in either the high state (positive potential) or the low state (negative or ground potential) for biasing one of the first and the second light emitting diodes 18 and 24 in the forward direction to cause the segments 16 to emit the first or the second color, the signal path 62 being connected to the input of each of the inverting buffers 58.
Each inverting buffer 58 receives the color control signal on the signal path 62 and provides an inverted output signal on the respective output signal paths 64a, 64b, 64c, 64d, 64e, 64f, and 64g, or, in other words, each inverting buffer 58 provides an output signal in the high state in response to receiving the color control signal in the low state and provides an output signal in the low state in response to receiving the color control signal in the high state. Each of the inverting buffers 58 is connected to the common connection between the cathode 20 of the first light emitting diode 18 and the anode 28 of the second light emitting diode 24 of one of the segments 16, the inverting buffer 58a output signal path 64a being connected to the signal path 30a, the inverting buffer 58b output signal path 64b being connected to the signal path 30b, the inverting buffer 58c output signal path 64c being connected to the signal path 30c, the inverting buffer 58d output signal path 64d being connected to the signal path 30d, the inverting buffer 58e output signal path 64e being connected to the signal path 30e, the inverting buffer 58f output signal path 64f being connected to the signal path 30f, and the inverting buffer 58g output signal path 64g being connected to the signal path 30g.
The driving network 14 also includes seven tri-state non-inverting buffers 66a, 66b, 66c, 66d, 66e, 66f, and 66g. Each non-inverting buffer 66 receives one of the output signals provided by four bit binary to seven segment decoder 34. More particularly, the buffer 66a receives the output signal provided on the signal path 44, the buffer 66b receives the output signal provided on the signal path 46, the buffer 66c receives the output signal provided on the signal path 48, the buffer 66d receives the output signal provided on the signal path 50, the buffer 66e receives the output signal provided on the signal path 52, the buffer 66f receives the output signal provided on the signal path 54, and the buffer 66g receives the output signal provided on the signal path 56. The signals provided on the output signal paths 44, 46, 48, 50, 52, 54, and 56 are connected to control inputs of the buffers 66a, 66b, 66c, 66d, 66e, 66f, and 66g, respectively. Each buffer 66 is constructed to provide a high impedance output in response to receiving a signal in the low state at the control input of the buffer 66 regardless of the logic state of the input signal to the buffer 66, and each buffer 66 provides an output signal in the same logic state as the logic state of the input signal received by the buffer 66 when receiving a signal in the high state at the control input of the buffer 66.
Each buffer 66 receives the color control signal provided on the signal path 62 and each buffer 66 provides an output signal on a signal path 68 which is in the same logic state as the received color control signal, the signal paths 68 being designated respectively 68a, 68b, 68c, 68d, 68e, 68f, and 68g, in the drawings. The signal path 68 of each buffer 66 is connected to the common connector between the anode 22 of the first light emitting diode 18 and the cathode 26 of the second light emitting diode 24 of one of the segments 16, the signal paths 68 being connected to the respective signal paths 32.
The signals on the output signal paths 44, 46, 48, 50, 52, 54, and 56 determine which of the segments 16 will be emitting one of the first and second colors. If the signal on any of the output signal paths 44, 46, 48, 50, 52, 54, and 56 is in the low state, the non-inverting buffer 66 connected to that signal path will be conditioned to provide a high impedance output on the buffers 66 output signal path 68 and, in that condition or state of the buffer 66, neither the first nor the second light emitting diodes 18 or 24 can be forward biased. However, when any of the signals on the signal paths 44, 46, 48, 50, 52, 54, and 56 is in the high state, the non-inverting buffer 66 connected to such signal path operates to provide an output signal on the signal path 68 which is in the same state (high or low) as the color control signal received on the signal path 62. Thus, when the signal on one of the signal paths 44, 46, 48, 50, 52, 54, and 56 is in the high state, the color control signal functions to determine whether the first or the second light emitting diode 18 or 24 will emit color.
The color control signal is connected to the cathode 20 of the first light emitting diode 18 and to the anode 28 of the second light emitting diode 24 of each segment 16 via one of the inverting buffers 58, and thus the signal applied to the cathode 20 and the anode 28 of the first and the second light emitting diodes will be in a state (high or low) which is the opposite of the state of the applied color control signal since the inverting buffer 58 functions to invert the received color control signal. The color control signal is connected to the anode 22 of the first light emitting diode 18 and to the cathode 26 of the second light emitting diode 24 via one of the non-inverting buffers 66, and thus the signal applied to the anode 22 and the cathode 26 of the first and second light emitting diodes 18 and 24 will be in the same state (high or low) as the color control signal. Thus, the inverting buffers 58 cooperate to assure that the first and the second light emitting diodes 18 and 24 will be biased in opposite directions and the direction of such biasing is controlled by the color control signal. The foregoing description presumes that the signal connected to the control input of the non-inverting buffer 66 is in the high state.
By way of example, assume that the four bit binary input code is indicative of an indicia which requires the illumination of the segment 16a, then this input code will be decoded by the decoder 34 and the decoder 34 will provide an output signal on the signal path 44 in the high state, such signal being received by the non-inverting buffer 66a. Further, assume that it is predetermined that the segment 16a is to emit the first color, then the color control will provide an output color control signal on the signal path 62 in the high state. The color control signal in the high state will be received by the inverting buffer 58a which will provide an output signal on the signal path 64a in the low state and the color control signal in the high state will be received by the non-inverting buffer 66a which will provide an output signal on the path 68a in the high state. In this condition, the first light emitting diode 18a of the segment 16a will be biased in the forward direction (a signal in the high state or a positive potential being applied to the anode 22a and a signal in the low state or respective potential being applied to the cathode 20a) and the second light emitting diode 24a will be biased in the reverse direction with a signal in the low state or negative potential being applied to the anode 28a and a signal in the high state or positive potential being applied to the cathode 26a. When the first light emitting diode 18a of the segment 16a is biased in the forward direction, the first light emitting diode 18a will emit the first color.
Further, by way of example, assume that the seven segment display 12 is to be conditioned to display the numeral "4" in the first color. Then, the segments 16b, 16c, 16f, and 16g will be conditioned so that the first light emitting diodes 18b, 18c, 18f, and 18g of the segments 16b, 16c, 16f, and 16g, respectively, will be forward biased and thus emit the first color. The four bit input binary code will be "0100" which is the binary equivalent of the numeral "4", and thus a signal in the low state will be applied to the signal path 36, a signal in the high state will be applied to the signal path 38, a signal in the low state will be applied to the signal path 40 and a signal in the low state will be applied to the signal path 42. In response to receiving this particular input signal, the decoder 34 will provide the appropriate output signals to cause the segments 16b, 16c, 16f, and 16g to emit a color or, more particularly, the decoder 34 will provide an output signal on the signal path 44 in the low state, an output signal on the signal path 46 in the high state, an output signal on the signal path 48 in the high state, an output signal on the signal path 50 in the low state, an output signal on the signal path 52 in the low state, an output signal on the signal path 54 in the high state, and an output signal on the signal path 56 in the high state. In this condition, the non-inverting buffers 66a, 66d, and 66e, each will receive a signal in the low state at the respective control inputs, and each buffer 66a, 66d, and 66e will provide an output signal on the respective signal paths 68a, 66d, and 66e having a high impedance. In this state of the buffers 66a, 66d, and 66e, the first and the second light emitting diodes 18 and 24 of the segments 16a, 16d, and 16e cannot be forward biased regardless of the state of the color control signal on the signal path 62a, 62d, and 62e. The non-inverting buffers 66b, 66c, 66 f, and 66g each will receive a high signal at the respective control inputs, and each buffer 66b, 66c, 66f, and 66g will provide an output signal on the respective signal paths 68b, 68c, 68f, and 68g having the same state as the input color control signal received on the signal path 62. The inverting buffers 58 each will receive the color control signal in the high state and each of the inverting buffers 58 will provide an output signal on the respective signal paths 64 in the low state. Thus, a signal in the high state (positive potential) will be applied to the anodes 22b, 22c, 22f, and 22g of the first light emitting diodes 18b, 18c, 18f, and 18g of the segments 16b, 16c, 16f, and 16g, and a signal in the low state (negative potential) will be applied to the cathodes 20b, 20c, 20f, and 20g of the first light emitting diodes 18b, 18c, 18f, and 18g of the segments 16b, 16c, 16f, and 16g, thereby biasing the first light emitting diodes 18b, 18c, 18f, and 18g of the segments 16b, 16c, 16f, and 16g in the forward direction and causing the first light emitting diodes 18 of the segments 16b, 16c, 16f, and 16g to emit the first color, the seven segment display 12 displaying the numeral "4" via the first color of light emitting by the first light emitting diodes 18b, 18c, 18f, and 18g of the segments 16b, 16c, 16f, and 16g.
If the color control signal is in the low state, then a signal in the high state will be applied to the anode 28 of the second light emitting diode 24 and a signal in the low state will be applied to the cathode 26 of the second light emitting diode 24 of those selected segments 16 where the associated non-inverting buffer 66 is receiving a signal in the high state at the control input. In this condition, the second light emitting diode 24 will be forward biased and the second light emitting diode 24 will emit the second color.
It should be noted that an additional segment could be added to the left seven segment display 12 for displaying a decimal indicia display and another segment could be added to the right of the seven segment display 12 for displaying another decimal indicia. If both additional decimal indicia segments are added, two additional inverting buffers and two additional tri-state non-inverting buffers would be added to the driving network 14. In view of the foregoing detailed description, the construction and operation of the electronic display including the two additional decimal indicating indicia will be apparent.
Also, it should be noted that in practice an electronic display would include more than one seven segment display or a display with more than seven segments, the precise number depending upon the particular application.
Embodiment of Fig. 2
Shown in FIG. 2 is a modified driving network 14h which can be utilized in conjunction with the seven segment display 12 shown in FIG. 1.
The driving network 14h is constructed exactly like the driving network 14 shown in FIG. 1, except the driving network 14h includes only one inverting buffer 70 in lieu of the seven inverting buffers 58a, 58b, 58c, 58d, 58e, 58f, and 58g. The single inverting buffer 70 receives the color control signal on the signal path 62 and provides an output signal having an inverted state with respect to the state of the received color control signal. The output signal provided by the buffer 70 is connected to and applied on the signal paths 64a, 64b, 64c, 64d, 64e, 64f, and 64g.
The driving network 14h will operate exactly like the driving network 14 shown in FIG. 1 and described in detail before, except the signal on the signal paths 64a, 64b, 64c, 64d, 64e, 64f, and 64g is provided by the single inverting buffer 70. With respect to the driving network 14h, the inverting buffer 70 must be capable of handling a current approximately equal to the sum of the currents handled by the buffers 58a, 58b, 58c, 58d, 58e, 58f, and 58g in the driving network 14.
Embodiment of Fig. 3
Shown in FIG. 3 is a modified electronic display 80 having a modified seven segment display 82; and a modified driving network 84, which is constructed similar to the embodiment of the present invention shown in FIG. 1.
The seven segment display 82 includes seven segments 86, each of the seven segments 86 being identical in construction and designated respectively in FIG. 3 by the reference numerals 86a, 86b, 86c, 86d, 86e, 86f, and 86g. The seven segments 86 are arranged to form the seven segment display 82 in a manner and for reasons like those described before with respect to the seven segment display 12 shown in FIG. 1.
Each segment 86 includes a first light emitting diode 88 having a cathode 90 and an anode 92, and a second light emitting diode 94 having a cathode 96 and an anode 98. The first light emitting diodes are designated in FIG. 3 by the reference numerals 88a, 88b, 88c, 88d, 88e, 88f, and 88g, and the respective cathodes and anodes are designated in FIG. 3 by the reference numerals 90a, 90b, 90c, 90d, 90e, 90f, and 90g, and 92a, 92b, 92c, 92d, 92e, 92f, and 92g. The second light emitting diodes are designated in FIG. 3 by the reference numerals 94a, 94b, 94c, 94d, 94e, 94f, and 94g, and the respective cathodes and anodes are designated in FIG. 3 by the reference numerals 96a, 96b, 96c, 96d, 96e, 96f, and 96g, and 98a, 98b, 98c, 98d, 98e, 98f, and 98g.
In each segment 86, the cathode 90 of the first light emitting diode 88 is connected to the cathode 96 of the second light emitting diode 94 by a signal path 100, each connection between the cathodes 90 and 96 is connected to a cathode potential 101 by a conductor 102, the respective signal paths 100 being designated by the reference numerals 100a, 100b, 100c, 100d, 100e, 100f, and 100g in the drawings. The cathode potential 101 is constructed to apply a negative potential to the cathodes 90 and 96 of each of the first and the second light emitting diodes 88 and 94, the negative potential being either a logic low signal or ground.
Each of the first light emitting diodes 88 is constructed to emit a first color when biased in the forward direction, and each of the second light emitting diodes 94 is constructed to emit a second color when biased in the forward direction, for reasons described before with respect to the diodes 18 and 24.
The driving network 84 is connected to each of the segments 86 and the driving network 84 is constructed to selectively bias one of the first and the second light emitting diodes 88 and 94 of predetermined or selected ones of the segments 86 to cause the seven segment display 82 to display a predetermined indicia in the first or the second color.
The driving network 84 includes a four bit binary to seven segment decoder 104 which is constructed to receive an input binary code on the input signal paths 106, 108, 110, and 112 indicative of a predetermined indicia. In response to receiving the input binary code, the seven segment decoder 104 decodes the input binary code and provides output signals on the output signal paths 114, 116, 118, 120, 122, 124, and 126 indicative of the predetermined indicia for causing selected ones of the seven segments 86 to display the predetermined indicia indicated by the input binary code.
The driving network 84 also includes fourteen AND gates 128a, 128b, 128c, 128d, 128e, 128f, 128g, 128h, 128i, 128j, 128k, 128l, 128m, and 128n, and a color control 130. The color control 130 is constructed to provide a first color control signal on an output signal path 132 in either the high state (positive potential) or the low state (negative potential) and to provide a second color control signal on an output signal path 134 in either the high state or the low state for biasing one of the first and the second light emitting diodes 88 and 94 in the forward direction to cause the segments 86 to emit the first or the second color.
Each AND gate 128a, 128c, 128e, 128g, 128i, 128k, and 128m receives the first color control signal on the signal path 132 and each AND gate 128b, 128d, 128f, 128h, 128j, 128l, and 128n receives the second color control signal on the signal path 134.
Each AND gate 128 is constructed to provide an output signal in the high state in response to receiving two input signals each in the high state. Each AND gate 128 provides an output signal in the low state in response to receiving two input signals either one or both being in the low state.
The AND gates 128a and 128b each are connected to and receive the signal provided by the decoder 104 on the signal path 114, the AND gate 128a providing an output signal on a signal path 136 which is connected to the anode 92a of the first light emitting diode 88a of the segment 86a and the AND gate 128b providing an output signal on a signal path 138 which is connected to the anode 98a of the second light emitting diode 94a of the segment 86a.
The AND gates 128c and 128d each are connected to and receive the signal provided by the decoder 104 on the signal path 116, the AND gate 128c providing an output signal on a signal path 140 which is connected to the anode 92b of the first light emitting diode 88b of the segment 86b and the AND gate 128d providing an output signal on a signal path 142 which is connected to the anode 98b of the second light emitting diode 94b of the segment 86b.
The AND gates 128e and 128f each are connected to and receive the signal provided by the decoder 104 on the signal path 118, the AND gate 128e providing an output signal on a signal path 144 which is connected to the anode 92c of the first light emitting diode 88c of the segment 86c and the AND gate 128f providing an output signal on a signal path 146 which is connected to the anode 98c of the second light emitting diode 94c of the segment 86c.
The AND gates 128g and 128h each are connected to and receive the signal provided by the decoder 104 on the signal path 120, the AND gate 128g providing an output signal on a signal path 148 which is connected to the anode 92d of the first light emitting diode 88 of the segment 86d and the AND gate 128h providing an output signal on a signal path 150 which is connected to the anode 98d of the second light emitting diode 94d of the segment 86d.
The AND gates 128i and 128j each are connected to and receive the signal provided by the decoder 104 on the signal path 122, the AND gate 128i providing an output signal on a signal path 152 which is connected to the anode 92e of the first light emitting diode 88e of the segment 86e and the AND gate 128j providing an output signal on a signal path 154 which is connected to the anode 98e of the second light emitting diode 94e of the segment 86e.
The AND gates 128k and 128l each are connected to and receive the signal provided by the decoder 104 on the signal path 124, the AND gate 128k providing an output signal on a signal path 156 which is connected to the anode 92f of the first light emitting diode 88f of the segment 86f and the AND gate 128f providing an output signal on a signal path 158 which is connected to the anode 98f of the second light emitting diode 94f of the segment 86f.
The AND gates 128m and 128n each are connected to and receive the signal provided by the decoder 104 on the signal path 126, the AND gate 128m providing an output signal on a signal path 160 which is connected to the anode 92g of the first light emitting diode 88g of the segment 86g and the AND gate 128n providing an output signal on a signal path 162 which is connected to the anode 98g of the second light emitting diode 94g of the segment 86g.
When the AND gate 128a receives a signal on the signal path 114 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128a provides an output signal on the signal path 136 in the high state thereby causing the first light emitting diode 88a to be forward biased and emit the first color. When the AND gate 128b receives a signal on the signal path 114 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128b provides an output signal on the signal path 138 in the high state thereby causing the second light emitting diode 94a to be forward biased and emit the second color.
When the AND gate 128c receives a signal on the signal path 116 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128c provides an output signal on the signal path 140 in the high state thereby causing the first light emitting diode 88b to be forward biased and emit the first color. When the AND gate 128d receives a signal on the signal path 116 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128d provides an output signal on the signal path 142 in the high state thereby causing the second light emitting diode 94b to be forward biased and emit the second color.
When the AND gate 128e receives a signal on the signal path 118 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128e provides an output signal on the signal path 144 in the high state thereby causing the first light emitting diode 88c to be forward biased and emit the first color. When the AND gate 128f receives a signal on the signal path 118 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128f provides an output signal on the signal path 146 in the high state thereby causing the second light emitting diode 94c to be forward biased and emit the second color.
When the AND gate 128g receives a signal on the signal path 120 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128g provides an output signal on the signal path 148 in the high state thereby causing the first light emitting diode 88d to be foreard biased and emit the first color. When the AND gate 128h receives a signal on the signal path 120 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128h provides an output signal on the signal path 150 in the high state thereby causing the second light emitting diode 94d to be forward biased and emit the second color.
When the AND gate 128i receives a signal on the signal path 122 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128i provides an output signal on the signal path 152 in the high state thereby causing the first light emitting diode 88e to be forward biased and emit the first color. When the AND gate 128j receives a signal on the signal path 122 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128j provides an output signal on the signal path 154 in the high state thereby causing the second light emitting diode 94e to be forward biased and emit the second color.
When the AND gate 128k receives a signal on the signal path 124 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128k provides an output signal on the signal path 156 in the high state thereby causing the first light emitting diode 88f to be forward biased and emit the first color. When the AND gate 128l receives a signal on the signal path 124 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128l provides an output signal on the signal path 158 in the high state thereby causing the second light emitting diode 94f to be forward biased and emit the second color.
When the AND gate 128m receives a signal on the signal path 126 in the high state and a first color control signal in the high state on the signal path 132, the AND gate 128m provides an output signal on the signal path 160 in the high state thereby causing the first light emitting diode 88g to be foreard biased and emit the first color. When the AND gate 128n receives a signal on the signal path 126 in the high state and the second color control signal in the high state on the signal path 134, the AND gate 128n provides an output signal on the signal path 162 in the high state thereby causing the second light emitting diode 94g to be forward biased and emit the second color.
The color control 130 is constructed to provide only one of the first and the second color control signals in the high state and the opposite color control signal in the low state at any one time. When the first color control signal is in the high state and the second color control signal is in the low state, only the first light emitting diodes 88 can be forward biased to emit the first color. When the second color control is in the high state and the first color control signal is in the low state, only the second light emitting diodes 94 can be forward biased to emit the second color. It should be noted that, in the alternative, the driving network 84 could be constructed to bias both the first and the second light emitting diodes 88 and 94 in the forward direction to cause the seven segment display 82 to display a predetermined indicia in a third color resulting from the simultaneous emitting of the first and the second colors.
By way of example, assume that the seven segment display 82 is to be conditioned to display the numeral "4" in the first color. Then, the segments 86b, 86c, 86f, and 86g will be conditioned so that the first light emitting diodes 88b, 88c, 88f, and 88g of the segments 86b, 86c, 86f, and 86g, respectively, will be forward biased and thus emit the first color. The four bit input binary code will be "0100" which is the binary equivalent of the numeral "4", and thus a signal in the low state will be applied to the signal path 106, a signal in the high state will be applied to the signal path 108, a signal in the low state will be applied to the signal path 110 and a signal in the low state will be applied to the signal path 112. In response to receiving this particular input signal, the decoder 104 will provide the appropriate output signals to cause the segments 86b, 86c, 86f, and 86g to emit a color or, more particularly, the decoder 104 will provide an output signal on the signal path 114 in the low state, an output signal on the signal path 116 in the high state, an output signal on the signal path 118 in the high state, an output signal on the signal path 120 in the low state, an output signal on the signal path 122 in the low state, an output signal on the signal path 124 in the high state, and an output signal on the signal path 126 in the high state. In this condition, the AND gates 128a, 128b, 128g, 128h, 128i, and 128j, each will receive a signal in the low state, and each AND gate 128a, 128b, 128g, 128h, 128i, and 128j will provide an output signal on the respective signal paths 136, 138, 148, 150, 152, and 154 in the low state. In this condition, the first and the second light emitting diodes 88 and 94 of the segments 86a, 86d, and 86e will not be forward biased regardless of the state of the first and second color control signals on the signal paths 132 and 134. The AND gates 128c, 128d, 128e, 128f, 128k, 128l, 128m, and 128n each will receive a high signal on the respective signal paths 116, 118, 124, and 126. The AND gates 128c, 128e, 128k, and 128m also will receive the first color control signal on the signal path 132 in the high state, and thus the AND gates 128c, 128e, 128k, and 128m will each provide an output signal in the high state on the respective signal paths 140, 144, 156, and 160 in the high state thereby forward biasing the first light emitting diodes 88b, 88c, 88f, and 88g to cause the numeral "4" to be displayed in the first color.
Two additional segments could be included with the seven segment display 12 to display decimals in a manner and for reasons described before with respect to the electronic display 10.
Embodiment of Fig. 4
Shown in FIG. 4 is a modified seven segment display 200 which is constructed and operates similar to the seven segment display 82 shown in FIG. 3.
The seven segment display 200 includes seven segments 204, each of the seven segments 204 being identical in construction and designated respectively in FIG. 4 by the reference numerals 204a, 204b, 204c, 204d, 204e, 204f, and 204g. The seven segments 204 are arranged to form the seven segment display 200 in a manner and for reasons like those described before with respect to the seven segment displays 12 and 82.
Each segment 204 includes a first light emitting diode 206 having a cathode 208 and an anode 210, and a second light emitting diode 212 having a cathode 214 and an anode 216. The first light emitting diodes are designated in FIG. 4 by the reference numerals 206a, 206b, 206c, 206d, 206e, 206f, and 206g, and the respective cathodes and anodes are designated in FIG. 4 by the reference numerals 208a, 208b, 208c, 208d, 208e, 208f, and 208g, and 210a, 210b, 210c, 210d, 210e, 210f, and 210g. The second light emitting diodes are designated in FIG. 4 by the reference numerals 212a, 212b, 212c, 212d, 212e, 212f, and 212g, and the respective cathodes and anodes are designated in FIG. 4 by the reference numerals 214a, 214b, 214c, 214d, 214e, 214f, and 214g, and 216a, 216b, 216c, 216d, 216e, 216f, and 216g.
In each segment 204, the anode 210 of the first light emitting diode 206 is connected to the anode 216 of the second light emitting diode 212 by a signal path 218, and each connection between the anodes 210 and 216 is connected to an anode potential 220 by a conductor 222, the respective signal paths 218 being designated by the reference numerals 218a, 218b, 218c, 218d, 218e, 218f, and 218g in the drawings. The anode potential 220 is constructed to apply a positive potential to the anodes 210 and 216 of each of the first and the second light emitting diodes 206 and 212, the positive potential being a logic high signal.
Each of the first light emitting diodes 206 is constructed to emit a first color when biased in the forward direction, and each of the second light emitting diodes 212 is constructed to emit a second color when biased in the forward direction, for reasons described before with respect to the diodes 18 and 24, shown in FIG. 1.
The cathodes 208 and 214 are each connected to a driving network (not shown in FIG. 4) by signal paths 224, 226, 228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248, and 250.
The driving network can be constructed exactly like the driving network 84 shown in FIG. 3 except the driving network for the seven segment display 200 must apply a negative potential or a signal having a low state to selected ones of the signal paths 224, 226, 228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248, and 250 to cause the first or the second light emitting diodes 206 or 212 to be forward biased to emit the first or the second color. This can be accomplished by modifying the decoder 104 or by interposing an inverter in each of the signal paths 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, and 162 (shown in FIG. 4) and otherwise using the identical driving network 84 shown in FIG. 4.
Embodiment of Fig. 5
Shown in FIG. 5 is a modified driving network 84x which is constructed exactly like the driving network 84 shown in FIG. 3, except the driving network 84x includes a modified color control 130x and an inverter 300. The color control 130x provides a color control signal on a signal path 302 which is connected to the signal path 134x, the signal on the signal path 134x being the second color control signal and this signal being identical to the color control signal provided by the color control 130x. The inverter 300 is interposed in the signal path 302 and the inverter 300 is constructed to provide an inverted output signal (a signal in the high state in response to receiving a signal in the low state on the signal path 302 and a signal in the low state in response to receiving a signal in the high state on the signal path 302). The output signal provided by the inverter 300 is connected to the signal path 132x and thus the inverter 300 output signal is in the first color control signal.
The driving network 84x will operate exactly like the driving network 84 (shown in FIG. 3). The inverter 300 assures that the first color control signal will have a state (high or low) which is opposite the state (high or low) of the second color control signal, thereby assuring that only one color will be emitted at any one time.
Changes may be made in the construction and operation of the various embodiments disclosed herein without departing from the spirit and scope of the invention as defined in the following claims.
Claims
What is claimed is:
1. An electronic display, comprising: a segment, comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; a second lignt emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the cathode of the first light emitting diode being connected to the anode of the second light emitting diode and the anode of the first light emitting diode being connected to the cathode of the second light emitting diode; means connected to the segment for selectively biasing one of the first and the second light emitting diodes in the forward direction, said means being connected to the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode and being connected to the common connection between the cathode of the first light emitting diode and the anode of the second light emitting diode, and said means selectively applying a bias to the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode and applying a negative bias to the common connection between the cathode of the first light emitting diode and the anode of the seocnd light emitting diode to bias the first light emitting diode in the forward direction, and said means selectively applying a positive bias to the common connection between the cathode of the first light emitting diode and the anode of the second light emitting diode and applying a negative bias to the common connection between the anode of the first light emitting diode and the cathode of the seocnd light emitting diode to bias the second light emitting diode in the forward direction; a color control providing a color signal, the color control signal being connected to and applied at the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode; and an inverting buffer receiving the color control signal and providing an inverted output signal, the inverted output signal being connected to and applied at the common connection between the cathode of the first light emitting diode and the anode of the second light emitting diode, the first light emitting diode being forward biased in the high state of the color control signal and the second light emitting diode being forward biased in the low state of the color control signal; and wherein the means for selectively biasing one of the first and the second light emitting diodes is defined further to include: a tri-state non-inverting buffer receiving the color control signal and providing an output signal connected to and received at the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode, the tri-state non-inverting buffer having a control input and providing a high impedance output signal in response to receiving a signal at the color control input in the low state and providing an output signal having the same state as the received signal in response to receiving a signal at the control input in the high state; and wherein the means for selectively biasing the first and the second light emitting diodes is defined further as applying the signal to the control input of the tri-state non-inverting buffer.
2. An electronic display, comprising: a plurality of segments arranged for displaying predetermined indicia, each segment comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the cathode of the first light emitting diode being connected to the anode of the second light emitting diode and the anode of the first light emitting diode being connected to the cathode of the second light emitting diode; and means connected to the segment for selectively biasing one of the first and the second light emitting diodes in the forward direction, said means selectively forward biasing a selected one of the first and the second light emitting diodes of selected ones of the segments for displaying predetermined indicia, said means comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the decoder providing output signals in a predetermined state in response to receiving the four bit binary code; a color control providing a color control signal; a plurality of inverting buffers, each inverting buffer receiving the color control signal and providing an inverted output signal, the inverted output signal of each inverting buffer being connected to the common connection between the cathode of the first light emitting diode and the anode of the second light emitting diode of one of the segments; and a plurality of tri-state non-inverting buffers, each non-inverting buffer receiving one of the output signals provided by the decoder at a control input and each non-inverting buffer providing an output signal having a high impedance in response to receiving a signal at the control input in the low state and each non-inverting buffer providing an output signal having the same state as a received input signal in response to receiving a signal in the high state at the control input, each non-inverting buffer receiving the color control signal and providing an output signal having the same state as the received color control signal when receiving a signal in the high state at the control input, the output signal of each non-inverting buffer being connected to and received at the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode of one of the segments.
3. An electronic display, comprising: a plurality of segment arranged for displaying predetermined indicia, each segment comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the cathode of the first light emitting diode being connected to the cathode of the second light emitting diode; means connected to each segment for selectively forward biasing selected ones of the first and the second light emitting diodes of selected ones of the segments by applying a logic potential to the common connection between the cathodes of the first and the second light emitting diodes, said means comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the decoder providing output signals in a predetermined state in response to receiving the four bit input binary code; a color control providing a first color control signal and a second color control signal; a plurality of AND gates, each AND gate receiving the first color control signal and one of the output signals provided by the decoder and providing an output signal in the high state in response to receiving the first color control signal in the high state and receiving the decoder output signal in the high state, the output signal provided by each AND gate being connected to the anode of the first light emitting diode of one of the segments; and a plurality of AND gates, each AND gate receiving the second color control signal and one of the output signals provided by the decoder and providing an output signal in the high state in response to receiving the second color control signal in the high state and receiving the decoder output signal in the high state, the output signal provided by each AND gate being connected to the anode of the second light emitting diode of one of the segments.
4. An electronic display, comprising: a plurality of segments arranged for displaying predetermined indicia, each segment comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the cathode of the first light emitting diode being connected to the cathode of the second light emitting diode; means connected to each of the segments for selectively biasing one of the first and the second light emitting diodes in the forward direction, the segments being arranged for displaying predetermined indicia by forward biasing a selected one of the first and the second light emitting diodes of selected ones of the segments, said means comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the decoder providing output signals in a predetermined state in response to receiving the four bit input binary code; a color control providing a second color control signal; an inverter receiving the second color control signal and providing an inverted output signal, the inverted output signal being a first color control signal; a plurality of AND gates, each AND gate receiving the first color control signal and one of the output signals provided by the decoder and providing an output signal in the high state in response to receiving the first color control signal in the high state and receiving the decoder output signal in the high state, the output signal provided by each AND gate being connected to the anode of the first light emitting diode of one of the segments; and a plurality of AND gates, each AND gate receiving the first color control signal and one of the output signals provided by the decoder and providing an output signal in the high state in response to receiving the second color control signal in the high state and receiving the decoder output signal in the high state, the output signal provided by each AND gate being connected to the anode of the second light emitting diode of one of the segments.
5. An electronic display, comprising: a plurality of segments arranged for displaying predetermined indicia, each segment comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the anode of the first light emitting diode being connected to the anode of the second light emitting diode and the segments being arranged for displaying predetermined indicia by forward biasing a selected one of the first and the second light emitting diodes of selected ones of the segments; means connected to each of the elements for selectively biasing one of the first and the second light emitting diodes in the forward direction, comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the decoder providing output signals in a predetermined state in response to receiving the four bit input binary code; a color control providing a first color control signal and a second color control signal; a plurality of AND gates, each AND gate receiving the first color control signal and one of the output signals provided by the decoder and providing an output signal in the low state in response to receiving one of the first color control signals and the decoder output signal in the low state, the output signal provided by each AND gate being connected to the cathode of the first light emitting diode of one of the segments; and a plurality of AND gates, and AND gate receiving the second color control signal and one of the output signals provided by the decoder and providing an output signal in the low state in response to receiving one of the second color control signals and the decoder output signal in the low state, the output signal provided by each AND gate being connected to the cathode of the second light emitting diode of one of the segments.
6. An electronic display, comprising: a plurality of segments arranged for displaying predetermined indicia, each segment comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the anode of the first light emitting diode being connected to the anode of the second light emitting diode; and means connected to each of the segments for selectively biasing one of the first and the second light emitting diodes of selected ones of the segments by applying a logic high potential to the common connection between the anodes of the first and the second diodes, the segments being arranged for displaying a predetermined indicia by forward biasing selected ones of the first and the second light emitting diodes of selected ones of the segments, said means comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the providing output signals in a predetermined state in response to receiving the four bit input binary code; a color control providing a second color control signal; an inverter receiving the second color control signal and providing an inverted output signal, the inverted output signal being a first color control signal; a plurality of AND gates, each AND gate receiving the first color control signal and one of the output signals provided by the decoder and providing an output signal in the low state in response to receiving one of the first color control signals and the decoder output signal in the low state, the output signal provided by each AND gate being connected to the cathode of the first light emitting diode of one of the segments; and a plurality of AND gates, each AND gate receiving the second color control signal and one of the output signals provided by the decoder and providing an output signal in the low state in response to receiving one of the second color control signals and the decoder output signal in the low state, the output signal provided by each AND gate being connected to the cathode of the second light emitting diode of one of the segments.
7. An electronic display, comprising: a plurality of segments arranged for displaying predetermined indicia, comprising: a first light emitting diode having a cathode and an anode and emitting a first color when biased in the forward direction; and a second light emitting diode having a cathode and an anode and emitting a second color when biased in the forward direction, the segments being arranged for displaying predetermined indicia by forward biasing a selected one of the first and the second light emitting diodes of selected ones of the segments, the cathode of the first light emitting diode being connected to the anode of the second light emitting diode and the anode of the first light emitting diode being connected to the cathode of the second light emitting diode; means connected to each of the segments for selectively biasing the first and the second light emitting diodes in the forward direction, comprising: a four bit binary to seven segment decoder for receiving a four bit input binary code indicating a predetermined indicia, the decoder providing output signals in a predetermined state in response to receiving the four bit input binary code; a color control providing a color control signal; an inverting buffer receiving the color control signal and providing an inverted output signal, the inverted output signal being connected to the common connection between the cathode of the first light emitting diode and the anode of the second light emitting diode of each of the segments; and a plurality of tri-state non-inverting buffers, each non-inverting buffer receiving one of the output signals provided by the decoder at a control input and each non-inverting buffer providing an output signal having a high impedance in response to receiving a signal at the control input in the low state and each non-inverting buffer providing an output signal having the same state as a received input signal in response to receiving a signal in the high state at the control input, each non-inverting buffer receiving the color control signal and providing an output signal having the same state as the received color control signal when receiving a signal in the high state at the control input, the output signal of each non-inverting buffer being connected to and received at the common connection between the anode of the first light emitting diode and the cathode of the second light emitting diode of one of the segments.