Variable Color Digital Timepiece

This relates to my application Ser. No. 664,426, filed on Mar. 8, 1976, entitled Electronic Timepiece with Transducer, abandoned.

1. Field of the Invention

This invention relates to timepieces utilizing variable color digital display.

2. Description of the Prior Art

A display device that can change color and selectively display digits and characters is described in my U.S. Pat. No. 4,086,514, entitled Variable Color Display Device and issued on Apr. 25, 1978. This display device includes display areas arranged in a suitable display font, such as well known 7-segment display font, which may be selectively energized in groups to display all known characters. Each display segment includes three light emitting diodes for emitting light signals of respectively different primary colors, which are blended within the display segment to form a composite light signal. The color of the composite light signal can be controlled by selectively varying the portions of the primary light signals.

Timepieces with monochromatic digital display are well known and extensively used. Such timepieces, however, have a defect in that they are capable of indicating only values of time. They are not capable of simultaneously indicating values of time and values of another quantities.

Although the possibility of a variable color digital display has been previously considered, no practical system utilizing such a display has been made available to public use.

In a broad sense, it is the principal object of this invention to provide a timepiece with a variable color digital display.

The present invention provides a new dimension in the digital display art. Completely new, unexpected and heretofore impossible, features may be obtained when a well known monochromatic digital display is substituted with a variable color digital display. In the preferred embodiment, the invention was advantageously incorporated into a timepiece. However, the invention is not limited to timepieces and may be utilized in a wide variety of devices, without imposing any limitations.

It is another object of the invention to provide step variable 2-primary and 3-primary color control circuit which is capable of illuminating the display in a selected one of several possible colors.

It is further object of the invention to provide continuously variable 2-primary and 3-primary color converter, for converting an input voltage to variable color, which is capable of illuminating the display in any color of the spectrum, in accordance with the magnitude of the input voltage.

In summary, the electronic timepiece of the present invention is provided with a variable color digital display, in lieu of a commercially well known monochromatic digital display, to indicate time in digital format. The timepiece also includes a transducer for measuring certain physical quantities and for developing output electrical signals related to the measured physical quantities. The color of the time display is controlled in accordance with the output electrical signals of the transducer. In the most preferred embodiment, a timepiece with a variable color digital display is disclosed which can indicate time in digital format and in a color variable in accordance with the heart rate of its user.

The nature and functions of electronic timekeeping devices are well known to those having ordinary skill in the art and do not constitute a limitation on the present invention.

In the drawings in which are shown several possible embodiments of the invention,

FIG. 1 is a block diagram of a typical prior art monochromatic digital display system.

FIG. 2 is a generalized block diagram of variable color digital display system for the practice of the present invention.

FIG. 3 is a block diagram of a step variable color display system.

FIG. 4 is a block diagram of a continuously variable color display system.

FIG. 5 is a block diagram of 2-primary color digital display.

FIG. 6 is a block diagram of 3-primary color digital display.

FIG. 7 is an enlarged detail of one digit of 2-primary color digital display.

FIG. 8 is an enlarged cross-sectional view of one display segment in FIG. 7, taken along the line A--A.

FIG. 9 is an enlarged detail of one digit of 3-primary color digital display.

FIG. 10 is an enlarged cross-sectional view of one display segment in FIG. 9, taken along the line A--A.

FIG. 11 is a schematic diagram of one digit of 2-primary color control circuit of this invention.

FIG. 12 is a schematic diagram of one digit of 3-primary color control circuit of this invention.

FIG. 13 is a block diagram of a color control logic circuit for controlling 2-primary color display.

FIG. 14 is a block diagram of a color control logic circuit for controlling 3-primary color display.

FIG. 15 is a schematic diagram of a color control logic circuit for controlling 2-primary color display.

FIG. 16 is a schematic diagram of a color control logic circuit for controlling 3-primary color display.

FIG. 17 is a simplified schematic diagram, similar to FIG. 11, showing how the number `7` can be displayed in three different colors.

FIG. 18 is a simplified schematic diagram, similar to FIG. 12, showing how the number `1` can be displayed in seven different colors.

FIG. 19 is a block diagram of a multi-element 2-primary color 4-digit display.

FIG. 20 is a block diagram of a multi-element 3-primary color 4-digit display.

FIG. 21 is a block diagram of a signal converter for 2-primary color display.

FIG. 22 is a block diagram of a signal converter for 3-primary color display.

FIG. 23 is a schematic diagram of a comparator circuit for 2-primary color display.

FIG. 24 is a graph showing the relationship between the inputs and outputs of the comparator circuit in FIG. 23.

FIG. 25 is a schematic diagram of a comparator circuit for 3-primary color display.

FIG. 26 is a graph showing the relationship between the inputs and outputs of the comparator circuit in FIG. 25.

FIG. 27 is a block diagram of a continuously variable color display system utilizing two primary colors.

FIG. 28 is a block diagram of a continuously variable color display system utilizing three primary colors.

FIG. 29 is an expanded block diagram of FIG. 27.

FIG. 30 is an expanded block diagram of FIG. 28.

FIG. 31 is a schematic diagram of a scaling circuit.

FIG. 32 is a schematic diagram of an A/D converter and memory combination of FIGS. 29 and 30.

FIG. 33 is a schematic diagram of a memory and color converter combination of FIG. 29.

FIG. 34 is a timing diagram of the circuit shown in FIG. 33.

FIG. 35 is a schematic diagram of a memory and color converter combination of FIG. 30.

FIG. 36 is a timing diagram of the circuit shown in FIG. 35.

FIG. 37 is a continuation of the timing diagram of FIG. 36.

FIG. 38 is a graphic representation of the TABLE 1.

FIG. 39 is a graphic representation of the TABLE 2.

FIG. 40 is a graph of the ICI chromaticity diagram.

FIG. 41 is a block diagram of a timepiece with variable color digital display and a transducer.

FIG. 42 is a block diagram of a like timepiece characterized by multiplexed outputs.

FIG. 43 is an expanded block diagram of a timepiece with variable color digital display and 3-step color control for all display digits.

FIG. 44 is an expanded block diagram of a like timepiece with 7-step color control for all display digits.

FIG. 45 is an expanded block diagrams of a timepiece with variable color digital display and 3-step color controls for individual display digits.

FIG. 46 is an expanded block diagram of a like timepiece with 7-step color control for individual display digits.

FIG. 47 is an expanded block diagram of a timepiece with 2-LED continuously variable color digital display and color control for all display digits.

FIG. 48 is an expanded block diagram of a like timepiece characterized by 3-LED continuously variable color digital display.

FIG. 49 is an expanded block diagram of a timepiece with 2-LED continuously variable color digital display and color converters for individual display digits.

FIG. 50 is an expanded block diagram of a like timepiece characterized by 3-LED continuously variable color digital display.

FIG. 51 is a schematic diagram of a temperature transducer with interface circuit.

FIG. 52 is a schematic diagram of an atmospheric pressure transducer with interface circuit.

FIG. 53 is a block diagram of a heart rate transducer circuit for controlling the color of the display in steps.

FIG. 54 is a block diagram of a heart rate transducer circuit for controlling the color of the display continuously.

FIG. 55 is a graph showing typical electrocardiogram waves.

FIG. 56 is a detail of the combination of the counter shown generally in FIG. 54 with a memory for 2-primary color converter.

FIG. 57 is a detail of the combination of the counter shown generally in FIG. 54 with a memory for 3-primary color converter.

FIG. 58 is a detail of the counter control shown generally in FIGS. 53 and 54.

FIG. 59 is a schematic diagram of an amplifier and shaping circuit combination in the heart rate transducer circuit shown generally in FIGS. 53 and 54.

FIG. 60 is a timing diagram showing the relationship between the measured R wave and generated COUNTER SAVE and COUNTER CLEAR signals.

FIG. 61 is a schematic diagram of an oscillator shown generally in FIGS. 53 and 54.

FIG. 62 is a detail of the counter and decoder combination shown generally in FIG. 53 for controlling the color of the display in three steps.

FIG. 63 is a chart showing the relationship between the recorded count of the counter shown in FIG. 62, calculated heart rate, and color of the display.

FIG. 64 is a detail of the counter and decoder combination shown generally in FIG. 53 for controlling the color of the display in seven steps.

FIG. 65 is a chart showing the relationship between the recorded count of the counter shown in FIG. 64, calculated heart rate, and color of the display.

Throughout the drawings, like characters indicate like parts.

In the tables which show examples of a relationship between an input voltage, memory contents, and resulting color in the color converter of the present invention,

TABLE 1 shows the characteristic of a step variable 2-primary color converter.

TABLE 2 shows a rainbow-like characteristic of a continuously variable 3-primary color converter.

Throughout the tables, memory addresses and data are expressed in a well known hexadecimal notation.

Referring now, more particularly, to the drawings, in FIG. 1 is shown a block diagram of a typical prior art digital display system which usually includes a device 10a for developing digital data, a suitable decoder 20 for converting the digital data into a displayable code, and a monochromatic digital display 30 for indicating the digital data visually.

As shown in FIG. 2, the present invention resides in the substitution of a commercially well known monochromatic digital display with variable color digital display 40, and in the addition of a color control circuit 50 for controlling the color of the display 40. The variable color digital display system of this invention can simultaneously indicate the values of two different quantities, from the outputs of respective devices 10b, 10c, by causing the value of the first quantity to be indicated in digital format, and by controlling the color of the display in accordance with the value of the second quantity.

In FIG. 3 is shown a block diagram of another embodiment of a variable color digital display system of the present invention, characterized by a step variable color control circuit 51.

In FIG. 4 is shown a block diagram of still another embodiment of variable color digital display system, characterized by a continuously variable color control circuit 56.

In FIG. 5 is shown a block diagram of a 2-primary color display system including a commercially well known 7-segment display decoder driver 22, variable color 7-segment display 42, and 2-primary color control logic circuit 52. The decoder 22 accepts at its inputs A0, A1, A2, A3, a 4-bit BCD (binary coded decimal) code and develops output drive signals at its outputs a, b, c, d, e, f, g, and DP (decimal point), to drive respective segments of the 7-segment display 42. The color control circuit 52 accepts at its input R (red), Y (yellow), and G (green), color control logic signals and develops at its outputs drive signals for the red bus 5 and green bus 6, respectively, to illuminate the display 42 in a selected color.

In FIG. 6 is shown a block diagram of 3-primary color display system including a 7-segment display decoder driver 22, variable color 7-segment display 43, and 3-primary color control logic circuit 53. The color control circuit 53 accepts at its input R (red), Y (yellow), G (green), BG (blue-green), B (blue), P (purple), and W (white), color control logic signals and develops at its outputs drive signals for the red bus 5, green bus 6, and blue bus 7, respectively, to illuminate the display 43 in a selected color.

In FIG. 7, the 2-primary color display element includes seven elongated display segments a, b, c, d, e, f, g, arranged in the conventional pattern, which may be selectively energized in different combinations to display the desired digits. Each display segment includes a pair of LEDs (light emitting diodes): a red LED 2 and green LED 3, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon each other to mix the colors. To facilitate the illustration, the LEDs are designed by segment symbols, e.g., the red LED in the segment a is designated as 2a, etc.

In FIG. 8 the light emitting diodes 2e (red) and 3e (green) are placed on the base of the segment body 15a, which is filled with transparent light scattering material 16. When forwardly biased, the LEDs 2e and 3e emit light signals of red and green colors, respectively, which are scattered within the transparent material 16, thereby blending the red and green light signals into a composite light signal that emerges at the upper surface of the segment body 15a. The color of the composite light signal may be controlled by varying portions of the red and green light signals.

In FIG. 9, each display segment of the 3-primary color display element includes a triad of LEDs: a red LED 2, green LED 3, and blue LED 4, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon one another to mix the colors.

In FIG. 10 the light emitting diodes 2e (red), 3e (green), and 4e (blue) are placed on the base of the segment body 15b, which is filled with transparent light scattering material 16. Red LEDs are typically manufactured by diffusing a p-n junction into a GaAsP epitaxial layer on a GaAs substrate; green LEDs typically use a GaP epitaxial layer on a GaP substrate; blue LEDs are typically made from SiC material.

When forwardly biased, the LEDs 2e, 3e, and 4e emit light signals of red, green, and blue colors, respectively, which are scattered within the transparent material 16, thereby blending the red, green, and blue light signals into a composite light signal that emerges at the upper surface of the segment body 15b. The color of the composite light signal may be controlled by varying the portions of the red, green, and blue light signals.

In FIG. 11 is shown a complete schematic diagram of a one-character 2-primary color common cathodes 7-segment display element which can selectively display various digital fonts in different colors. The anodes of all red and green LED pairs are interconnected in each display segment and are electrically connected to respective outputs of a commercially well known common-cathode 7-segment decoder driver 23. The cathodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g, and 2i are interconnected to a common electric path referred to as a red bus 5. The cathodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3i are interconnected to a like common electric path referred to as a green bus 6.

The red bus 5 is connected to the output of a tri-state inverting buffer 63a, capable of sinking sufficient current to forwardly bias all red LEDs in the display. The green bus 6 is connected to the output of a like buffer 63b. The two buffers 63a, 63b can be simultaneously enabled by applying a logic low level signal to the input of the inverter 64a, and disabled by applying a logic high level signal therein. When the buffers 63a, 63b are enabled, the conditions of the red and green buses can be selectively controlled by applying suitable logic control signals to the bus control inputs RB (red bus) and GB (green bus), to illuminate the display in a selected color. When the buffers 63a, 63b are disabled, both red and green buses are effectively disconnected and the display is completely extinguished.

In FIG. 12 is shown a complete schematic diagram of a one-character 3-primary color common anodes 7-segment display element which can selectively display digital fonts in different colors. The cathodes of all red, green, and blue LED triads in each display segment are interconnected and electrically connected to respective outputs of a commercially well known common anode 7-segment decoder driver 24. The anodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g are interconnected to form a common electric path referred to as a red bus 5. The anodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g are interconnected to form a like common electric path to as a green bus 6. The anodes of all blue LEDs 4a, 4b, 4c, 4d, 4e, 4f, 4g are interconnected to form a like common electric path referred to as a blue bus 7.

The red bus 5 is connected to the output of a non-inverting tri-state buffer 62a, capable of sourcing sufficient current to illuminate all red LEDs in the display. The green bus 6 is connected to the output of a like buffer 62b. The blue bus 7 is connected to the output of a like buffer 62c. The three buffers 62a, 62b, 62c can be simultaneously enabled, by applying a logic low level signal to the input of the inverter 64b, and disabled by applying a logic high level signal therein. When the buffers 62a, 62b, 62c are enabled, the conditions of the red, green, and blue buses can be selectively controlled by applying valid combinations of logic level signals to the bus control inputs RB (red bus), GB (green bus), and BB (blue bus), to illuminate the display in a selected color. When the buffers 62a, 62b, 62c are disabled, all three buses are effectively disconnected and the display is completely extinguished.

In FIG. 13 is shown a logic circuit 69a for developing drive signals for the red bus 5 and green bus 6, to control the color of the display element 42 shown in FIG. 11. Two voltage levels, referred to as logic high and low, respectively, are used throughout the description of the digital circuits. The color of the display 42 may be controlled by applying valid combinations of logic level signals to its color control inputs R (Red), Y (Yellow), and G (Green). The logic circuit 69a combines the input signals in a logic fashion and develops output drive signals RB (Red Bus) and GB (Green Bus), for activating the red bus 5 and green bus 6, respectively, of the display 42.

In FIG. 14 is shown a like logic circuit 69b for developing drive signals for the red bus 5, green bus 6, and blue bus 7, to control the color of the display element 43 shown in FIG. 12. The color of the display 43 may be controlled by applying valid combinations of logic level signals to its color control inputs B (Blue), P (Purple), BG (Blue-Green), G (Green), Y (Yellow), W (White), and R (Red). The logic circuit 69b combines the input signals in a logic fashion and develops output drive signals RB (Red Bus), GB (Green Bus), and BB (Blue Bus), for activating the red bus 5, green bus 6, and blue bus 7, respectively, of the display 43.

Exemplary schematic diagrams of the clor control logic circuits shown in FIGS. 15 and 16 consider active high logic levels, which means that only the selected color control input are maintained at a high level, while all remaining color control inputs are maintained at a low logic level. The circuit in FIG. 15 is a detail of the color control logic circuit 69a employing 2-input logic OR gates 60a, 60b, interposed between the color control inputs R, Y, G and bus control outputs RB, GB, in a manner which will become more apparent from the description below. A like circuit in FIG. 16 is a detail of the color control logic circuit 69b employing 4-input logic OR gates 61a, 61b, 61c similarly interposed between the color control inputs B, P, BG, G, Y, W, R and bus control outputs RB, GB, BB. It will be obvious to those skilled in the art that other types of logic devices may be effectively used.

The operation of the 2-primary color 7-segment display will be now explained in detail on example of illuminating the digit `7` in three different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 17. Any digit between 0 and 9 can be selectively displayed by applying the appropriate BCD code to the inputs A0, A1, A2, A3 of the common-cathode 7-segment decoder driver 23. The decoder 23 will develop at its outputs a, b, c, d, e, f, g, and DP, the drive signals for energizing selected groups of the segments to thereby visually display the selected number, in a manner well known to those having ordinary skill in the art. To display decimal number `7`, a BCD code 0111 is applied to the inputs A0, A1, A2, A3. The decoder 23 will develop high voltage levels at its outputs a, b, c, to illuminate the respective segments a, b, c, and low voltage levels at all remaining outputs (not shown), to extinguish all remaining segments.

To illuminate the display in red color, the color control input R is raised to a high logic level, and the color control inputs Y and G are maintained at a low logic level. As a result, the output of the OR gate 60a will rise to a high logic level, thereby causing the output of the buffer 63a to drop to a low logic level. The current will flow from the ouput a of the decoder 23, via red LED 2a, red bus 5, to the current sinking output of the buffer 63a. Similarly, the current will flow from the output b of the decoder 23, via red LED 2b, red bus 5, to the output of the buffer 63a. The current from the output c of the decoder 23 will flow via red LED 2c, red bus 5, to the output of the buffer 63a. As a result, the segments a, b, c will illuminate in red color, thereby causing a visual impression of a character `7`. The green LEDs 3a, 3b, 3c will remain extinguished because the output of the buffer 63b is at a high logic level, thereby disabling the green bus 6.

To illuminate the display in green color, the color control input G is raised to a high logic level, while the color control inputs R and Y are maintained at a low logic level. As a result, the output of the OR gate 60b will rise to a high logic level, thereby causing the output of the buffer 63b to drop to a low logic level. The current will flow from the output a of the decoder 23, via green LED 3a, green bus 6, to the current sinking output of the buffer 63b. Similarly, the current will flow from the output b of the decoder 23, via green LED 3b, green bus 6, to the output of the buffer 63b. The current from the output c of the decoder 23 will flow, via green LED 3c, green bus 6, to the output of the buffer 63b. As a result, the segments a, b, c will illuminate in green color. The red LEDs 2a, 2b, 2c will remain extinguished because the output of the buffer 63a is at a high logic level, thereby disabling the red bus 5.

To illuminate the display in yellow color, the color control input Y is raised to a high logic level, while the color inputs R and G are maintained at a low logic level. As a result, the outputs of both OR gates 61a, 61b will rise to a high logic level, thereby causing the outputs of both buffers 63a, 63b to drop to a low logic level. The current will flow from the output a of the decoder 23, via red LED 2a, red bus 5, to the current sinking output of the buffer 63a, and, via green LED 3a, green bus 6, to the current sinking output of the buffer 63b. Similarly, the current from the output b of the decoder 23 will flow, via red LED 2b, red bus 5, to the output of the buffer 63a, and, via green LED 3b, green bus 6, to the output of the buffer 63b. The current from the output c of the decoder 23 will flow, via red LED 2c, red bus 5, to the output of the buffer 63a, and, via green LED 3c, green bus 6, to the output of the buffer 63b. As a result of blending light of red and green color in each segment, the segments a, b, c will illuminate in substantially yellow color.

The operation of the 3-primary color 7-segment display shown in FIG. 12 will be now explained in detail on example of illuminating the digit `1` in seven different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 18. To display decimal number `1`, a BCD code 0001 is applied to the inputs A0, A1, A2, A3 of the common anode 7-segment decoder driver 24. The decoder 24 will develop low voltage levels at its outputs b, c to illuminate the segments b, c, and high voltage levels at all remaining outputs (not shown), to extinguish all remaining segments.

To illuminate the display in red color, the color control input R is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of the OR gate 61a will rise to a high logic level, thereby causing the output of the buffer 62a to rise to a high logic level. The current will flow from the output of the buffer 62a, via red bus 5, red LED 2b, to the output b of the decoder 24, and, via red LED 2c, to the output c of the decoder 24. As a result, the segments b, c will illuminate in red color, thereby causing a visual impression of a character `1`. The green LEDs 3b, 3c and blue LEDs 4b, 4c will remain extinguished because the green bus 6 and blue bus 7 are disabled.

To illuminate the display in green color, the color control input G is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of the OR gate 61b will rise to a high logic level, thereby causing the output of the buffer 62b to rise to a high logic level. The current will flow from the output of the buffer 62b, via green bus 6, green LED 3b, to the output b of the decoder 24, and, via green LED 3c, to the output c of the decoder 24. As a result, the segments b, c will illuminate in green color.

To illuminate the display in blue color, the color control input B is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of the OR gate 61c will rise to a high logic level, thereby causing the output of the buffer 62c to rise to a high logic level. The current will flow from the output of the buffer 62c, via blue bus 7, blue LED 4b, to the output b of the decoder 24, and, via blue LED 4c, to the output c of the decoder 24. As a result, the segments b, c will illuminate in blue color.

To illuminate the display in yellow color, the color control input Y is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of the OR gates 61a, 61b will rise to a high logic level, thereby causing the outputs of the buffers 62a, 62b to rise to a high logic level. The current will flow from the output of the buffer 62a, via red bus 5, red LED 2b, to the output b of the decoder 24, and, via red LED 2c, to the output c of the decoder 24. The current will also flow from the output of the buffer 62b, via green bus 6, green LED 3b, to the output b of the decoder 24, and, via green LED 3c, to the output c of the decoder 24. As a result of blending light of red and green colors in each segment, the segments b, c will illuminate in substantially yellow color.

To illuminate the display in purple color, the color control input P is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of the OR gates 61a, 61c will rise to a high logic level, thereby causing the outputs of the buffers 62a, 62c to rise to a high logic level. The current will flow from the output of the buffer 62a, via red bus 5, red LED 2b, to the output b of the decoder 24, and, via red LEd 2c, to the output c of the decoder 24. The current will also flow from the output of the buffer 62c, via blue bus 7, blue LED 4b, to the output b of the decoder 24, and, via blue LED 4c, to the output c of the decoder 24. As a result of blending light of red and blue color in each segment, the segments b, c will illuminate in substantially purple color.

To illuminate the display in blue-green color, the color control input BG is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of the OR gates 61b, 61c will rise to a high logic level, thereby causing the outputs of the buffers 62b, 62c to rise to a high logic level. The current will flow from the output of the buffer 61b, via green bus 6, green LED 3b, to the output b of the decoder 24, and, via green LED 3c, to the output c of the decoder 24. The current will also flow from the output of the decoder 62c, via blue bus 7, blue LED 4b, to the output b of the decoder 24, and, via blue LED 4c, to the output c of the decoder 24. As a result of blending light of green and blue colors in each segment, the segments b, c will illuminate in substantially blue-green color.

To illuminate the display in white color, the color control input W is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of the OR gates 61a, 61b, 61c will rise to a high logic level, theeby causing the outputs of the respective buffers to rise to a high logic level. The current will flow from the output of the buffer 62a, via red bus 5, red LED 2b, to the output b of the decoder 24, and, via red LED 2c, to the output c of the decoder 24. The current will also flow from the output of the buffer 62b, via green bus 6, green LED 3b, to the output b of the decoder 24, and, via green LED 3c, to the output c of the decoder 24. The current will also flow from the output of the buffer 62c, via blue bus 7, blue LED 4b, to the output b of the decoder 24, and, via blue LED 4c, to the output c of the decoder 24. As a result of blending light of red, green, and blue colors in each segment, the segments b, c will illuminate in substantially white color.

Since the outputs of the 7-segment decoder 24 may be overloaded by driving a triad of LEDs in parallel in the display 43, rather than a single LED in a monochromatic display, it would be obvious to employ suitable buffers to drive respective color display segments (not shown).

To illustrate how the present invention can be utilized in a multi-element variable color display configuration, in FIG. 19 is shown a detail of the interconnection in a 2-primary color 4-digit display. The color control inputs R, Y, G of all display elements 46a, 46b, 46d are interconnected, respectively, and the enable inputs E1, E2, E3, E4 are used to control the conditions of respective display elements. A high logic level at the enable input E will extinguish the particular display element; a low logic level therein will illuminate the element in a color determined by the instant conditions of the color control logic inputs R, Y, G.

In FIG. 20 is shown a like detail of the interconnection in a 3-primary color 4-digit display. Similarly, the color control inputs B, P, BG, G, Y, W, R of all display elements 47a, 47b, 47c, 47d are interconnected and the conditions of respective display elements are controlled by the enable inputs E1, E2, E3, E4. A high logic level at the enable input E will extinguish the particular display element; a low logic level therein will illuminate the element in a color determined by the instant conditions of the color control logic inputs B, P, BG, G, Y, W, R.

It is readily apparent that a multi-element variable color digital display may be constructed, in accordance with the principles of the invention, either in a common cathodes or in a common anodes configuration. The exemplary color control circuits described herein will cooperate equally well with both such configurations.

The enable inputs E1, E2, E3, E4 may be utilized to control the variable color multi-digit display in a multiplexed configuration, wherein the color codes for the display digits are presented in a sequence, one at a time, at a relatively fast rate, while the particular display digit is enabled.

In FIG. 21 is shown a block diagram of a signal converter for developing color control logic signals for 2-primary color display. The signal converter 85a accepts at its input voltage from a variable analog voltage source 11 and develops at its outputs color control logic signals R, Y, G, having relation to the magnitude of instant input analog voltage, for controlling the color of the variable color display 42, shown in FIGS. 11 and 15, in accordance with the magnitude of input voltage.

In FIG. 22 is shown a block diagram of a like signal converter for developing color control logic signals for 3-primary color display. The signal converter 85b accepts at its inputs voltage from a source 11 and develops output color control logic signals B, P, BG, G, Y, W, R, related to the magnitude of instant input analog voltage, for controlling the color of the variable color display 43, shown in FIGS. 12 and 16, in accordance with the magnitude of input voltage.

In FIG. 23, the output voltage of a variable analog voltage source 11 is applied to the interconnected inputs of two analog comparators 82a, 82b, in a classic `window` comparator configuration. When the voltage developed by the source 11 is lower than the low voltage limit Vlo, set by a potentiometer 92a, the output of the comparator 82a will drop to a low logic level, thereby forcing the output of the inverter 65a to rise to a high logic level, to activate the color control logic input Y of the display element 42, shown in FIGS. 11 and 15, to thereby illuminate the display in yellow color.

When the voltage developed by the source 11 is higher than the high voltage limit Vhi, set by a potentiometer 92b, the output of the comparator 82b will drop to a low logic level, thereby forcing the output of the inverter 65b to rise to a high logic level, to activate the color control logic input R, to thereby illuminate the display 42 in red color.

When the voltage developed by the source 11 is between the low voltage limit Vlo and high voltage limit Vhi, the outputs of the comparators 82a, 82b will rise to a high logic level, thereby causing the output of the AND gate 66 to rise to a high logic level, to activate the color control logic input G, to thereby illuminate the display 42 in green color.

FIG. 24 is a graph depicting the relationship between the input voltage of the comparator circuit shown in FIG. 23 and the color of the display element shown in FIG. 11. The display element will illuminate in yellow color for the input voltage lower than the limit Vlo, in green color for the input voltage between the limits Vlo and Vhi, and in red color for the input voltage higher than the limit Vhi.

In FIG. 25, the output voltage of a variable analog voltage source 11 is applied to the interconnected `+` inputs of six analog comparators 82c, 82d, 82e, 82f, 82g, 82h, connected in a well known `multiple aperture window` configuration. There are six progressively increasing voltage limits V1 to V6, set by respective potentiometers 92c to 92h. The outputs of the comparators 82c to 82h are respectively connected, via inverters 65c to 65h, to the inputs I1 to I7 of a priority encoder 67. Each of the inputs I1 to I7 has assigned a certain priority (from I1 being the lowest priority progressively to I7 being the highest one). The priority encoder 67 will develop at its outputs 00, 01, 02 a code identifying the highest priority input activated. The outputs of the encoder 67 are respectively connected, via inverters 65j to 65m, to the inputs A0, A1, A2 of a 3-to-8 line decoder 68, to decode the outputs of the encoder 67 into seven mutually exclusive active logic low outputs Y1 to Y7. The outputs Y1 to Y7 are respectively connected, via inverters 65p to 65v, to the color control logic inputs B, P, BG, G, Y, W, R of the display element 43 shown in the FIGS. 12 and 16.

When the output voltage of the source 11 is lower than the lowest voltage limit V1, the output of the comparator 82c will drop to a low logic level, thereby activating the input I1 of the priority encoder 67. The code 110 developed at the outputs 00, 01, 02 will be inverted by the inverters 65j to 65m to yield the code 001 which will produce a low logic level at the output Y1, to force, via the inverter 65p, the color control logic input B to a high logic level. The display 43 will illuminate in blue color.

When the output voltage of the source 11 is between the adjacent voltage limits, e.g., V4 and V5, the output of the comparator 82f will rise to a high logic level, thereby activating the input I5 of the priority encoder 67. The code 100 developed at the inputs of the decoder 68 will produce a high logic level at the color control logic input Y and the display 43 will illuminate in yellow color.

FIG. 26 is a graph depicting the relationship between the input voltage of the comparator circuit shown in FIG. 25 and the color of the display element shown in FIG. 12. The display element will illuminate in blue color for the input voltage lower than the limit V1, in purple color for the input voltage between the limits V1 and V2, in blue-green color for the input voltage between the limits V2 and V3, in green color for the input voltage between the limits V3 and V4, in yellow color for the input voltage between the limits V4 and V5, in white color for the input voltage between the limits V5 and V6, and in red color for the input voltage higher than the limit V6.

It would be obvious to those having ordinary skill in the art, in the view of this disclosure, that the color sequences could be readily changed by differently interconnecting the outputs of the comparator circuit with the color control logic inputs of the display element.

FIG. 27 is a block diagram of a 2-LED continuously variable color display system, which includes a device 10 for developing electric signals and 2-LED color converter circuit 57 for controlling the red bus 5 and green bus 6, respectively, of the 2-LED variable color display 42 in accordance with the electric signals.

FIG. 28 is a block diagram of 3-LED continuously variable color display system which differs from the like system shown in FIG. 27 in that a 3-LED color converter circuit 58 is utilized to control the red bus 5, green bus 6, and blue bus 7, respectively, of the 3-LED variable color display 43, in accordance with the electric signals developed by the device 10.

The display system shown in FIG. 29 utilizes a scaling circuit 80a which scales input analog voltage levels to a voltage range suitable for an A/D converter 74a, which in turn develops at its outputs digital code having relation to the value of the input analog voltage. The output lines of the A/D converter 74a are connected to the address inputs of a memory 76 having a plurality of addressable locations which contain data indicating the portions of red color for several different values of the input analog voltage. The output data of the memory 76 are applied to the inputs of a color converter 57 which will develop control signals for the red bus 5 and green bus 6, respectively, of the variable color display 42.

The display system shown in FIG. 30 utilizes a scaling circuit 80b and an A/D converter 74b for converting the instant value of input analog voltage to a digital code. The outputs of the A/D converter 74b are connected, in parallel, to the address inputs of a memory 76a, which contains data indicating the portions of red color, to the address inputs of a memory 76b, which contains data indicating the portions of green color, and to the address inputs of a memory 76c, which contains data indicating the portions of blue color. The output data of the memory 76a are applied to the red color converter 59a which will develop control signals for the red bus 5 of the variable color display 43. The output data of the memory 76b are applied to the green color converter 59b which will develop control signals for the green bus 6 of the display 43. The output data of the memory 76c are applied to the blue color converter 59c which will develop control signals for the blue bus 7 of the display 43.

FIG. 31 is a schematic diagram of a scaling circuit capable of shifting and amplifying the input voltage levels. The circuit utilizes two operational amplifiers 81a, 81b in a standard inverting configuration. The amplifier 81a is set for a unity gain, by using resistors 90a, 90b of equal values; the potentiometer 92a is adjusted to set a desired offset voltage. The amplifier 81b will set the gain, by adjusting the potentiometer 92b, to a desired value. As a result, the input voltage, which may vary between arbitrary limits Vlow and Vhigh, may be scaled and shifted to the range between 0 Volts and 9.961 Volts, to facilitate the use of a commercially available A/D converter.

FIG. 32 is a schematic diagram of an A/D (analog-to-digital) converter 75 which is capable of converting input analog voltage to 8-bit digital data for addressing a memory 77. The conversion may be initiated from time to time by applying a short positive pulse 99a to the Blank and Convert input B&C. The converter 75 will thereafter perform a conversion of the instant input voltage to 8-bit data indicative of its value. When the conversion is completed, the Data Ready output DR drops to a low logic level, thereby indicating that the data are available at the outputs Bit 1 to Bit 8, which are directly connected to respective address inputs A0 to A7 of the memory 77. When the DR output drops to a low logic level, the Chip Select input CS of the memory 77 is activated, the memory 77 is enabled, and the data, residing at the address selected by the instant output of the converter 75, will appear at its data outputs D0 to D7.

The description of the schematic diagram in FIG. 33 should be considered together with its accompanying timing diagram shown in FIG. 34. A clock signal 99b of a suitable frequency (e.g., 10 kHz), to provide a flicker-free display, is applied to the Clock Pulse inputs CP of the 8-bit binary counters 71e, 71f, to step same down. At the end of each counter cycle, which takes 256 clock cycles to complete, the Terminal Count output TC of the counter 71e will drop to a low logic level for one clock cycle, to thereby indicate that the lowest count was reached. The negative pulse 99c at the TC output of the counter 71e, which is connected to the Parallel Load input PL of the counter 71f, will cause the instant data at the outputs of the memory 76 to be loaded into the counter 71f. The data at the memory represent the portion of the red color; the portion of the green color is complementary. The rising edge of the TC pulse 99c will trigger the flip-flop 73 into its set condition wherein its output Q rises to a high logic level.

The counter 71f will count down, from the loaded value, until it reaches zero count, at which moment its TC output will drop to a low logic level. The negative pulse at the TC output of the counter 71f, which is connected to the Clear Direct input CD of the flip-flop 73, will cause the latter to be reset and to remain in its reset condition until it is set again at the beginning of the next 256-count cycle. It is thus obvious that the Q output of the flip-flop 73 will be at a high logic level for a period of time proportional to the data initially loaded into the counter 71f. The complementary output Q will be at a high logic level for a complementary period of time.

The Q and Q outputs of the flip-flop 73 are connected to the red bus 5 and green bus 6, respectively, via suitable buffers 63a, 63b, shown in detail in FIG. 11, to energize the respective buses for variable time periods, depending on the data stored in the memory 76.

By referring now, more particularly, to the timing diagram shown in FIG. 34, in which the waveforms are compressed to facilitate the illustration, the EXAMPLE 1 considers the memory data `FD`, in a standard hexadecimal notation, to generate light of substantially red color. At the beginning of the counter cycle, the pulse 99c loads the data `FD` into the counter 71f. Simultaneously, the flip-flop 73 is set by the rising edge of the pulse 99c. The counter 71f will be thereafter stepped down, by clock pulses 99b, until it reaches zero count, 2 clock cycles before the end of the counter cycle. At that instant a short negative pulse 99d will be produced at its output TC to reset the flip-flop 73, which will remain reset for 2 clock cycles and will be set again by the pulse 99c at the beginning of the next counter cycle, which will repeat the process. It is readily apparent that the flip-flop 73 was set for 254 clock cycles, or about 99% of the time, and reset for 2 clock cycles, or about 1% of the time. Accordingly, the red bus 5 of the display 42 will be energized for about 99% of the time, and the green bus 6 will be energized for the remaining about 1% of the time. As a result, the display 42 will illuminate in substantially red color.

The EXAMPLE 2 considers the memory data `02` (HEX) to generate light of substantially green color. At the beginning of the counter cycle, the data `02` is loaded into the counter 71f, and, simultaneously, the flip-flop 73 will be set. The counter 71f will count down and will reach zero count after 2 clock cycles. At that instant it will produce at its output TC a negative pulse 99e to reset the flip-flop 73. It is readily apparent that the flip-flop 73 was set for 2 clock cycles, or about 1% of the time, and reset for 254 clock cycles, or about 99% of the time. Accordingly, the red bus 5 of the display 42 will be energized for about 1% of the time, and the green bus 6 will be energized for the remaining about 99% of the time. As a result, the display 42 will illuminate in substantially green color.

The EXAMPLE 3 considers the memory data `80` (HEX) to generate light of substantially yellow color. At the beginning of the counter cycle, the data `80` are loaded into the counter 71f, and, simultaneously, the flip-flop 73 is set. The counter 71f will count down, and will reach zero count after 128 clock cycles. At that instant it will produce at its output TC a negative pulse 99f to reset the flip-flop 73. It is readily apparent that the flip-flop 73 was set for 128 clock cycles, or about 50% of the time, and reset for 128 clock cycles, or about 50% of the time. Accordingly, the red bus 5 of the display 42 will be energized for about 50% of the time, and the green bus 6 will be energized for the remaining about 50% of the time. As a result of blending substantially equal portions of red and green colors, the display 42 will illuminate in substantially yellow color.

The description of the schematic diagram of a 3-LED color converter in FIG. 35 should be taken together with its accompanying timing diagrams shown in FIGS. 36 and 37. A clock signal 99b is applied to the CP inputs of the counters 71d, 71a, 71b, 71c, to step same down. Every 256 counts a negative pulse 99c is generated at the TC output of the counter 71d, to load data into the counters 71a, 71b, 71c from respective memories 76a, 76b, 76c, and to set the flip-flops 73a, 73b, 73c. The data in the RED memory 76a represent the portions of the red color, the data in the GREEN memory 76b represent the portions of the green color, and the data in the BLUE memory 76c represent the portions of the blue color to be blended together.

The counters 71a, 71b, 71c will count down, from the respective loaded values, until zero counts are reached. When the respective values of the loaded data are different, the length of time of the count-down will be different for each counter. When a particular counter reaches zero count, its TC output will momentarily drop to a low logic level, to reset its associated flip-flop (the RED counter 71a resets its RED flip-flop 73a, etc.). Eventually, all three flip-flops 73a, 73b, 73c will be reset. The Q outputs of the flip-flops 73a, 73b, 73c are connected to the red bus 5, green bus 6, and blue bus 7, respectively, via suitable buffers 62a, 62b, 62c, as shown in FIG. 12, to energize the respective buses for variable periods of time.

By referring now more particularly to the timing diagram shown in FIGS. 36 and 37, the EXAMPLE 4 considers the red memory data `80`, green memory data `00`, and blue memory data `80`, all in hexadecimal notation, to generate light of substantially purple color. At the beginning of the counter cycle, the pulse 99c will simultaneously load the data `80` from the red memory 76a into the red counter 71a, data `00` from the green memory 76b into the green counter 71b, and data `80` from the blue memory 76c into the blue counter 71c. The counters 71a, 71b, 71c will be thereafter stepped down. The red counter 71a will reach its zero count after 128 clock cycles; the green counter 71b will reach its zero count immediately; the blue counter 71c will reach its zero count after 128 clock cycles.

It is readily apparent that the red flip-flop 73a was set for 128 clock cycles, or about 50% of the time, the green flip-flop 73b was never set, and the blue flip-flop 73c was set for 128 clock cycles, or about 50% of the time. Accordingly, the red bus 5 of the display 43 will be energized for about 50% of the time, green bus 6 will never be energized, and blue bus 7 will be energized for about 50% of the time. As a result of blending together substantially equal portions of red and blue colors, the display 43 will illuminate in substantially purple color.

The EXAMPLE 5 considers the red memory data `00`, green memory data `00`, and blue memory data `80`, to generate light of substantially blue-green color. At the beginning of the counter cycle, the data `00` are loaded into the red counter 71a, data `80` are loaded into the green counter 71b, and data `80` are loaded into the blue counter 71c. The red counter 71a will reach its zero count immediately, the green counter 71b will reach its zero count after 128 clock periods, and so will the blue counter 71c.

The red flip-flop 73a was never set, the green flip-flop 73b was set for 128 clock pulses, or about 50% of the time, and so was the blue flip-flop 73c. Accordingly, the green bus 5 of the display 43 will be energized for about 50% of the time, and so will be the blue bus. As a result, the display 43 will illuminate in substantially blue-green color.

The EXAMPLE 6 considers the red memory data `40`, green memory data `40`, and blue memory data `80`, to generate light of substantially cyan color. At the beginning of the counter cycle, the data `40` are loaded into the red counter 71a, data `40` are loaded into the green counter 71b, and data `80` are loaded into the blue counter 71c. The red counter 71a will reach its zero count after 64 clock cycles, and so will the green counter 71b. The blue counter 71c will reach its zero count after 128 clock cycles.

The red flip-flop 73a was set for 64 clock cycles, or about 25% of the time, and so was the green flip-flop 73b. The blue flip-flop 73c was set for 128 clock periods, or about 50% of the time. Accordingly, the red bus 5 and green bus 6 of the display 43 will be energized for about 25% of the time, and the blue bus 7 will be energized for about 50% of the time. As a result of blending about 50% of blue color, 25% of red color, and 25% of green color, the display 43 will illuminate in substantially cyan color.

The EXAMPLE 7 considers the red memory data `80`, green memory data `40`, and blue memory data `40`, to generate light of substantially magenta color. At the beginning of the counter cycle, the data `80` are loaded into the red counter 71a, data `40` are loaded into the green counter 71b, and data `40` are loaded into the blue counter 71c. The red counter 71a will reach its zero count after 128 clock cycles, the green counter 71b will reach its zero count after 64 clock cycles, and so will the blue counter 71c.

The red flip-flop 73a was set for 120 clock cycles, or about 50% of the time, the green flip-flop 73b and blue flip-flop 73c were set for 64 clock cycles, or about 25% of the time. Accordingly, the red bus 5 of the display 43 will be energized for about 50% of the time, green bus 6 and blue bus 7 will be energized for about 25% of the time. As a result, the display 43 will illuminate in substantially magenta color.

By referring now more particularly to FIGS. 38 and 39, which are graphic representations of the TABLES 1 and 2, respectively, the data at each memory address are digital representation of the portion of the particular primary color. All examples consider an 8-bit wide PROM (Programmable Read Only Memory). However, the principles of the invention could be applied to other types of memories.

In FIG. 38 the RED PORTION indicates the portion of red primary color; the GREEN PORTION indicates the portion of green primary color. The RED PORTION for a particular memory address was calculated by dividing the actual value of data residing at that address by the maximum possible data `FF` (HEX). The GREEN PORTION for the same memory address is complementary; it was obtained by subtracting the calculated value of the RED PORTION from number 1.0.

In FIG. 38 is shown the characteristic of 2-primary color converter, defined in the TABLE 1, for developing color variable in steps: pure green for input voltages less than 0.625 V, substantially yellow for voltages between 1.25 V and 1.875 V, pure red for voltages between 2.5 V and 3.125 V, and of intermediate colors therebetween, this sequence being repeated three times over the voltage range.

In FIG. 39 the RED PORTION indicates the portion of red primary color; the GREEN PORTION indicates the portion of green primary color; the BLUE PORTION indicates the portion of blue primary color. The RED PORTION for a particular memory address was calculated by dividing the value of RED data residing at such address by the maximum possible data `FF` (HEX). Similarly, the GREEN PORTION for that memory address was obtained by dividing the value of GREEN data by `FF` (HEX). The BLUE PORTION was obtained by dividing the value of BLUE data by `FF` (HEX).

In FIG. 39 is shown the characteristic of 3-primary color converter, defined in the TABLE 2, for developing color continuously variable from pure red, through substantially orange and yellow, pure green, pure blue, to substantially purple, in a rainbow-like fashion.

In the examples of the characteristics of color converters, shown in the TABLE 1 to TABLE 2, the data values stored in the red, green, and blue memories are so designed that the sums of the red data, green data, and blue data are constant for all memory addresses, to provide uniform light intensities for all colors. It is further contemplated that data stored in the red, green, and blue memories may be modified in order to compensate for different efficiencies of red, green, and blue LEDs. By way of an example, data values for a low efficiency LED may be proportionally incremented such that time of energization is proportionally increased, to effectively provide equal luminances for LEDs of unequal efficiencies.

With reference to FIG. 40 there is shown the ICI (International Committee on Illumination) chromaticity diagram designed to specify a particular color in terms of x and y coordinates. Pure colors are located along the horseshoe-like periphery. Reference numbers along the periphery indicate wavelength in nanometers. When relative portions of three primary colors are known, the color of light produced by blending their emissions can be determined by examining the x and y values of ICI coordinates.

FIG. 41 is a generalized block diagram of a timepiece with transducer of this invention which includes a timekeeping device 301 for keeping time and for developing output electrical signals indicative of time, a digital decoder driver 21 for converting the timekeeping device's output electrical signals into a displayable code, and variable color digital display 40 for indicating time in digital format. The invention resides in the addition of a transducer 310 for measuring a physical quantity and for developing output electrical signals related to values of such physical quantity, and of a color converter circuit 55 for converting output electrical signals of the transducer 310 to color control signals for controlling the color of the display 40. The display 40 will thus simultaneously indicate time, in digital format, and values of the measured physical quantity, in variable color.

The timekeeping device 301 typically contains a high frequency accurate time standard signal generator and a chain of frequency dividers for providing highly stable clock signal of 1 Hz frequency which drives the seconds, minutes, and hours counters (not shown). The digital decoder driver 21 continuously converts output signals of such counters to suitable codes for driving multidigit display 40, in a manner well understood by those skilled in the art.

The term transducer, as used throughout the description of the invention, is used in its widest sense so as to include every type of a device for performing a conversion of one type of energy to another. The principles of the invention may be applied to various displacement, motion, force, pressure, sound, flow, temperature, humidity, weight, magnetic, and physiological transducers and the like.

A physiological transducer is defined for the purpose of this invention as means for producing electrical signals which represent physiological conditions or events in a human body or other living matter.

A timepiece shown in a schematic diagram in FIG. 43 includes a stopwatch chip 304 for developing multiplexed segment drive signals a, b, c, d, e, f, and g to directly drive a 4-digit 2-LED variable color digital display 44, which will indicate time in hours (on digits H10 and H1) and minutes (on digits M10 and M1), in a manner well understood by those skilled in the art. The multiplexing enable signals Cath1, Cath2, Cath3, and Cath4 are utilized to sequentially enable respective digits of the display 44, as shown in the detail in FIG. 19, at a relatively fast rate, to thereby provide a flicker-free display in a color determined by the instant conditions of the color control inputs R, Y, and G.

The invention resides in the addition of a transducer 310 for developing electrical signals related to values of the measured physical quantity, and a signal converter 85i, for converting the transducer's output electrical signals to color control signals R, Y, and G, as shown in the detail in FIGS. 21 and 23, to thereby control the color of the display 44 in three steps in accordance with the values of the measured physical quantity.

In FIG. 44 is shown a like schematic diagram of a timepiece, which differs from the one shown in FIG. 43 in that a 4-digit 3-LED variable color digital display 45 and a signal converter 85j are utilized for converting the transducer's output electrical signals to color control signals B, P, BG, G, Y, W, and R, as shown in the detail in FIGS. 22 and 25, to control the color of the display 45 in seven steps in accordance with the values of the measured physical quantity. The detail of the interconnection of the four display digits is shown in FIG. 20.

In FIG. 45 is shown a schematic diagram of a timepiece which differs from a like diagram shown in FIG. 43 in that four transducers 310a, 310b, 310c, and 310d with associated signal converters 85m, 85n, 85p, 85r and color control circuits 52a, 52b, 52c, 52d are used to independently control the color of respective display digits in three steps. The display 44 will indicate time in digital format and each display digit will illuminate in a color in accordance with the value of a physical quantity measured by the associated transducer.

In FIG. 46 is shown a schematic diagram of a timepiece utilizing four transducers 310a, 310b, 310c, and 310d with associated signal converters 85s, 85t, 85u, 85v and color control circuits 53a, 53b, 53c, 53d to independently control the color of respective display digits of the display 45 in seven steps in accordance with four different physical quantities measured by respective transducers.

In FIG. 47 is shown a schematic diagram of a timepiece characterized by a 2-primary color converter 57 for converting output electrical signals of the transducer 310 to drive signals RB (for the red bus) and GB (for the green bus), as shown in the detail in FIGS. 29 to 34, to control the color of the 4-digit 2-LED variable color digital display substantially continuously in accordance with the values of the physical quantity measured by the transducer such that the color changes of the display are proportional to changes in the values of the physical quantity.

Similar schematic diagram of a timepiece shown in FIG. 48 differs from the one shown in FIG. 47 in that a 3-primary color converter 58 is utilized for converting output electrical signals of the transducer 310 to drive signals RB, GB and BB (for the blue bus), as shown in the detail in FIGS. 30, 35 to 37, to control the color of 4-digit 3-LED variable color digital display substantially continuously in accordance with the values of the physical quantity measured by the transducer such that the color changes of the display are proportional to changes in the values of the physical quantity.

In FIG. 49 is shown a schematic diagram of a timepiece which differs from a like diagram shown in FIG. 47 in that four transducers 310a, 310b, 310c, and 310d with associated 2-primary color converters 57a, 57b, 57c, and 57d are used to independently control the color of respective display digits of the 4-digit 2-LED display 44 substantially continuously in accordance with four different physical quantities measured by respective transducers.

In FIG. 50 is shown a schematic diagram of a timepiece utilizing four transducers 310a, 310b, 310c, and 310d with associated 3-primary color converters 58a, 58b, 58c, and 58d to independently control the color of respective display digits of the 4-digit 3-LED display 45 substantially continuously in accordance with four different physical quantities measured by respective transducers.

In a schematic diagram shown in FIG. 51, temperature transducer 312 measures ambient temperature and develops at its output a current which is linearly proportional to measured temperature in degrees Kelvin. The current flows through a resistor 323e of suitable value (e.g., 1 k Ohm), to develop voltage proportional to the measured temperature, which is applied to the input of an op amp 331c. To read at the op amp's output OUT voltage that directly corresponds to temperature in degrees Celsius, the other input of the op amp is offset by 273.2 mV. The invention resides in utilizing the output voltage at the terminal OUT to develop color control signals for causing the display to illuminate in a color related to the measured ambient temperature. To achieve this, the terminal OUT may be connected as shown in the detail either in FIG. 23, to control the color of the display in three steps, or in FIG. 25, to control the color of the display in seven steps, or in FIGS. 29 and 30, to control the color of the display continuously.

In a schematic diagram shown in FIG. 52, the pressure transducer 314 measures atmospheric pressure and develops at its output a voltage which is linearly proportional to the measured atmospheric pressure. The scaling circuit consisting of two op amps 331a and 331b with associated resistors 323h to 323n scales the transducer's output voltage, in a manner well understood by those skilled in the art, such that the resulting voltage at the terminal OUT directly corresponds to the measured atmospheric pressure, either in milibars or in mm Hg, depending on the selection of certain resistors. The invention resides in utilizing the output voltage at the terminal OUT for causing the display to illuminate in a color related to the measured atmospheric pressure. The terminal OUT may be connected as shown in FIGS. 23, 25, 29, and 30.

In FIG. 53 is shown a block diagram of a circuit for measuring cardiac activity of the user which includes three electrodes 338a, 338b, and 338c adapted to be positioned on the body of the user, amplifier 349 adapted to amplify the output of the electrodes which indicates the functioning of a heart beating within the user's body, shaping circuit 341 for converting output signals of the amplifier to square wave pulses, oscillator 343 for providing a periodic sequence of clock pulses of a predetermined rate, counter 345 for counting the pulses, counter control 347, responsive to output signals of the shaping circuit, for starting and stopping the counter such that its final count is proportional to the heart rate of the user, as will be more fully explained later, decoder 353 for converting the output count of the counter to color control signals, and color control latch 351 for intermediately storing the color control signals.

In FIG. 54 is shown a block diagram of a like circuit which differs from the one shown in FIG. 53 in that a color converter 55 and counter latch 352 are used in lieu of the decoder and color control latch. When the counter completes its counting cycle, its output data will be intermediately stored in the counter latch 352 and thus applied to the input of the color converter 55.

Regular throbbing in the arteries caused by contractions of the heart can be monitored on the wrist or on many other suitable locations on the body where major arteries approach the skin. The rate and strength of the blood pulse depend on the age, sex, physiological condition, and a number of other factors. In adult person, the heart rate may range from 50 to 80 beats per minute.

Systematic monitoring of the heart rate by the device of the present invention allows to detect changes in physiological patterns in the body of the user. It also allows to explore possibilities of influencing abnormal physiological patterns by a technique of feedback.

FIG. 55 shows well known electrocardiogram wave with its salient points indicated. The R wave 398b is the most distinct signal and, therefore, well known technique of counting the number of stable clock pulses between the adjacent R waves was employed to measure the heart rate.

FIG. 56 is a detail of the counter and 2-primary color converter combination shown generally in FIG. 54. An 8-bit binary counter 346 may be from time to time reset to its zero count by applying a short negative COUNTER CLEAR pulse to its Clear input CLR. When not in its reset condition, the counter is incremented by clock pulses of suitable frequency provided by the oscillator 343. When a positive going edge COUNTER SAVE is applied to the counter's Register Clock input REG CL, the instant count data are transferred to the internal register and appear at the outputs Q0 to Q7, which are directly connected to respective address inputs A0 to A7 of the memory 77 which contains data symbolizing the portions of red color for all possible counter output data. The memory data residing at the address selected by the instant counter's output data will appear at the memory outputs D0 to D7, which may be connected as shown in the detail in FIG. 33, to cause the display to illuminate in a specific color.

In FIG. 57 is shown a similar schematic diagram of the counter and 3-primary color converter combination. The outputs Q0 to Q7 of the counter 346 are respectively connected to the interconnected address inputs A0 to A7 of the RED MEMORY 77a, GREEN MEMORY 77b, and BLUE MEMORY 77c. When the instant output data of the counter are applied to the address inputs of the memories, the memory data residing at such address in the memory 77a, symbolizing the portion of red primary color, will appear at its memory outputs D0 to D7, memory datal residing at the same address in the memory 77b, symbolizing the portion of green primary color, will appear at its memory outputs D0 to D7, and memory data residing at the same address in the memory 77c, symbolizing the portion of blue primary color, will appear at its memory outputs D0 to D7. The memory outputs of the three memories may be connected as shown in the detail in FIG. 35, to cause the display to illuminate in a specific color.

FIG. 58 is a detail of the counter control circuit, shown generally in FIGS. 53 and 54, for controlling the counter 345. The description of the circuit should be considered together with its associated timing diagram shown in FIG. 60. The R wave 398b, measured by the electrodes, is amplified by the amplifier 349 and converted to square R wave by the shaping circuit 341. The leading positive going edge of the SQUARE R WAVE 399c is used as COUNTER SAVE pulse 399h, to transfer the instant data in the counter 345, which represent the heart rate for previous R-R interval, to its internal register for storing it until new data are available. The SQUARE R WAVE 399c is applied to the D input of SYNCHRO flip-flop 356, to be synchronized with clock pulses 399a, and appears at its Q output as SYNC R WAVE 399d, to trigger, by its leading edge, RESET one shot multivibrator 358, which will produce at its output Q a negative going COUNTER CLEAR pulse 399i of short duration, determined by the values of resistor 323a and capacitor 321c, for resetting the counter 345 immediately after its contents were stored in its internal register.

FIG. 59 is a detail of the amplifier and shaping circuit combination shown generally in FIGS. 53 and 54. Measuring electrodes 339a, 339b, and 339c are adapted to be attached to specific points of the body of the timepiece user for measuring electrical signals generated by functioning of a heart within the user's body. The electrode 339c is provided for suppression of common mode noise that may appear at the differential inputs from external electromagnetic fields. An amplifier 332d amplifies the measured signals from the range of milivolts to the range of volts, and provides at its output inverted R wave 398f, which is applied, via capacitor 321i, to the input of an inverter 334a. A potentiometer 325d provides adjustable bias voltage with respect to the ground potential, to allow a treshold 397 to be adjusted such that the inverted R wave 398f is converted into a square R wave 399c at the inverter's output.

By referring now, more particularly, to the timing diagram shown in FIG. 60, the heart rate measuring method may be briefly summarized. Measured R wave is amplified and inverted, to obtain a wave 398f, and squared, to obtain a SQUARE R WAVE 399c. The interval between the adjacent R waves is measured by counting the number of stable clock pulses 399a. The leading edge of the SQUARE R WAVE 399c is used to generate the COUNTER SAVE pulse 399h, which is applied to the counter 345 to effect the transfer of its instant count, representing the distance between the previous R wave and the instant one, to the counter's internal register. The counter 345 is reset immediately after that, by the COUNTER CLEAR pulse 399i, which was generated in response to the leading edge of the SYNC R WAVE 399d, and starts accumulating clock pulses 399a again until the next R wave is detected, at which moment the total number of accumulated clock pulses is transferred to the counter's internal register, and the process is repeated. The heart rate may be calculated by dividing the number of clock pulses per minute by the number of clock pulses measured between the adjacent R waves.

FIG. 61 is a schematic diagram of the oscillator shown generally in FIGS. 53 and 54. A CLOCK TIMER 357 is used in its astable configuration to generate at its output OUT square wave pulses of a frequency 250 Hz, determined by the values of resistors 323u, 323v and capacitor 321m. The square wave pulses are applied to the Clock Pulse input CP of a CLOCK FLIP-FLOP 356b which will divide the frequency by two, to provide at its Q output clock pulses of 125 Hz frequency and of equal duty cycle which are used in the circuits for heart rate measurements. Alternately, it would be obvious that the clock pulses may be derived from the master clock which is used to generate the second, minute, and hour signals in the clock chip.

FIG. 62 is a detail of the counter and decoder combination, shown generally in FIG. 53, for generating color control signals to cause the display to illuminate in one of three possible colors in accordance with the accumulated count in the counter's internal register. The description of the circuit should be considered together with its associated chart shown in FIG. 63. The 8-bit binary counter 346 contains internal register with outputs Q0 to Q7 available. Two most significant outputs Q6 and Q7 are connected to respective inputs A and B of the 3-to-8 line decoder 354; the decoder's most significant input C is grounded. In response to the conditions of the counter outputs Q6 and Q7, the decoder 354 will develop output signals Y0, Y1, and Y2. It is readily apparent that the output Y0 will rise to a high logic level when both counter outputs Q6 and Q7 are at a low logic level (which is typical for counts less than 63), to generate active color control signal R (red). When the counter output Q6 rises to a high logic level, while the output Q7 is low (which is typical for counts between 64 and 127), the decoder output Y1 will rise to a high logic level to generate active color control signal Y (yellow). When the counter output Q7 rises to a high logic level and Q6 drops to a low logic level (which is typical for counts between 128 and 191), the decoder output Y2 will rise to a high logic level to generate active color control signal G (green). The values of the heart rate in the chart were calculated by dividing the number of clock pulses per minute (7500) by particular counts in the left column. The decoder outputs Y0 to Y2 may be connected as shown in FIG. 19.

FIG. 64 is a like detail of the counter and decoder combination for generating color control signals to cause the display to illuminate in one of seven possible colors, depending on the accumulated count in the counter's internal register. The associated chart is shown in FIG. 65. This circuit differs from the one shown in FIG. 62 in that three counter outputs Q5, Q6, and Q7 are connected to respective inputs A, B, and C of the decoder 354, to develop color control signals R, W, G, BG, P, and B at respective decoder outputs Y1 to Y7. When the counter output Q5 is at a high logic level and Q6, Q7 are at a low logic level (which is typical for counts between 32 and 63), the decoder output Y1 will rise to a high logic level to generate active color control signal R (red). The remaining color control signals are generated similarly. The decoder outputs Y1 to Y7 may be connected as shown in FIG. 20.

Although not shown in the drawings, it will be appreciated that the timepiece of this invention may have any conceivable form or shape, such as a wristwatch, pocket watch, clock, alarm clock, and the like. Alternately, the timepiece may have characteristics of an article for wearing on a body of wearer or for securing to wearer's clothing, such as a bracelet, ring, ear-ring, necklace, tie tack, button, cuff link, brooch, hair ornament, and the like, or it may be built into, or associated with, an object such as a pen, pencil, ruler, lighter, briefcase, purse, and the like.

In brief summary, the invention describes a method and a device for simultaneously displaying values of time and values of a physiological quantity, on a single variable color digital display device, by causing the values of time to be indicated in a digital format, and by controlling the color of the display in accordance with the values of the physiological quantity. In the most preferred embodiment, a timepiece with a variable color digital display was disclosed which can indicate time in digital format and in a color variable in accordance with the heart rate of its user.

All matter herein described and illustrated in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. It would be obvious that numerous modifications can be made in the construction of the preferred embodiments shown herein, without departing from the spirit of the invention as defined in the appended claims. It is contemplated that the principles of the invention may be also applied to numerous diverse types of display devices, such are liquid crystal, plasma devices, and the like.

The examples of commercially available components should be considered as merely illustrative. It will be appreciated that other components may be readily and effectively used. The integrated circuits used in the description of the invention are manufactured by several well known companies, such are National Semiconductor Incorporated, Motorola Semiconductor Products Inc., Fairchild Camera and Instrument Corporation, Texas Instruments Incorporated, Intel Corporation, Analog Devices, Inc., Teledyne Semiconductor, Intersil, Inc., Precision Monolithics Incorporated, etc.