Transpose Memory for DCT/IDCT Circuit

The following patents and patent applications are assigned to the assignee hereof:

1. U.S. Pat. No. 5,226,002, entitled "Matrix Multiplier Circuit" filed Jun. 28, 1991 for Hug-Di Wu, Rong-Yean Lee and Maing-Ku Yang;

2. U.S. Pat. No. 5,204,830, entitled "Fast Pipelined Matrix Multiplier" filed Feb. 13, 1992 for Jinn-Shyan Wang and Jinn-Nan Kao;

3. U.S. patent application Ser. No. 07/948,237, entitled "Algorithm and Circuits for Matrix Multiplication" filed Sep. 21, 1992 for Jinn-Nan Kao; and

4. U.S. patent application Ser. No. 08/121,598, entitled "Fast Pipelined 2-D Discrete Cosine Transform Architecture" filed Sep. 15, 1993 for Jinn-Nan Kao.

The above-listed patents and patent applications contain subject matter related to the present application and are incorporated herein by reference.

The present invention relates to circuits which may be used in compressing video signals. In particular, the present invention relates to a novel transpose memory which may be inserted in between two one dimension transform circuits, such as discrete cosine transform (DCT) or inverse discrete cosine transform circuits (IDCT) .

The Discrete Cosine Transform (DCT) is a frequently used operation in several applications. For example, it is advantageous in the area of video image data compression to apply a two dimensional (2-D) DCT to inputted video data.

The 2-D DCT is defined as: ##EQU1## where x.sub.ij are input elements in an N.times.N matrix, with i,j=0,1,2, . . ., N-1 and where z.sub.mn are output elements in an N.times.N matrix with m,n=0,1,2, . . ., N-1 and where: ##EQU2## The Inverse Discrete Cosine Transform (IDCT) is defined as: ##EQU3## The matrix expression for equation (1) is

where X is the input data matrix, C is the cosine transform matrix and C.sup.t is the transpose of the matrix C. If the input matrix X is an N.times.N matrix, then equation (3) may be expressed as: ##EQU4## The computation of the IDCT is similar to that of the DCT except that the matrix C.sup.t is substituted for the matrix C and vice versa. Therefore, the discussion may continue with only the DCT without loss of generality. Equation (3) may be divided into one dimensional transforms as follows:

where Y is an intermediate product matrix or intermediate matrix and C.sup.t is the transpose of the cosine coefficient matrix C. Likewise from equation (6) the following is also true:

where Y.sup.t is the transpose of the intermediate matrix Y. (Likewise, for an IDCT, we have:

There are several conventional techniques and circuits for performing a DCT of an inputted data matrix. N. Ahmed, T. Natarajan & K. Rao, "Discrete Cosine Transform," IEEE Trans. on Computers, vol. C-23, Jan., 1974, 90-93 teaches a general DCT technique. N. Cho & S. Lee, "Fast Algorithm and Implementation of 2-D Discrete Cosine Transform," IEEE Trans. on Cir. & Sys., vol. 38, no. 3, Mar. 1991, p. 297-305 discloses a circuit that computes an 2-D N.times.N DCT using N 1-D DCT circuits or with multiplexers and N/2 1-D DCT circuits. M. Sun, T. Chen & A. Gottlieb, "VLSI Implementation of a 16.times.16 Discrete Cosine Transform," IEEE Trans. on Cir. & Sys., vol. 36, no. 4, Apr., 1989, p.610-17 teaches a 2-D DCT circuit with DCT stages having a memory for storing partial results in the matrix calculations of 1-D DCT's. H. Hou, "A Fast Recursive Algorithm For Computing the Discrete Cosine Transform," IEEE Trans. on Acoustics, Speech and Signal Processing, vol. ASSP-35, no. 10, Oct., 1987, p.1455-61 teaches a decimation technique which exploits symmetry properties of the DCT coefficient matrix in order to reduce the number of multiplications of the transformation. More specifically, equation (5) can be rewritten as follows: ##EQU5## where Y.sub.e is a matrix containing the even rows of the matrix Y, Y.sub.o is a matrix containing the odd rows of the matrix Y, X.sub.f is a matrix containing the front rows (in the upper half) of the matrix X, X.sub.r is a matrix containing the recent rows, in reverse order, (in the lower half) of the matrix X and C.sub.1 and C.sub.2 are N/2.times.N/2 DCT coefficient matrices. For example, in an 8.times.8 DCT, equation 7 may be rewritten as: ##EQU6## Y.sub.0, Y.sub.1, . . ., Y.sub.7 are rows of the intermediate matrix Y and x.sub.0, x.sub.1, . . ., x.sub.7 are rows of the input data matrix X. Likewise, the IDCT may be written as follows: where C.sub.1.sup.t is the transpose of C.sub.1 and C.sub.2.sup.t is the transpose of C.sub.2. For example, in an 8.times.8 IDCT, equation 8 may be rewritten as: ##EQU7##

Equations 7, (7a) , (8b) and 8, (8a), (8b) are also applicable in determining Z=CY.sup.t as in Equation 6(a) or its analog in IDCT Y=ZC.

Equations (7a) , (7b) , (8a) and 8(b) provide an advantage in that the number of multiplications necessary to determine each 1-D DCT is reduced by 50%.

FIG. 1 shows one 2-D DCT/IDCT architecture. See U.S. Pat. No. 4,791,598. As shown, the circuit has a first 1-D DCT (or IDCT) circuit 3 which receives an input data matrix X (or 2-D transformed matrix Z) on lines n.sub.1. The 1-D DCT circuit 3 transforms the inputted data matrix according to equation (6a) or (7a)-(7b) (or (6b) or (8a)-(8b)) and outputs an intermediate product matrix Y on lines n.sub.2 to a transpose memory 5. The transpose memory 5 transposes the intermediate product matrix Y and outputs the transpose of the intermediate product matrix Y.sup.5 on lines n.sub.3 to a second 1-D DCT circuit 7. The second 1-D DCT transform circuit 7 outputs a 2-D transformed output matrix Z according to equation 6(a) or (7a)-(7b) (or (6b) or (8a)-(8b)) on lines n.sub.4.

In the case of a DCT circuit, the 1-D DCT circuit outputs a row-column ordered sequence i.e., y.sub.0, y.sub.1, y.sub.2, . . ., y.sub.63. (Herein, as a matter of convenience, an 8.times.8 matrix is assumed wherein matrix elements y.sub.ij, for i,j=0,1,2, . . .,7 will be referred to using single number subscripts as follows: ) ##EQU8## The transpose memory 5 writes out the data in transposed order, in this case column-row order, i.e., y.sub.0, y.sub.8, y.sub.8, y.sub.16, y.sub.32, . . ., y.sub.1, y.sub.9, y.sub.17, y.sub.25, y.sub.33, . . . , y.sub.63. However, an inspection of equation (7a)-(7b), reveals that a 1-D decimation technique DCT circuit 7 requires two elements of the intermediate matrix Y at a time in the order (y.sub.0, y.sub.56), (y.sub.8, y.sub.48), (y.sub.16, y.sub.40), . . . , (y.sub.1, y.sub.57), (y.sub.9, y.sub.49), . . . , (y.sub.31, y.sub.39) (referred to herein as "shuffled column-row order"). Furthermore, it is often desirable to separately apply equations (7a) and (7b) (or (8a) and (8b), in the case of an IDCT) to each data pair successively, rather than simultaneously. This allows using a smaller matrix multiplier in the circuit 7 without significantly affecting the throughput. In such a case, each column of element pairs of the outputted sequence is outputted twice, i.e., the following sequence is outputted: (y.sub.0, y.sub.56), (y.sub.8, y.sub.48), . . . , (y.sub.24, y.sub.32), (y.sub.0, y.sub.56), (y.sub.8, y.sub.48), . . . , (y.sub.24, y.sub.32), (y.sub.1, y.sub.57), (y.sub.9, y.sub.49) , . . . , (y.sub.25, y.sub.33), (y.sub.1, y.sub.57) , (y.sub.9, y.sub.49) , . . . , (y.sub.25, y.sub.33) , . . . , (y.sub.31, y.sub.39).

The sequence outputted from the transpose memory is received at a pre-processing circuit 7a containing an ALU 7b and shift-in parallel-out registers 7c. The shift-in parallel-out registers 7c receive each column outputted from the transpose memory 5 and output two elements, in parallel, in shuffled column-row order.

In the case of an IDCT, the 1-D IDCT circuit 3 outputs the elements of the matrix Y in the order y.sub.0, y.sub.7, y.sub.1, y.sub.6, y.sub.2, y.sub.5, . . . , y.sub.8, y.sub.15, y.sub.9, y.sub.14, . . . , y.sub.59, y.sub.60 (referred to herein as "shuffled row-column order"). The transpose memory thus outputs the elements in transposed order, i.e., shuffled column-row order y.sub.0, y.sub.56, y.sub.8, y.sub.48, y.sub.16, y.sub.40, . . . , y.sub.1, y.sub.57, y.sub.9, y.sub.49, . . . , y.sub.31, y.sub.39. However, an inspection of equations (8a)-(8b) reveals that a 1-D IDCT decimation technique circuit requires two elements per cycle in column-row order, i.e., (y.sub.0, y.sub.8), (y.sub.16, y.sub.24), . . . , (y.sub.1, y.sub.9), (y.sub.17, y.sub.25) , . . . , (y.sub.55 , y.sub.63) (or, advantageously, repeated row-column order: (y.sub.0, y.sub.8), (y.sub.16, y.sub.24) , . . . , (y.sub.48, y.sub.56), (y.sub.0, y.sub.8), (y.sub.16, y.sub.24) , . . . , (y.sub.48, y.sub.56), (y.sub.1, y.sub.9), (y.sub.17, y.sub.25) , . . . , (y.sub.49, y.sub.57), (y.sub.1, y.sub.9), (y.sub.17, y.sub.25) , . . . , (y.sub.49, y.sub.57) , . . . , (y.sub.55, y.sub.63)). Again, the shift-in parallel-out registers 7c of the pre-processor circuit 7a receive each column in shuffled column-row order outputted from the transpose memory 5 and outputs two elements per cycle in column-row order.

It is desirable to implement the architecture shown in FIG. 1 in a fashion which is fully pipelined, i.e., such the flow of intermediate matrices Y from the first 1-D DCT 3, to the transpose memory 5, to the second 1-D DCT 7 is continuous without stoppages. However, the transpose memory 5 is a potential bottleneck. This because of the actual transpose operation performed by the transpose memory 5. For example, data may be written in the transpose memory 5 in row-column order. The data is then read out in the column-row or shuffled column-row order. The time to write the data in the transpose memory 5 is T and the time to read out the data from the transpose memory 5 is T. Thus, a conventional transpose memory utilizes a time 2T to process each matrix Y.

In order to reduce this processing time, several conventional transpose memories have been proposed. In a first conventional architecture, two transpose memories are provided which are used to alternately process each inputted intermediate matrix Y. That is, during a first phase, a first transpose memory writes a first intermediate matrix Y1 therein according to, e.g., row-column ordering. During a second phase, the second transpose memory writes a second intermediate matrix Y2 therein according to row-column ordering. While writing the second intermediate matrix Y2, the first transpose memory reads-out the intermediate matrix Y1 according to column-row ordering. Likewise, during a third phase, the first transpose memory writes a third intermediate matrix Y3 therein in row-column order and the second transpose memory reads-out the second intermediate matrix Y2 in column-row order. This transpose memory is disadvantageous because two memories are required.

FIG. 2 shows a different conventional approach which is disclosed in U.S. Pat. No. 4,791,598. As shown, the transpose memory 5 has a column of shift registers 13 and a column of parallel registers 15 connected at its output. The matrix Y is shifted into the shift register column 13 in column-row order so that each column register 13-1, 13-2, . . ., 13-N receives a corresponding row of matrix elements of Y. When the entire matrix is loaded into the shift register column 13, the individual registers 13-1, 13-2, . . ., 13-N transfer their contents in parallel to corresponding parallel registers 15-1, 15-2, . . ., 15-N connected thereto. Form there, the data in the parallel registers may be fed to a combined core processor-ALU 17. In the meantime, the shift register column 13 is immediately available to receive the next intermediate product matrix Y. This architecture is disadvantageous because many space wasting registers are required.

U.S. Pat. No. 5,053,985 teaches another architecture which is shown in FIG. 3. An input data matrix X is processed by a 1-D DCT circuit 20 which can process data at twice the rate at which the matrix X is inputted. As shown, the 1-D DCT circuit 20 includes a first circuit containing pre-registers and an ALU 30 for preprocessing the data, multiplier and accumulators 35 for performing row-column matrix multiplication and a second circuit containing post-registers and an ALU 40 for post-processing the data. The intermediate matrix Y produced by the 1-D DCT circuit 20 is stored in a RAM 60, e.g., in row-column order. The data is then read out of the RAM 60 in column-row order and processed again by the 1-D DCT circuit 20 at twice the rate at which the matrix X is inputted. However, while a 100 MHZ DCT processor is known from S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Terane and M. Yoshimoto, "A 100-MHz 2-D Discrete Cosine Transform Core Processor" I.E.E.E J. OF SOLID STATE CIRS., VOl. 27, no. 4, Apr. 1992, p. 429-99, the input data rate is limited to 1/2 of the processor speed.

U.S. Pat. Nos. 5,042,007 and 5,177,704 show transpose memory architectures which use shift registers connected to form FIFO (first-in first-out) memories. In both of these patents, the transpose memories themselves are formed using (N.sup.2 +1) n-bit shift registers and (2N.sup.2 -2) 2-to-1 multiplexers. The multiplexers and shift registers are connected in a configuration for transposing an inputted intermediate matrix. Likewise, U.S. Pat. No. 4,903,231 teaches another transpose memory formed by interconnecting N.sup.2 shift registers and approximately N.sup.2 multiplexers. U.S. Pat. No. 4,903,231 also teaches that elements may be shifted in and out in row-column or column-row order. These architectures are disadvantageous because many space consuming registers and multiplexers are required.

U.S. Pat. No. 4,769,790 teaches a transpose circuit in which the columns (rows) of an inputted matrix are inputted in parallel to a delay circuit which delays each column a different number of cycles. The delayed columns are sequentially inputted to a distribution circuit which rotates the delayed elements received each cycle a number of columns depending on the cycle in which the elements are received. The rotated columns are outputted to a second delay circuit which delays each of the rotated columns. Like the other architectures mentioned above, this architecture requires many space consuming shift registers in each delay circuit and thus occupies a great deal of space.

U.S. Pat. No. 4,918,527 teaches a transpose memory in which a memory is partitioned into two separately accessible halves or planes. Data is written in one half plane while data is read out of the other half plane. Furthermore, the data is stored in the two half-planes such that data of odd rows are permutated two-by-two, i.e., in each odd row, the intermediate matrix is stored such that the elements of each pair of columns are swapped. The disadvantage of this architecture is that a pre-processing unit, having many registers, is required to convert the outputted sequence of individual matrix elements into a sequence of matrix element pairs. Furthermore, the architecture requires extensive space consuming pre and post-decoders including at least nine logic gates for each stored matrix element.

The primary disadvantage of the prior art architectures is that they occupy a great deal of space. This is an important consideration if the 2-D DCT or IDCT circuit is to be formed on a single integrated circuit (IC) chip. Furthermore, none of the above. architectures provides for fully flexible write and read orderings. That is, none of the above architectures provide for writing a matrix into, and subsequently reading the matrix from, the transpose memory according to any combination of read and write orderings (i.e., row-column, column-row, shuffled row-column, shuffled column-row). In the very least, the pre-and post-processing registers and ALUs, transpose memory and 1-D transform circuits must be completely emptied before the order of in which the input matrices are received or in which the output matrices are outputted can be changed.

It is therefore an object of the present invention to overcome the disadvantages of the prior art.

These and other objects are achieved by the present invention. According to one embodiment, a transpose memory is provided for receiving elements of a matrix according to a first order. The transpose memory is capable of outputting the received matrix elements to a first or second type of transform circuit, e.g., a DCT or IDCT transform circuit, according to a second order. The transpose memory has four dual port memories which illustratively are dual port RAMs. Each dual port memory has a number of storage cells including one storage cell for storing each element of one fourth of the received matrix. The transpose memory also has a first counter for writing each received matrix element in a particular storage cell of a particular memory. Furthermore, the transpose memory has a second counter for reading out pairs of elements according to the second order.

The particular dual port memory in which the first counter writes each matrix element is selected to facilitate simultaneous reading-out of matrix element pairs without the need of space consuming registers or many logic gates. If the received matrix is to be outputted to the first type of transform circuit, each of the dual port memories is assigned to one quadrant or one corner of the received matrix. In such a case, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. That is, matrix elements in front rows and front columns (upper left corner) of the matrix are written in a first memory. Elements in front rows and recent columns (upper right corner) of the matrix are written in a second memory. Elements in recent rows and front columns (lower left corner) of the matrix are written in a third memory. Elements in recent rows and recent columns (lower right corner) of the matrix are written in the fourth memory. If the received matrix is to be outputted to the second type of transform circuit, each of the dual port memories is assigned to alternating rows and columns of the received matrix. In such a case, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element. That is, matrix elements in odd rows and odd columns of the matrix are written in a first memory. Elements in odd rows and even columns of the matrix are written in a second memory. Elements in even rows and odd columns of the matrix are written in a third memory. Elements in even rows and even columns of the matrix are written in the fourth memory.

Illustratively, the writing of elements in a memory corresponding to the quadrant of the matrix element allows simultaneous reading-out of element pairs in a shuffled order, i.e., shuffled row-column or shuffled column-row. This is because, each element of each pair to be read-out is stored in a different memory. For instance, the elements y.sub.0, y.sub.8, y.sub.16, and y.sub.24 of the upper left quadrant of a matrix are written in a first dual port memory and the elements y.sub.32, y.sub.40, y.sub.48, and y.sub.56 of a lower left quadrant are written in a second dual port memory. Thus, the second counter can easily read out each element of each pair (y.sub.0, y.sub.56), (y.sub.8, y.sub.48), (y.sub.16, y.sub.40) and (y.sub.24, y.sub.32) of the shuffled column-row ordered sequence because each element of each pair is stored in a different dual port memory. Likewise, the writing of each matrix element in a particular memory assigned to the evenness or oddness of the row and column of the matrix element allows simultaneous reading-out of element pairs in non-shuffled order, i.e., non-shuffled row-column or column-row order. For instance, the elements y.sub.0, y.sub.16, y.sub.32, and y.sub.48 and y.sub.48 in odd rows of a matrix are written in a first dual port memory and the elements y.sub.8, y.sub.24, y.sub.40, and y.sub.56 in even rows are written in a second dual port memory. Thus, the second counter can easily read out each element of each pair (y.sub.0, y.sub.8), (y.sub.16, y.sub.24), (y.sub.32, y.sub.40) and (y.sub.48, y.sub.56) of the shuffled column-row ordered sequence because each element of each pair is stored in a different dual port memory.

Illustratively, the transpose memory of the present invention is inserted in between two one-dimensional transform circuits. The transpose memory can be inserted between two transform circuits of the same type, e.g., between two DCT or two IDCT transform circuits. In such a case, the first and second counters can be synchronized in relation to the inputted matrix elements to provide pipeline transpose operation. That is, the first counter can simultaneously write received matrix elements in the dual port memories while the second counter simultaneously reads-out previously written matrix elements. Illustratively, the second counter vacates, i.e., reads-out elements of a previously stored matrix from, storage cells of the memories prior to the first counter writing elements of a subsequently received matrix therein. In an alternative embodiment, the transpose memory can receive elements from one type of transform circuit and output the elements to, and in an order suitable for, a different type of transform circuit.

In short, a transpose memory is provided which can be implemented with four low area occupying memories, two counters and a limited amount of glue logic circuits. The transpose memory occupies little area on an IC chip yet is capable of outputting elements according to one of a number of possible orders regardless of the input order.

FIG. 1 shows a first conventional 2-D DCT/IDCT architecture.

FIG. 2 shows a first conventional transpose memory architecture.

FIG. 3 shows a second conventional transpose memory architecture.

FIG. 4 shows a 2-D DCT/IDCT architecture according to the present invention.

FIG. 5 shows a transpose memory according to the present invention in greater detail.

FIGS. 6(a), (b), (c), (d) show write counter orders according to one embodiment of the present invention.

FIG. 7 illustrates the state of the transpose memory of FIG. 5 after writing part of a first matrix therein using the write counter order of FIG. 6(a).

FIGS. 8(a), (b), (c), (d) show read counter orders according to one embodiment of the present invention.

FIG. 9 illustrates the state of the transpose memory of FIG. 5 after writing part of a second matrix therein using the write counter order of FIG. 6(d) and reading-out the first matrix using the read counter order of FIG. 8(a).

FIG. 10 illustrates the state of the transpose memory of FIG. 5 after writing part of a third matrix therein using the write counter order of FIG. 6(a) and reading-out the second matrix using the read counter order of FIG. 8(d).

FIG. 11 illustrates the state of the transpose memory of FIG. 5 after writing part of a first matrix therein using the write counter order of FIG. 6(b).

FIG. 12 illustrates the state of the transpose memory of FIG. 5 after writing part of a second matrix therein using the write counter order of FIG. 6(c) and reading-out the first matrix using the read counter order of FIG. 8(b).

FIG. 13 illustrates the state of the transpose memory of FIG. 5 after writing part of a third matrix therein using the write counter order of FIG. 6(b) and reading-out the second matrix using the read counter order of FIG. 8(c).

FIG. 4 shows a 2-D DCT/IDCT architecture 100 according to the present invention. As shown, the 2-D DCT/IDCT architecture 100 has a 1-D DCT or IDCT circuit 110 as before which outputs intermediate matrices Y in row-column y.sub.0, y.sub.1, y.sub.2, . . ., y.sub.63 (in the case of a DCT circuit 110) or shuffled row-column order y.sub.0, y.sub.7, y.sub.1, y.sub.6, y.sub.2, y.sub.6, . . ., y.sub.60 (in the case of an IDCT circuit 110). The outputted matrices Y are received by a transpose memory 120 according to the present invention via an n-bit line 111. The transpose memory 120 transposes and shuffles the inputted matrices. The transpose memory 120 outputs the matrices y.sup.t in shuffled column row order to the DCT circuit 140 (or column row order in the case of an IDCT circuit 140), two elements at a time, via two n-bit lines 121 and 122. The matrices Y.sup.t are received at a pre-processor 130 which is shown having only an ALU 135. Since the transpose memory 120 according to the present invention is capable of outputting the matrix Y.sup.t in the correct order (i.e., shuffled column-row or non-shuffled column-row order, two elements at a time), the shift and parallel registers 13, 15 (FIG. 2) which are needed in prior art 2-D DCT/IDCT circuits may be omitted. The output of the pre-processor circuit 135 is then received by a 1-D DCT/IDCT circuit 140 which outputs the two-dimensionally transformed matrix, i.e., the transformed matrix Z or original data sequence X.

FIG. 5 shows the transpose memory 120 according to the present invention in greater detail. As shown, the transpose memory 120, which is capable of transposing an N.times.N matrix, has four sub-memories 141, 142, 143 and 144 which illustratively are smaller transpose dual port random access memories or "STRAMs". Each STRAM 141-144 has a two-dimensional memory array with a total of N/2.times.N/2 storage cells for storing one fourth of the elements of each inputted intermediate matrix Y. Each STRAM 141-144 has a corresponding data-in port 141-1, 142-1, 143-1 or 144-1 for receiving the elements of each intermediate matrix Y outputted from the 1-D DCT/IDCT circuit 110 (FIG. 4) via the n-bit line 111. Each STRAM 141-144 has a write address port 141-2, 142-2, 143-2 or 144-2, respectively connected to a write address counter 151. Furthermore, each STRAM has a chip enable terminal 141-3, 142-3, 143-3 or 144-3, respectively, connected to the write address counter 151 via a corresponding line 151-1, 151-2, 151-3 or 151-4. When the write address counter 151 generates a chip enable signal on the appropriate line 151-1, 151-2, 151-3 or 151-4, the corresponding STRAM 141, 142 143 or 144, respectively, is enabled. When enabled, the STRAM 141, 142, 143 or 144 writes the intermediate matrix element appearing on the data-in line 111 in the storage cell therein which storage cell is indicated by the address outputted by the write address counter 151.

In addition to the write address counter 151, the transpose memory 120 also has a read address counter 152. The read address counter 152 is connected to a read address port 141-4, 142-4, 143-4 and 144-4 of each STRAM 141-144, respectively. Furthermore, the read address counter 152 outputs two selector control signals S1 and S2, the purpose of which is discussed below. In response to receiving an address from the read address counter 152, each STRAM 141-144 reads-out, in parallel, the contents of the storage cell therein indicated by the read address counter 152. The STRAMs 141-144 output the read-out elements via the read ports 141-5, 142-5, 143-5 and 144-5.

A first multiplexer 161 is provided which receives the selector control signal S1 (outputted from the read address counter 152) as a selector control input. As shown, the first multiplexer 161 receives the elements outputted from the read port 142-5 of the second STRAM 142 at a first data input terminal and the elements outputted from the read port 143-5 of the third STRAM 143 at a second data input terminal.

A second multiplexer 162 and a third multiplexer 163 are provided which both receive the selector control signal $2 (outputted from the read address counter 152) as a selector control input. The output of the first multiplexer 161 is received as a first data input of the third multiplexer 163 and a second data input of the second multiplexer 162. The elements outputted from the read port 141-5 of the first STRAM 141 are received at a first data input terminal of the second multiplexer 162. The elements outputted from the read port 144-5 of the fourth STRAM 144 are received at a second data input terminal of the third multiplexer 163.

As mentioned above, each STRAM 141-144 outputs a matrix element in parallel from its read address port 141-5 to 144-5. By appropriate choice of select control signals S1 and S2, the read address counter 152 can cause the multiplexers 162 and 163 to simultaneously output the elements read-out of two different STRAMs 141, 142, 143 and 144.

The operation of the transpose memory 120 is now discussed. For purposes of convenience, it is assumed that each intermediate matrix Y is an 8.times.8 matrix with elements labeled in row-column order y.sub.0, y.sub.1, . . ., y.sub.8, y.sub.9, . . . , y.sub.63. The write address counter 151 is capable of counting the storage cells of the STRAMs 141-144 according to one of a number of write counter orders. (Herein, the term "counter order" is used to refer to the order in which the read counter 152 or write counter 151 accesses the storage cells of the STRAMs 141-144. These "counter orders" should not be confused with "sequence orders" such as row-column, shuffled column-row, etc., which refer to the sequence order in which matrix elements are inputted to, or outputted from, the transpose memory 120.) For example, FIGS. 6(a), 6(b), 6(c) and 6(d) show four illustrative write counter orders of the write address counter 151. As shown in FIGS. 6(a)-(d), each STRAM 141-144 has a number of storage cells 171-0 to 171-5, 172-0 to 172-15, 173-0 to 173-15, and 174-0 to 174-15 including one storage cell for storing sixteen matrix elements (one fourth of an 8.times.8 intermediate matrix). The storage cells of each STRAM 141-144 are organized into a two-dimensional array. A label from 1 to 64 indicates the order in which the write counter 151 accesses the cells. For example, according to the write counter order of FIG. 6(a), on cycle 1, the write address counter 151 accesses the storage cell 171-0 of the STRAM 141. On cycle 2, the write address counter 151 accesses the storage cell 171-1 of the STRAM 141, etc.

Illustratively, the write counter order (FIGS. 6(a)-6(d)) in which the write address counter 151 counts is selected depending on the sequence order in which the elements of each inputted intermediate matrix Y are received and the sequence order in which they are to be outputted. These input and output sequence orderings are summarized in Table 1 below.

In Table 1, the outputted sequences are shown in parenthetical to indicate that a pair of elements is to be outputted each cycle. The write counter order may be predetermined or adjustable. For instance, the write counter order may be selected by inputting a control signal to the write address counter 151 via a control input (not shown) for selecting the appropriate write counter order.

An example is now discussed for the case of a 2-D DCT. As shown in Table 1, the 1-D DCT circuit 110 (FIG. 4) outputs each intermediate matrix Y as a row-column ordered sequence. The elements of the matrix Y in row-column order are inputted to the transpose memory 120 one element per cycle on data-in line 111. The transpose memory 120 outputs the elements of each inputted intermediate matrix Y to the pre-processor 135 in shuffled column-row order wherein each shuffled column is repeated (see Table 1). Suppose the 1-D DCT circuit 110 sequentially outputs the elements of a sequence of matrices Y1, Y2, Y3, Y4, . . .. The write address counter 151 illustratively counts according to the write counter order shown in FIG. 6(a). For example, the first received element y.sup.1.sub.0 is written in the storage cell 171-0 of the first STRAM 141, the second element y.sup.1.sub.1 is written in the storage cell 171-1, etc. The memory accesses and elements of the matrix Y1 written on each of the first 57 cycles are summarized below in Table 2.

The state of the STRAMs 141-144 after cycle 57 is shown in FIG. 7. In FIG. 7, empty storage cells are indicated by shading.

It is possible in the present 2-D DCT example for the write address counter 151 to write received matrix elements in the STRAMs 141-144 while the read address counter 152 simultaneously reads-out pairs of previously stored matrix elements. The simultaneous reading-out and writing of matrix elements is now described.

Like the write address counter 151, the read address counter 152 can count according to a number of read counter orders such as shown in FIGS. 8(a)-(d). The read counter orders may be predetermined and fixed or may be adjustable by transmitting a select signal to select inputs of the read counter 152 (not shown in FIG. 5). As shown in FIGS. 8(a)-8(d), the read address counter 152 accesses two storage cells simultaneously, one in each of two STRAMs 141-144. For example, in FIG. 8(a), on cycle 1, the read address counter 152 reads-out the elements in storage cells 171-0 and 173-0 of the STRAMs 141 and 143, respectively. Furthermore, the read address counter 152 repeats its access to the storage cells so as to repeat each outputted column of the received matrix. For example in FIG. 8(a), the read address counter 152 accesses one column 171-0, 173-0, 171-4, 173-4, 171-8, 173-8, 171-12, and 173-12 of the STRAMs 141 and 143 on cycles 1-4 and then access the same column of each STRAM 141 and 143 on cycles 5-8. This causes the read address counter 152 to read-out the sequence of pairs (y.sup.1.sub.0, y.sup.1.sub.56) , (y.sup.1.sub.8, y.sup.1.sub.48) , (y.sup.1.sub.16, y.sup.1.sub.40) , (y.sup.1.sub.24, y.sup.1.sub.32) on cycles 1-4 , respectively, and on cycles 5-8, respectively.

In order for the read and write address counters 151 and 152 to simultaneously read-out and write matrix elements, they must be synchronized in relation to each other. Assume that after cycle 57, the state of the STRAMs is as shown in FIG. 7. Starting on cycle 58, the read address counter 152 can begin to read-out pairs of matrix element according to the order shown in FIG. 8(a). Thus on cycle 58, the write address counter 151 stores the matrix element y.sup.1.sub.57 in the storage cell 173-1. In addition, the read address counter 152 reads-out the pair of matrix elements (y.sup.1.sub.0, y.sup.1.sub.56) from the storage cells 171-0 and 173-0. The read address counter 152 achieves this by outputting a single address to each STRAM 141-144 which reads-out the contents of the storage cells 171-0, 172-0, 173-0 and 174-0 in parallel. The read address counter 152 also outputs appropriate S1 and $2 select control signals for causing the multiplexer 161 to select the element outputted from the STRAM 143, for causing the multiplexer 162 to select the element outputted from the STRAM 141 and for causing the multiplexer 163 to select the element outputted from the multiplexer 161 (which element was outputted from the STRAM 143).

Likewise, on cycle 59, the write address counter 151 writes the element y.sup.1.sub.58 in the storage cell 173-2 while the read address counter 152 reads of the pair of elements (y.sup.1.sub.8, y.sup.1.sub.48) from the storage cells 171-4, 173-4. This process continues through cycle as shown in Table 3 below.

After cycle 64, the write address counter 151 has written in the last element y.sup.1.sub.63 of the first received matrix Y1. Furthermore, the read address counter 152 has nearly read out the entire first column of the matrix Y1 (in shuffled column row order) twice. The write address counter 151 may now write the elements of a second received matrix Y2 in the STRAMs 141-144 (which elements of the matrix Y2 are sequentially received in row-column order, i.e., y.sup.2.sub.0, y.sup.2.sub.1, . . . , y.sup.2.sub.8, y.sup.2.sub.9, . . ., y.sup.2.sub.63). However, the write address counter 151 may only write elements into storage cells no longer needed by the read address counter 152. That is, the write address counter 151 may only write received elements of the matrix Y2 into storage cells containing elements of the matrix Y1 already read-out by the read address counter 152 (or which will simultaneously be read-out by the read address counter 151). For instance, the write address counter 151 may write each element of the first row of the matrix Y2 into storage cells 171-0, 171-4, 171-8, 171-12, 173-0, 173-4, 173-8, and 173-12 which currently store the first column of the matrix Y1. In order to properly store the elements of the matrix Y2, in the cells no longer needed by the read address counter 152, the write address counter 151 counts according to the order shown in FIG. 6(d). Thus, on cycle 65, the write address counter 151 writes the element y.sup.2.sub.0 in the storage cell 171-0 while the read address counter 152 reads-out the elements (y.sup.1.sub.24, y.sup.1.sub.32) from the storage cells 171-12, 173-12. The writing of elements of the matrix Y2, and the read-out of elements of the matrix Y1, continues through cycle 121 as shown in Table 3. After cycle 121, the state of the STRAMs 141-144 is as shown in FIG. 9. In FIG. 9, shading is used to indicate storage cells which are "not needed" by the read address counter 152.

Starting on cycle 122, the read address counter 152 begins reading-out the elements of the matrix Y2. However, the matrix Y2 has been written in the storage cells of the STRAMs 141-144 according to a different counter order (FIG. 6(d)) than the matrix Y1 (FIG. 6(a)). Thus, the read address counter 152 must count according to a different order, i.e.., the read counter order shown on FIG. 8(d). Thus, on cycle 122, the write address counter writes the element y.sup.2.sub.57 in storage cell 172-4 while the read address counter 152 reads-out the elements (y.sup.2.sub.0, y.sup.2.sub.56) from the storage cells 171-0, 172-0. This simultaneous read-out according to the order of FIG. 8(d) and writing according to the order of FIG. 6(d) continues through cycle 128 as shown in Table 4 below.

On cycle 129, the write address counter 151 begins writing elements of a subsequently received matrix Y3 in storage cells no longer needed by the read address counter 152. To that end, the write address counter 151 counts according to the write counter order shown in FIG. 6(a). Thus, on cycle 129, the write address counter 151 writes the element y.sup.3.sub.0 in the storage cell 171-0 while the read address counter 152 reads-out the elements (y.sup.2.sub.24, y.sup.2.sub.32) from the storage cells 171-3 and 172-3. The simultaneous writing of elements of the matrix Y3 according to the write counter order of FIG. 6(a) and read-out of the matrix Y2 according to the read counter order of FIG. 8(d) continues through cycle 185 as shown in Table 4. After cycle 185, the state of the STRAMs is as shown in FIG. 10 (wherein storage cells which are "not needed" by the read address counter 152 are shown with shading).

As shown in FIG. 10, the storage of elements of the matrix Y3 is identical to the storage of elements Y1 (FIG. 7). Thus, it is possible to continue simultaneously writing received matrices and reading-out previously stored matrices indefinitely. In other words, the transpose memory 120 can continuously transpose intermediate matrices Y (without stoppages) if the write address counter 151 alternately counts according to the write counter orders FIGS. 6(a), 6(d) (i.e., according to FIG. 6(a) for each odd received matrix Y1, Y3, . . . and according to FIG. 6(d)for each even received matrix Y2, Y4, . . .) and the read address counter 152 alternately counts according to the read counter orders of FIGS. 8(a), 8(d). Furthermore, an examination of the write counter orders 6(a) and 6(d) reveals that they are the transpose of each other. Likewise, The read counter orders 8(a) and 8(d) are the transpose of each other.

The transpose memory 120 can also be used in a 2-D IDCT circuit. As shown in Table 1, the 1-D IDCT 110 circuit outputs a shuffled row-column sequence on the data-in line 111. The second 1-D IDCT circuit 140 requires two elements of the intermediate matrix Y at a time in column-row order wherein each column is repeated. This is achieved by the transpose memory 120 as follows. Suppose the 1-D IDCT circuit 110 (FIG. 4) sequentially outputs the elements of the matrices Y1, Y2, Y3, Y4, . . .. A first shuffled row-column ordered intermediate matrix Y1 is outputted from the 1-D IDCT circuit 110 onto the data-in line 111. The write address counter 151 counts according to the second write counter order 6(b) and writes the received matrix elements as shown in Table 5 below.

That is, on the first cycle, the element y.sup.1.sub.0 is written into the storage cell 171-0, on the second cycle, the element y.sup.1.sub.7 is written into the storage cell 172-3, on the third cycle, the element y.sup.1.sub.1 is written into the storage cell 172-0, on the fourth cycle, the element y.sup.1.sub.6 is written into the storage cell 171-3, etc. FIG. 11 shows the state of the storage cells of the STRAMs 141-144 after the cycle 56 (wherein shading indicates empty storage cells).

Table 6 below illustrates the simultaneous read-out and writing of matrix elements in the STRAMs 141-144 on cycles 57-120,

Starting on cycle 57, the read address counter 152 begins to read-out the matrix elements of the matrix Y1 according to the read counter order shown in FIG. 8(b). Thus, on cycle 57, the write address counter 151 writes the element y.sup.1.sub.56 in the storage cell 173-12 while the read address counter 152 reads out the elements (y.sup.1.sub.0, y.sup.1.sub.8) from the storage cells 171-0 and 173-0.

On cycle 65, the write address counter 151 begins writing the elements of the matrix Y2 in the storage cells of the STRAMs 141-144 no longer needed by the read address counter 152. To that end, the write address counter 151 counts according to the write counter order shown in FIG. 6(c). Thus on cycle 65, the write address counter 151 writes the element y.sup.2.sub.0 in the storage cell 171-0 while the read address counter 152 reads-out the elements (y.sup.1.sub.1, y.sup.1.sub.9), from the storage cells 172-0 and 174-0. The simultaneous writing of matrix elements according to the write counter order of FIG. 6(c) and read-out of elements according to the read counter order of FIG. 8(b) continues in this fashion through cycle 120. After cycle 120, the state of the STRAMs 141-144 is as shown in FIG. 12 (wherein shading indicates storage cells no longer needed by the read address counter 152).

Table 7 shows the simultaneous writing and read-out of elements in the STRAMs 141-144 on cycles 121-184.

The write address counter 151 counts according to the write counter order shown in FIG. 6(c) through cycle 128 for purposes of writing the elements of the matrix Y2. Then the write address counter counts according to the write counter order of FIG. 8(c) during cycles 121 through 184 for purposes of writing the elements of the matrix Y3. After cycle 184, the state of the STRAMs 141-144 is as shown in FIG. 13 (wherein shading indicates storage cells not needed by the read address counter 152). The state shown in FIG. 13 is similar to the state shown in FIG. 11. It is therefore possible to continue to simultaneously read-out and write matrices indefinitely according to the above-described process.

As with the 2-D DCT circuit 100, the transpose memory 120 can transpose intermediate matrices continuously (without stoppages) in the 2-D IDCT circuit 100. In such a case, the write address counter 151 alternately counts according to the write counter order of FIG. 6(b) and the write counter order of FIG. 6(c). Likewise, the read address counter 152 alternately counts according to the read counter order FIG. 8(b) and the read counter order of FIG. 8(c). Again, the write counter orders of FIGS. 6(b) and 6(c) are the transpose of each other. Likewise the read counter orders of FIGS. 8(b) and 8(c) are the transpose of each other.

As shown above, the write address counter 151 stores matrix elements in the STRAMs 141-144 in a fashion which facilitates the simultaneous read-out of a pair of matrix elements in the appropriate output sequence order. For instance, in the case that the matrix elements are to be outputted to a 1-D DCT circuit 140, the output sequence order is a shuffled column-row ordered sequence wherein each shuffled column is repeated, i.e., (y.sub.0, y.sub.56) , . . . , (y.sub.24, y.sub.32), (y.sub.0, y.sub.56), . . ., (y.sub.24, y.sub.32), (y.sub.31, y.sub.39). Each pair of elements in the outputted sequence includes matrix elements from different quadrants. These matrix elements can be easily read-out simultaneously in pairs by the read address counter 152 because the write address counter 151 has stored the elements from different quadrants in different STRAMs 141-144. Likewise, matrix elements to be outputted to a 1-D IDCT circuit 140 are outputted in column-row order wherein each column is repeated, i.e., (y.sub.0, y.sub.8), . . ., (y.sub.48, y.sub.56), (y.sub.0, y.sub.8), . . ., (y.sub.55, y.sub.63). Each pair of elements comprises an element from an even row and an element from an odd row. Again, such pairs can be easily read-out simultaneously because the first counter 151 writes elements in odd rows in different STRAMs 141-144 than elements in even rows.

As further shown above, the write address counter 151 writes the received matrix elements in particular storage cells within each STRAM 141-144 for purposes of simplifying the read-out of matrix elements by the read address counter 152. An examination of the read counter orders of FIGS. 8(a)-(d) reveals that the read address counter 152 can simply output a single read address to each STRAM 141-144 and the appropriate selector control signals S1 and S2 in order to output a pair of elements. This is because the write address counter 151 writes the elements which form each outputted pair at corresponding addresses in their respective STRAMs 141-144. For example, as shown in Table 3 and FIG. 8(a), in order to read out the pair (y.sub.8), y.sup.48), the read address counter 152 can output a single address to each STRAM 141-144 (namely, the address for the storage cells 171-4, 172-4, 173-4 and 174-4) and appropriate selector control signals S1 and S2 (for selecting the matrix elements y.sub.8 and y.sub.16 outputted from the storage cells 171-4 and 173-4 of STRAMs 141 and 143).

The transpose memory 120 can also output each matrix of a received sequence of matrices according to different output sequence orders. For instance, a first inputted matrix can be outputted in shuffled column-row order while a second inputted matrix can be outputted in column-row order. However, in such a case, the first matrix must be read-out of the transpose memory 120 entirely before the second matrix is written in. Nevertheless, the delay incurred by the second matrix is only one block latency, wherein a block latency equals the time required to merely read-out a previous matrix from the STRAMs 141-144. This is an improvement over conventional transpose memories in which the second matrix would incur at least one system latency, wherein a system latency equals the time required to propagate one matrix through both 1-D transform circuits, the transpose memory, and the pre- and post-processing circuits.

In short, a transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to a first type of transform circuit (e.g., DCT), the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to a second type of transform circuit (e.g. IDCT), the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element. Thus, the transpose memory occupies little area on an IC chip yet is capable of outputting elements according to one of a number of possible orders regardless of the input order.

Finally, the above description is intended to be merely illustrative. Numerous other embodiments may be devised by those having ordinary skill in the art without departing from the spirit and scope of the following claims.