Matrix Multiplier Circuit

The present invention relates to a circuit for multiplying matrices.

Conceptually, a two dimensional matrix multiplier circuit functions through use of a multiplier and an accumulator. Recently, distributed arithmetic has been utilized to simplify the design of the multiplier circuit and increase the speed of computation. A multiplier circuit which utilizes distributed arithmetic takes advantage of both pipeline processing and parallel processing. When there is an appropriate match between pipeline processing and parallel processing, throughput is increased. It is an object of the present invention to provide a matrix multiplier circuit based on distributed arithmetic, in which throughput is increased by providing an appropriate match between pipeline processing and parallel processing.

In the field of digital signal processing, matrix multiplication is used extensively to transform a set of data into various domains. For example, the discrete cosine transform, the inverse discrete cosine transform, and the discrete Fourier transform utilize matrix multiplication.

Consider, for example, the matrix multiplication

where

X is an input data matrix,

B is a transformation matrix whose elements are constant transform coefficients, and

C is the output data matrix.

The data matrix X is of size I rows.times.J columns. The transformation matrix B is of size J rows.times.K columns. The output matrix c is of size I rows.times.K columns. Thus, the matrix X is comprised of the elements x.sub.ij i=1,2, . . . ,I, j=1,2, . . . ,J. The matrix B is composed of the elements b.sub.jk, k=1, . . . ,K. The matrix C is composed of the elements c.sub.ik.

Equation (1) can be rewritten as ##EQU1##

The conventional matrix multiplier circuit which utilizes distributed arithmetic multiplies one row of J elements x.sub.ij with K columns of elements b.sub.jk to obtain one row of elements c.sub.ik. In the conventional matrix multiplier, pipelining is controlled by the precision (i.e. the number of bits) M in the elements x.sub.ij, whereas parallel processing is determined by the size J of the X and B matrixes. When M is larger or smaller than J, the pipeline processing and parallel processing in the multiplier circuit are not well matched. It is an object of the present invention to provide a matrix multiplier circuit which utilizes distributed arithmetic and which takes more complete advantage of pipeline and parallel processing to achieve a higher throughput.

As indicated above, in the conventional matrix multiplier circuit utilizing distributed arithmetic, one row of J elements x.sub.ij is multiplied in parallel with K columns of elements b.sub.jk to obtain one row of elements c.sub.ik. In contrast, in accordance with the multiplier circuit of the present invention, N rows of elements x.sub.ij are multiplied in parallel with K columns of elements b.sub.jk to obtain N rows of elements c.sub.ik. If M is approximately equal to NJ (in particular, if N is the integer nearest to M/J) the maximum advantage of both pipeline processing and parallel processing is achieved.

More particularly, in accordance with the present invention, a matrix multiplier circuit comprises a first pipeline stage formed from an input shift register for sequentially receiving in bit parallel form over a period of NJ time units a first set of NJ data elements x.sub.ij from N rows of the data matrix X. Each data element x.sub.ij has a precision of M bits. The first set of NJ data elements is shifted concurrently in bit parallel form to a second pipeline stage. The second pipeline stage serves to multiply in parallel the first set of NJ data elements with the elements b.sub.ij from K columns of the transform matrix B. The output of the second stage is N rows of elements c.sub.ik of the output matrix C. To perform the multiplications, the second stage utilizes distributed arithmetic so that the multiplications require M time units. While the second pipeline unit is performing multiplications with the first set of NJ data elements, a second set of NJ data elements formed from a plurality of rows from the data matrix is shifted into the input shift register in the first pipeline stage.

Pipeline bottlenecks are eliminated and throughput is optimized if N is approximately equal to M/J. For example, N may be equal to the nearest integer to M/J. In this case, the amount of time required to perform the parallel multiplications in the second pipeline stage is approximately equal to the time required to shift a set of NJ data elements into the shift register of the first pipeline stage.

FIG. 1 schematically illustrates a conventional multiplier circuit based on distributed arithmetic.

FIG. 2 illustrates an RAC unit for use in the multiplier circuit of FIG. 1.

FIG. 3 illustrates a multiplier circuit based on distributed arithmetic in accordance with an illustrative embodiment of the present invention.

Before discussing the inventive matrix multiplier circuit in detail, it may be helpful to briefly review the operation of the conventional matrix multiplier circuit based on distributed arithmetic.

As indicated above, the conventional matrix multiplier circuit computes the elements ##EQU2## In particular, the conventional matrix multiplier multiplies in parallel one row of J elements x.sub.ij with K columns of elements b.sub.jk to output one row of elements c.sub.ik.

The value of each data element x.sub.ij is represented as ##EQU3## where x.sub.ij (m), m=0,1, . . . , M-1, is the m.sup.th bit of x.sub.ij which has a value logic 0 or logic 1, M is the number of bits in x.sub.ij, and x.sub.ij (M-1) the sign bit.

Utilizing equation (3), equation (2) can be rewritten as ##EQU4##

Each quantity ##EQU5## may be evaluated as follows. Each quantity S.sub.ij is a function of the fixed transformation matrix elements b.sub.jk. Each quantity S.sub.ik Can take on 2.sup.J possible values because x.sub.ij (m),j-1, . . . ,J can take on any one 2.sup.J possible patterns of 1's and 0's. Thus, 2.sup.J possible values for each quantity S.sub.ij are computed in advance and stored in a memory. A particular value of a quantity S.sub.ik can then be obtained by using the pattern x.sub.ij (m) as the address to a memory storing all the possible values of S.sub.ik.

The above described distributed arithmetic serves as the basis for implementing the conventional distributed arithmetic multiplier circuit which multiplies in parallel one row of elements x.sub.ij from the data matrix X with K columns of elements b.sub.jk from the transformation matrix B to obtain one row of elements c.sub.ik of the output matrix C.

Such a conventional multiplier circuit is illustrated in FIG. 1. The multiplier circuit 10 of FIG. 1 is illustratively designed to process one row of J elements x.sub.ij for the case where J=8 and where each element x.sub.ij comprises eight data bits and one sign bit for a total of nine bits. The multiplier circuit 10 of FIG. 1 comprises a first pipeline stage 11 which is formed by a first shift register 12. The shift register 12 comprises J=8 register units 14 each of which is nine bits wide. The data elements xp.sub.i1, x.sub.i2, . . . x.sub.i8 are shifted sequentially in time with bit parallel structure into the eight stage, nine-bit wide shift register 12 at the input data rate 1/T. After 8 T time intervals, the contents of each register unit 14 are moved concurrently in bit parallel form via the lines 15 to a second pipeline stage 13 which includes the register units 16. The register units 16 together form a second non-shift register 50.

The second pipeline stage 13 also comprises a plurality of RAC units 20. The detailed structure of a RAC unit 20 is discussed below in connection with FIG. 2. For now it is sufficient to note that each RAC unit 20 includes a ROM for storing all the possible values of S.sub.ik for one value of k. There are a total of eight RAC units 20 in the circuit of FIG. 1 so that k takes on the values k=1, , . . . ,K, K=8. The corresponding RAC units are labeled RAC(1), RAC(2), . . . ,RAC(8). The unit RAC(k) outputs in bit parallel form on the lines 22 the element c.sub.ik. The bits comprising each element c.sub.ik are loaded in bit parallel form into a corresponding register unit 24 of a shift register 26. The elements c.sub.i1, c.sub.i2, . . . , c.sub.ik are then shifted out of the shift register 26 sequentially in time with bit parallel structure.

A RAC unit 20 is illustrated in greater detail in FIG. 2. The RAC unit 20 of FIG. 2 makes use of the technique of partial sums to reduce memory requirements. The RAC unit 20 comprises two ROM units 30 and 32. Each of the ROM units is addressed by a four-bit number and the output of the two ROM units are added by the adder 34. If the technique of partial sums is not utilized, the RAC unit may comprise a single ROM unit which is addressed by an eight-bit number and the adder 34 is eliminated.

The RAC unit 20 also includes an accumulator 40 which is formed from the adder/subtractor unit 42 and the shift register 44. The shift register 44 has a hard wired one-bit shift right which is designed with the label 46.

Returning now to FIG 1, the calculation of the elements c.sub.ik proceeds as follows. The bits comprising the data elements x.sub.i1, x.sub.i2, . . . ,x.sub.iJ are concurrently shifted out of the register units 16 in bit serial form on the lines 17. Thus, in each time interval T there appears on the lines 17 a pattern x.sub.ij (m). The pattern x.sub.ij (m) serves as an address of the ROMs contained in the RAC units 20. Specifically, the eight bits comprising the pattern x.sub.ij (m) for each value of m are divided into two four-bit address groups, with one four-bit address group appearing on the lines 18 and one four-bit address group appearing on the lines 19. The four-bit address on lines 18 is utilized to address the ROM 30 in each RAC unit and the four-bit address on line 19 is utilized to address the ROM 32 in each RAC unit. Thus, for each value of m there is successively obtained on the lines 17 a pattern of bits which is used to address the ROMs 30 and 32 in each RAC unit. For each value of m, the outputs of the two ROMs 30 and 32 are summed using the adder 34 to obtain a value of S.sub.ik. Thus, nine values of D.sub.ik (one for each value of m) are obtained sequentially in time at the output of the adder unit 34 in each RAC. For example, the values of S.sub.i1 are obtained at the output of the adder 34 in the RAC(1) and the values of S.sub.i2 are obtained in the RAC(2) etc. The sums over m in equations (4) and (5) are evaluated using the accumulator 40 in each RAC unit. In particular, for each successive value of m, m-0,1, . . . ,M-2, each corresponding successive value of S.sub.ik is added, using the adder/subtractor unit 42, to the contents of shift register 44 with the one-bit shift right. When m reaches M-1, the unit 42 performs a subtraction instead of an addition. The resulting output is an element c.sub.ik of the output matrix C.

The matrix multiplier circuit 10 of FIG. 1 exploits both pipelined processing and parallel processing. In particular, while one row of data elements is being sequentially entered into the register units 14 of the shift register 12 of the first pipeline stage 11, a row of previously entered data elements, now stored in the register units 16, is processed in parallel by the RAC units. The entering of a row of J data elements x.sub.ij into the shift register 12 takes J time units. The processing of a previously entered row of data elements by the RAC units takes M time units. This pipeline works most efficiently if M is approximately equal to J. When the precision of the data elements of the data matrix X is high, i.e. when M>J, the processing by the RAC units becomes a bottleneck in the pipeline, as the shifting of data into the shift register 12 and out of the shift register 26 is much faster than the processing by the RAC units.

The matrix multiplier circuit of the present invention overcomes this bottleneck in the case of high precision data elements by providing a matrix multiplier with a high throughput.

FIG. 3 illustrates a matrix multiplier circuit in accordance with an embodiment of the present invention. The matrix multiplier 100 of FIG. 3 has a higher throughput than the matrix multiplier 10 of FIG. 1 for the case where M>J. In particular, the matrix multiplier 100 comprises N modules labeled 1,2, . . . ,N. Each of the modules 1,2, . . . ,N is identical to the multiplier circuit 10 of FIG. 1. The number of modules N is chosen so that it is approximately equal to M/J, e.g., N may be chosen so that it is equal to the nearest integer to M/J. When N is chosen in this manner there is an optimal matching between pipeline processing and parallel processing in the matrix multiplier circuit.

The matrix multiplier circuit 100 multiplies in parallel NJ elements x.sub.ij from N rows of the input data matrix X with K columns b.sub.ij of the transform matrix B to output N rows of elements c.sub.ij of the output matrix C.

The individual modules in the matrix multiplier circuit 100 of FIG. 3 are interconnected as follows. The input shift registers 112 of each module 1,2, . . . ,N are interconnected to form a single shift register 212 comprising NJ individual register units 114. Illustratively, each register unit 114 is nine bits wide. Similarly, the output shift registers 126 of each module 1,2, . . . ,N are connected to form a single shift register 226 comprising NJ individual register units 124.

The circuit 100 of FIG. 3 operates to optimally combine parallel and pipelined processing as follows. It takes NJ time units to shift NJ data elements x.sub.ij from the data matrix X into the shift register 212. While one set of NJ data elements is being shifted into the shift register 212, a previous set of NJ data elements now stored in the register units 116 are multiplied in parallel with the elements b.sub.jk from K rows of the transformation matrix B. As described above, it takes M time units for the RAC units 120 in each module to generate and add the quantities S.sub.ik to obtain a value of c.sub.ik. Because NJ is approximately equal to M there is a good match between pipeline and parallel processing in the circuit 100 of FIG. 3. It should be noted that in the circuit 100 of FIG. 3, NJ elements c.sub.ik comprising N rows of the output matrix C are shifted out of the shift register 226 in sequence.

Finally, the above described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the following claims.