Method for Composing Addresses of a Memory

The present invention relates to a method for generating addresses of a memory in which a plurality of data corresponding to a plurality of addresses can be assessed simultaneously.

Ordinarily, while a data is written in or read out of one address of a memory, the other memory addresses or locations cannot be accessed. If a plurality of addresses were accessible simultaneously, many advantages are realized, including an increase in processing speed due to the reduction of the access time, and so forth.

A method wherein a plurality of memory locations are accessed at the same time, has been proposed by the prior art. The ability to access, simultaneously, several memory locations is very important particularly when interpolation calculations are to be carried out. Under such circumstances, it is very useful to retrieve data located in adjacent memory locations simultaneously, because the value of an unknown parameter is calculated by interpolating between the adjacent values which are retrieved from the memory. Although the prior art teaches a method for simultaneous retrieval of adjacent data, that method is applicable to one dimensional data space only. For example, when addresses (x) which correspond to the numbers 0, 1, 2, 3, . . . , increase solely along one-dimention, a memory 1 having addresses continuously composed, as shown in FIG. 1, is separated into a plurality of distinct memory banks, and the addresses are not stored continuously into the plurality (two in this embodiment) of memory banks 2 and 3, as shown in FIG. 2a, but instead are stored in an interlace fashion into bank memories 4 and 5 by a so-called memory interlacing method, as shown in FIG. 2b. According to the memory interlacing method, the adjacent addresses such as (2) and (3), or (15) and (16) can be accessed at the same time.

However, in a conventional memory such as a table memory having 2-dimensional addresses (x,y), wherein x is a progression of 0, 1, 2, 3, . . . and y is a progression of 0, 1, 2, 3, . . . , a plurality of addresses i.e. memory locations cannot be accessed at the same time. The prior art interlacing method which is applicable to one-dimensional addresses cannot be used with 2-dimensional memories. Accordingly, there exists no effective way for dividing a multi-dimensionally organized memory into distinct memory banks to enable simultaneous accessing of data according to known art.

It is an object of the present invention to provide a method for deriving addresses in connection with a memory having n-dimensional addresses defined over a logical address space consisting of a plurality of unit divisions, each unit division having vertices defined by the n-dimensional address. The generated addresses are so arranged and selected as to enable the simultaneous accessing of a plurality of data elements located at respective n-dimensional addresses.

According to the present invention there is provided a method for deriving addresses of a memory, which comprises dividing the n-dimensional addresses of a memory space organized in a logical address space consisting of a plurality of unit divisions, each having vertices with the n-dimensional addresses, into 2.sup.n memory banks, each having independent data lines and address lines. The addresses are so divided that each of the addresses which correspond to a single unit division and which define the vertices of that unit are located in different memory banks. With this arrangement, all the addresses of the vertices of the unit division can be accessed at the same time. Moreover, the invention specifies the relationship between a given n-dimensional address and the memory bank to which it is allocated as well as the location of that address within its respective memory bank.

In order that the present invention may be better understood, preferred embodiments thereof will be described with reference to the accompanying drawings, in which:

FIG. 1 shows addresses of a memory, which are organized in a conventional manner;

FIG. 2(a) shows addresses stored in two conventional memory banks and FIG. 2(b) shows addresses stored according to a conventional memory interlacing method;

FIG. 3 shows four memory banks in which two-dimensional addresses are arranged according to the present invention;

FIG. 4 shows a look-up table memory which expresses bank memory numbers and two-dimensional addresses composed according to the present invention;

FIG. 5 shows a look-up table memory which expresses bank memory numbers and three-dimensional addresses composed according to the present invention;

FIG. 6 is a schematic view for explaining an interpolation according to the present invention; and

FIG. 7 is a block diagram of arithmetic circuits for performing the interpolation according to the present invention.

The present invention will now be described in connection with FIGS. 3-7. A logical address space of a memory having n-dimensional addresses is composed of a plurality of unit divisions, each having vertices with the n-dimensional addresses. In a two-dimensional system, the addresses of the vertices of one unit division having a square form are expressed as a set of addresses such as for example addresses (1,1), (2,1), (1,2) and (2,2), and so forth, and in a three-dimensional system, the addresses of the vertices of one unit division having a cubic form are expressed as a set of (1,1,1), (2,1,1), (1,2,1), (1,1,2), (2,2,1), (2,1,2), (1,2,2) and (2,2,2), and so forth.

First, in order that the present invention may be better understood, it will be explained in terms of two-dimensional addresses (x,y), wherein x means 0, 1, 2, 3, . . . , and y means 0, 1, 2, 3, . . . .

In this embodiment, as shown in FIG. 3, the memory is divided into 2.sup.2 =4 memory banks 6, 7, 8 and 9, hereinafter referred to as t0, t1, t2 and t3, respectively, each having independent address lines and data lnes, and each address data of the four vertices of the unit division is stored into each memory bank t0, t1, t2 or t3.

That is, when y equals zero, the address data (x,y) are stored in the memory banks: such as (0,0) into the memory bank t0, (1,0) into the memory bank t1, (2,0) into the memory bank t2, (3,0) into the memory bank t3, (4,0) into the memory bank t0, (5,0) into the memory bank t1, and the like. In general, the address data (x,y) is stored into a memory bank tp.sub.2, wherein p.sub.2 means a residue which is obtained by a division (x+2y)/2.sup.2.

This relation is shown visually in FIG. 4 showing the memory bank numbers and the two-dimensional addresses. That is, the intersections of the two lines extending in the x and y directions mean the two-dimensional addresses (0,0), (0,1), . . . , and the numbers "0", "1", "2" and "3" appearing on the intersections indicate the serial numbers attached to the memory banks, i.e. "0", "1", "2" and "3" mean the memory banks t0, t1, t2 and t3, respectively.

Hence, the serial number p.sub.2 of the memory bank tp.sub.2 in which an address (x,y) is to be stored, is obtained by the following formula (I), shown below, wherein MODE.sub.2 () means a residue obtained by dividing a number in the parenthesis by 2.sup.2.

Further, as described above, the addresses of the vertices of the unit division are separately stored in the different memory banks, and accordingly the addresses stored in each memory bank are non-sequential. However, in order to distribute effectively the addresses into the different memory banks, the relation between the address (x,y) of the memory and the address (x',y') of the memory bank is determined by the following formulae (II), wherein numbers x/2 and y/2 in the parenthesis are integral numbers, ignoring the fraction that is generated by the arithmetic operation. ##EQU1##

In other words, the addresses of the vertices of each unit division are distributed into different memory banks having independent address lines and data lines.

Next, the present invention will be described with reference to a three-dimensional system, wherein each unit division has a cubic form and eight vertices. Each vertex has a three-dimensional address (x,y,z) wherein x means 0, 1, 2, 3, . . . , y means 0, 1, 2, 3, . . . , and z means 0, 1, 2, 3, . . . .

In this embodiment, the memory is divided into 2.sup.3 =8 memory banks t0, t1, t2, t3, t4, t5, t6 and t7, each having independent address lines and data lines, and the addresses of the vertices of each unit division are so generated to permit them to be stored into the different memory banks.

For instance, when y equals zero and z equals zero, the address data (x,y,z) are stored in the memory banks as follows: (0,0,0) into the memory bank t0, (1,0,0) into the memory bank t1, (2,0,0) into the memory bank t2, (3,0,0) into the memory bank t3, (4,0,0) into the memory bank t4, (5,0,0) into the memory bank t5, (6,0,0) into the memory bank t6, (7,0,0) into the memory bank t7, (8,0,0) into the memory bank t0, and the like. Generally, an address data (x,y,z) is stored into a memory bank tp.sub.3, wherein a serial number p.sub.3 means a residue which is obtained by a division (x+2y+4z)/2.sup.3. This relation is shown in FIG. 5 showing the memory bank numbers and the three-dimensional addresses.

The serial number p.sub.3 of the memory bank tp.sub.3 in which the address (x,y,z) is to be stored, is obtained in the following formula (III), wherein MODE.sub.3 () means a residue obtained by dividing a number in parenthesis by 2.sup.3.

In addition, the relation between the address (x,y,z) of the memory and the address (x',y',z') of each memory bank is determined in the following formulae (IV), wherein numbers x/2, y/2 and z/2 in the parenthesis are integral numbers obtained by discarding the fractional component of the result of the division. ##EQU2##

As described above, the addresses of the vertices of each unit division are distributed in the different memory banks, each having independent address lines and data lines.

Now, the present invention will be described with reference to a n-dimensional system, wherein each unit division has n vertices with n-dimensional addresses (A.sub.1, A.sub.2, A.sub.3, . . . and A.sub.n) (n=1, 2, 3, . . . ).

In this embodiment, the memory is divided into 2.sup.n memory banks t0, t1, t2, t3, . . . and t(2.sup.n -1), each having independent address lines and data lines. Generally, an address data (A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.n) is stored into a memory bank tp.sub.n, wherein a serial number p.sub.n is obtained by the following formula (V) which is developed from the above mentioned formulae (I) and (III), wherein MODE.sub.n () means a residue obtained by dividing a number in parenthesis by 2.sup.n. ##EQU3##

Further, the relation between the address (A.sub.1, A.sub.2, A.sub.3, A.sub.4, . . . , A.sub.n) of the memory and the address (A.sub.1 ', A.sub.2 ', A.sub.3 ', A.sub.4 ', . . . , A.sub.n ') of each memory bank is determined in the following formulae (VI) in the same manner of those (II) and (IV) of the above described embodiments. ##EQU4##

Hence, according to the present invention, the n-dimensional addresses of the vertices of each unit division are distributed in the different memory banks, each having independent address lines and data lines, in the n-dimensional system.

It is readily understood from the above description that the addresses of the vertices of each unit division can be accessed at the same time. This differs from conventional methods in which the addresses must be accessed one at a time. The method of the invention is applicable even when the addresses become multi-dimensional and the addresses of the vertices of each unit division increase to a large number. Therefore, the time for accessing the memory locations corresponding to a unit division is significantly reduced according to the present invention.

In the above described embodiments of the present invention, the simultaneous access to the plurality of memory banks need not always be at the same absolute addresses, since each memory bank has independent address lines and its data can be retrieved independently of the data in the other memory banks.

One embodiment of the present invention will now be described. Of course, the present invention is not restricted to this embodiment.

When a first set of signals are converted into a second set of signals through a predetermined set of calculations, if the calculations taken a long time, and are performed over and over again, the second signals may be precalculated and the results stored in a memory look-up table. Then the data can be retrieved at any time by using the first signals as the addressing signals, thereby performing a signal conversion at a very high rate.

When two-dimensional first signals (x,y) are to be converted into two-dimensional second signals F(x,y), the obtained second signals corresponding to the first signals may be stored into a memory look-up table. As shown in FIG. 6, the second signal F(x.sub.i +x.sub.f, y.sub.i +y.sub.f), wherein x.sub.i and y.sub.i indicate integral parts and x.sub.f and y.sub.f indicate decimal parts, corresponding to the first signal (x.sub.i +x.sub.f, y.sub.i +y.sub.f), may be represented as a point G. This result may be obtained from the values F(x.sub.i, y.sub.i), F(x.sub.i +1, y.sub.i), F(x.sub.i, y.sub.i +1) and F(x.sub.i +1, y.sub.i +1), hereinafter referred to as interpolation data, of the second signals stored at the vertices of one interpolation area ABCD, according to the following formula (VII) for a straight line interpolation method. ##EQU5##

In order to perform such an interpolation, in a conventional method, the interpolation data are stored into one memory look-up table having a conventional address arrangement and thus must be read out of the look-up table one value at a time. However, as described above, according to the present invention, since a set of interpolation data corresponding to the addresses of the vertices of the unit division are stored in the different memory banks, the set of the interpolation data can be conveniently read out at the same time from the plurality of memory banks where all data is stored.

That is, according to the present invention, a set complete of interpolation data is read out in a time period during which the prior art reads out only a single data element. Therefore, in a two-dimensional system of the present invention, the time for retrieving the data for a unit division is reduced to one fourth of the time required according to the prior art.

Furthermore, the present method can be applied very effectively to a multidimensional memory look-up table for use in a color picture signal conversion, as described hierinafter in detail.

When a first set of color separation digital picture signals C, M, Y and K of a first signal system, employing cyan, magenta, yellow and black, corresponding to printing inks, are converted into a second set of color separation digital picture signals R, G and B of a second signal system, employing red, green and blue for reproducing images, the method of the invention can be used to simulate the final color on a video system. An expected printing finish according to the first picture signals is simulated by using a CRT monitor of a color scanner setup means or an electronic color proofreader. Values U(C.sub.i, M.sub.i, Y.sub.i, K.sub.i) of the second picture signals R, G and B are obtained in advance by performing a simulation arithmetic calculation and a signal conversion of upper four bits C.sub.i, M.sub.i, Y.sub.i and K.sub.i, corresponding to the integral parts, of the first picture signals C, M, Y and K expressed in 256 gradation (8 bits), are stored in a memory look-up table, in advance, whose addresses are derived by a method according to the present invention. Hence, the interpolation can be carried out thereafter at a high speed as follows.

In this embodiment, since the addresses (C, M, Y, K) of the memory look-up table are four-dimensional, the memory is divided into 2.sup.4 =16 memory banks t0, t1, t2, t3, . . . and t15. A serial number p.sub.4 of the memory bank tp.sub.4 is obtained by the following formula (VIII) which is obtained by substituting n=4, A.sub.1 =C.sub.i, A.sub.2 =M.sub.i, A.sub.3 =Y.sub.i and A.sub.4 =K.sub.i for the formula (V) described above, and the relation between the address (C.sub.i, M.sub.i, Y.sub.i, K.sub.i) of the memory and the address (C.sub.i ', M.sub.i ', Y.sub.i ', K.sub.i ') of the memory bank is determined by the following formula (IX), which is based on the formula (VI). ##EQU6##

Therefore, in this embodiment wherein the addresses are composed by the present method, the first picture signals C=C.sub.i +C.sub.f, M=M.sub.i +M.sub.f, Y=Y.sub.i +Y.sub.f and K=K.sub.i +K.sub.f, wherein C.sub.f, M.sub.f, Y.sub.f and K.sub.f correspond to lower four bits, may be obtained by determining 0.ltoreq.C.sub.f, M.sub.f, Y.sub.f, K.sub.f <1, which in turn may be obtained from one unit division by the interpolation of a set of 16 values U(C.sub.i, M.sub.i, Y.sub.i, K.sub.i), U(C.sub.i +1, M.sub.i, Y.sub.i, K.sub.i), . . . and U(C.sub.i +1, M.sub.i +1, Y.sub.i +1, K.sub.i +1). Thus, 16 interpolation data corresponding to 16 addresses (C.sub.i, M.sub.i, Y.sub.i, K.sub.i), (C.sub.i +1, M.sub.i, Y.sub.i, K.sub.i), . . . and (C.sub.i +1, M.sub.i +1, Y.sub.i +1, K.sub.i +1) of the vertices of the unit division including a point to be interpolated, can be read out of the different memory banks at the same time. Thus, the access time is significantly reduced according to the present invention.

By using the read-out interpolation data, the corresponding second picture signals R, G and B can be obtained according to the straight line interpolation method expressed by the following formula (X) or another simple interpolation method disclosed in Japanese Patent Application No. 52-57198 (Japanese Patent Laying-Open Specification No. 53-123201). ##EQU7##

In FIG. 7 there is shown an arithmetic circuit for performing the interpolation expressed by the formula (X), comprising 16 memory banks 10.sub.1 -10.sub.16 which output the interpolation data, selectors 11.sub.1 -11.sub.16, 12.sub.1 -12.sub.16, 13.sub.1 -13.sub.16 and 14.sub.1 -14.sub.16 which select C.sub.f or 1-C.sub.f, M.sub.f or 1-M.sub.f, Y.sub.f or 1-Y.sub.f, and K.sub.f or 1-K.sub.f, respectively, subtracters 15.sub.1 -15.sub.16, 16.sub.1 -16.sub.16, 17.sub.1 -17.sub.16 and 18.sub.1 -18.sub.16 which calculate 1-C.sub.f, 1-M.sub.f, 1-Y.sub.f and 1-K.sub.f, respectively, multipliers 19.sub.1 -19.sub.16, 20.sub.1 -20.sub.16, 21.sub.1 -21.sub.16 and 22.sub.1 -22.sub.16 for multiplying the outputs of the selectors 11-14 and the memory banks 10, and adders 23.sub.1 -23.sub.15 which sum up the multiplied values, thereby obtaining the interpolated value U(C.sub.i +C.sub.f, M.sub.i +M.sub.f, Y.sub.i +Y.sub.f, K.sub.i +K.sub.f).

In this embodiment, the interpolation data can be read out of the memory banks at the same time, and the calculation of the interpolation can be performed at the same time. Hence, the processing time of the interpolation can be largely reduced as compared with the conventional method.

Although the present invention has been described in some detail by way of illustration and example for purpose of clarity of understanding, it will, of course, be understood that various changes and modifications may be made in the form, details, and arrangements of the parts without departing from the scope of the present invention.