Self-Aligned Bipolar Transistor Structure and Fabrication Process

FIG. 1 is a cross sectional view showing a preferred embodiment of the present invention wherein a bipolar transistor is constructed in a single epi layer on top of a buried oxide layer.

FIGS. 2 through 8 are cross sectional views showing the processing steps of a preferred embodiment of the present invention wherein a bipolar transistor, along with an NMOS transistor, is constructed in a single epi layer on top of a buried oxide layer.

The present invention provides substantial advantages in circuits using bipolar transistors and particularly in circuits combining bipolar and CMOS transistors. The disclosed structure does not require that the polysilicon etch stop on single crystal silicon as has been required in prior art. The use of an oxide for the polysilicon etch stop in a fully self-aligned bipolar transistor has apparently never been done before. This structure has the distinct advantage that it is built in the same epitaxial layer 16 as the MOSFET. Another advantage is that this design has improved radiation hardness over prior art due to the reduced epitaxial thickness. One significant advantage of this structure is that the parasitic capacitances are reduced due to the fact that the diffusions extend down to the buried oxide such as for the extrinsic base.

The fabrication of this bipolar structure is described in the context of a CMOS/SOI process thus providing a BiCMOS/SOI process but it could also be used for a bipolar/SOI process. While this transistor structure is primarily suited for use on an SOI substrate, it can be used in a bulk process to avoid having to go through the processing of the buried N+layers. This is very attractive for use in a DRAM process where the substrate is a P-epi on a P+substrate and a buried layer which requires a high temperature cannot be formed. The only special requirement is that the tank depth be greater than the vertical isolation spacing in order to minimize the gain of the parasitic transistor (extrinsic base-tank-substrate). Also, note that the preferred embodiment is described as an NPN but could be built as a PNP.

The proposed structure is not truly self-aligned in that the emitter poly 60 does overlap an oxide 44 slightly but at the current alignment tolerances that steppers have, this is not expected to significantly alter the transistor characteristics.

FIGS. 1 through 8 are cross sectional diagrams showing a preferred embodiment of the present invention and method for forming the same. FIG. 1 is a cross sectional view of the bipolar transistor. The bipolar transistor 11 is formed in epi layer 16 which is the same epi layer used to form the NMOS transistor 13. The circuit contains buried oxide layer 10, n- type silicon epi layer (collector) 16, oxide sidewalls 36, nitride sidewalls 38, TEOS sidewalls 68, oxide layer 44, p-type active base 48, TEOS layer 50, nitride layer 52 (layers 50 and 52 are optional to increase dielectric thickness between emitter poly and base), n+polysilicon emitter 60, emitter and gate inner sidewall oxide (TEOS) spacers 66, p+extrinsic base 72 which is self-aligned to sidewall oxide spacer 66 on the emitter poly 60, emitter and gate outer sidewall oxide (TEOS) spacers 74, n+collector contact 76 which is self-aligned to outer sidewall oxide spacer 74 on the side of the emitter poly.

The process for integrating the bipolar npn structure into the 1.0-um CMOS/SOI process flow is shown in FIGS. 2 through 8 where the cross sections of a bipolar 13 and NMOS 11 transistor are shown. The process begins with SOI starting material (buried oxide) 10 that has a 0.6 to 0.8 um epitaxial layer 16 on it. After growing a pad oxide 20 and depositing a 1,000 angstrom nitride layer 22, the inverse of the bipolar collector region is patterned and the nitride is etched. An oxide 24 is grown to reduce the epitaxial thickness to approximately 0.33 um as required by the CMOS transistor design, shown in FIG. 2. After stripping the nitride 22, the bipolar collector 26 is implanted with ions such as phosphorus and annealed. The oxide layer 24 is removed by a wet deglaze. Next, a pad oxide 28 is grown, followed by a 1,400 angstrom nitride 30. The CMOS and bipolar mesas 13 and 11 are now patterned and the oxide/nitride stack is etched. After patterning and implanting ions such as boron (e.g. 0 degrees 1.8E13 cm-2 at 30 KeV and 3.0E13 cm-2 at 80 KeV) to form the NMOS channel stops 32, a 1,000 angstrom TEOS film is deposited, densified, and etched to form a sidewall oxide spacer 34 on the mesa stack, as shown in FIG. 3.

At this point, the silicon etch to form the mesas is performed. After the silicon etch, a 200 angstrom oxidation 36 is done on the mesa sidewall. After a nitride strip, the sidewall formation is completed by means of a 150 angstrom nitride 38 deposition followed by a 1,000 angstrom TEOS 40 deposition and plasma etch to form the sidewall (FIG. 4). The NMOS and PMOS threshold voltage, and tank implants are then patterned and implanted with ions such as boron (e.g. 1.7E12 cm-2 at 25 KeV and 3.5 E12 cm-2 at 80 KeV) for the NMOS threshold voltage and tank, and boron (e.g. 1.0E12 cm-2 at 24 KeV) and phosphorus (e.g. 2.7E12 cm-2 at 180 KeV) for the PMOS threshold voltage and tank.

After deglazing the dummy oxide from the mesa surface, a 200 angstrom gate oxide 44 is grown, followed by a 2,000 angstrom polysilicon deposition 46. It should be mentioned that a split polysilicon process is being used so that the MOS gate oxide 44 can be protected while the bipolar base 48 and emitter window 54 are being formed. The base 48 is formed following gate oxidation to limit its junction depth. The bipolar base region 48 is patterned and the polysilicon is removed from this region by a plasma etch. Next, the base of the bipolar transistor, shown in FIG. 5, is implanted through the remaining gate oxide. The base is formed following gate oxidation to limit its junction depth. Next, a 600 angstrom TEOS layer 50 is deposited, followed by a 200 angstrom nitride layer 52. TEOS layer 50 and nitride layer 52 are optional layers which are used to increase dielectric thickness between emitter poly and base. (Although not shown of the figures, these layers can be masked to slightly overlap the edges of the mesa to make alignment less critical.) The emitter contact is patterned so that it opens the emitter window 54 and all CMOS regions but leaves the TEOS/nitride stack 50 and 52 over the rest of the bipolar base region. The first 2,000 angstrom polysilicon film 46 protects the CMOS mesas during the emitter etch. This process has been used for bulk BiCMOS without any GOI (gate oxide integrity) degradation problems. FIG. 6 shows the cross section after the emitter etch.

Next, after a short deglaze, a 2,500 angstrom polysilicon layer is deposited and doped by implantation of ions such as arsenic (e.g. 1E16 cm-2 at 50 KeV) and phosphorus (may be optional) (e.g. 2E15 cm-2 at 80 KeV). This polysilicon layer serves as the bipolar emitter 60 and, in combination with the first polysilicon layer, forms a 4,500 angstrom polysilicon gate 62. Next, the gates and emitters are patterned and the polysilicon is etched, as shown in FIG. 7. After patterning and implanting both p (e.g. boron, 1.0E13 cm-2 at 20 KeV, 0 degrees) and n (e.g. phosphorus, 8.0E13 cm-2 at 80 KeV, 0 degrees) LDDs (lightly doped drains), a 2,500 angstrom TEOS layer is deposited and etched back to form sidewall oxide spacer 66 and 68. Then a 300 angstrom TEOS screen oxide (not shown) is deposited. Next, the p+(not shown) and n+source/drain (S/D) regions 70 are patterned and implanted. For the p+S/D regions, ions such as boron (e.g. 3.0E15 cm-2 at 20 KeV, 0 degrees) are implanted. For the n+S/D regions, ions such as arsenic (e.g. 3.0E15 cm-2 at 150 KeV, 0 degrees) and phosphorus (e.g. 5.0E14 cm-2 at 120KeV, 0 degrees) are implanted The p+S/D implant also forms the extrinsic base 72.

Next, the bipolar collector contact 76 is patterned. After the screen oxide is etched, a shallow silicon etch is performed to recess the heavily doped collector contact 76 below the base region 48. The collector side silicon etch separates the base and the heavily doped collector contact to prevent degradation of the breakdown voltage for the collector-base junction. A 1,000 angstrom TEOS layer is deposited and anisotropically etched to form a second sidewall oxide spacer 74. The bipolar collector contact 76 is then patterned and implanted with ions such as arsenic and phosphorus (optional). This pattern and implant could be combined with the MOS S/D to simplify the process. It should be noted that this structure does not use a buried layer to minimize collector resistance but accomplishes this by self-aligning the collector contact 76 to the emitter 60.

FIG. 8 shows the cross section after the S/D anneal cycle has been completed and the screen oxide has been etched. Titanium disilicide is then used to simultaneously clad all diffusions and gates. Standard multilevel metal processing completes the process flow.

The invention provides a bipolar transistor which has several advantages over prior art. (i) The disclosed design does not require that the polysilicon etch stop on single crystal silicon. (ii) The bipolar transistor is built in the same epitaxial layer as the MOSFET. (iii) This design has improved radiation stability over prior art. (iv) The parasitic capacitances are reduced because the diffusions extend down to the buried oxide such as for the extrinsic base.

Although a specific embodiment of the present invention is herein described, it is not to be construed as limiting the scope of the present invention. For example, the NPN bipolar transistor shown in the preferred embodiment could be built as a PNP bipolar transistor. Also, the preferred embodiment is described for a BiCMOS/SOI process, but the invention could be used for a bipolar/SOI process also. In addition, the process can also be used in bulk processing, rather than with the SOI process. Many embodiments of the present invention will become clear to those skilled in the art in light of the teachings of the specification. The scope of the invention is limited only by the claims appended.