Recessed Contact Bipolar Transistor and Method

"A BiCMOS Process for Forming Self-Aligned NPN Emitters and Bases and MOSFET/Source Drains", by Robert H. Havemann, Serial No. 057,871, filed June 2, 1987 and "Bipolar Transistor Fabrication Using CMOS Techniques", by David Spratt and Rajiv Shah, Serial No. 008,906, filed Jan. 30, 1987, both assigned to Texas Instruments.

The present invention relates in general to bipolar/CMOS semiconductor processing, and more specifically to the process of forming a scaled bipolar transistor structure that is compatible with the formation of CMOS structures on a single semiconductor substrate.

The challenges associated with device scaling or reducing the size of device geometries have become a focus of attention for both bipolar and MOS VLSI technologies in recent years. In addition, the integration of FET structures and bipolar transistors on a single substrate has become very desirable. Each of these technologies provides inherent advantages. Bipolar transistors provide high transconductance and, as a result, are very suitable for high speed VLSI devices. On the other hand, CMOS technology offers the advantages of low power operation and very high packing density. It has become clear that the exploitation of the high current driving capabilities of the bipolar transistor is important and that bipolar device scaling is critical to obtaining even higher levels of bipolar or merged bipolar CMOS integration.

Previous efforts to scale the geometries of the bipolar transistor have been directed to reducing the lateral dimensions of the device by photolithographically scaling the feature sizes. Using this approach, the desired breakdown voltages are typically accomplished by maintaining critical lateral spacings through appropriate adjustments in photomask pattern dimensions. By incorporating processes that include the use of polysilicon and self-alignment techniques, even further advances in performance and packing density have been realized. These improvements are largely the result of minimizing excessive parasitic extrinsic regions of the bipolar device. One recent technique to reduce the collector-base area is to self-align the emitter to the base by making direct contact to the emitter with a polysilicon layer. Polysilicon has also been used to contact the base of the transistor which has the effect of reducing the collector to base area. See, for example, Cuthbertson et al, Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI, IEEE Trans. Electron Devices, vol. ED-32, No. 2, pp. 242-247, February 1985.

Such techniques have more recently been implemented in a bipolar-based BiCMOS process which uses the second level polysilicon layer of the CMOS process to form the bipolar polysilicon emitter. This allows a small sized, shallow emitter structure without additional processing steps (see Ikeda et al, High-Speed BiCMOS Technology with a Buried Twin Well Structure, IEEE Trans. Electron Devices, vol. ED-34, No. 6, pp. 1304-1309, June 1987).

Other processes for producing multilayer bipolar and MOS structures having reduced packing density have incorporated the use of vertical or sidewall insulating layers. See for example J. Riseman U.S. Pat. No. 4,234,362, issued Nov. 18, 1980 or V.L. Rideout U.S. Pat. No. 4,085,498, issued Apr. 25, 1978.

While the above described methods have allowed ever increasing improvement in device performance and packing density, there exists a need for even further reduction in feature size that is not limited by photolithography for controlling critical dimensions between diffusions. In addition, there exists a need for improving device performance by eliminating parasitic peripheral diode effects and the level of stored charge in the collector region. Finally, it would be desirable to provide a method of producing a scaled bipolar device having the above improvements with a simplified manufacturing process that is compatible with various bulk and silicon-on-insulator isolation schemes as well as CMOS process technology.

It is therefore an object of the invention to provide a method of making a bipolar transistor that reduces the area of the transistor structure and improves the packing density of integrated circuits incorporating said transistor. It is also an object of the invention to provide a bipolar transistor having a reduced extrinsic base area with a corresponding reduction in the parasitic capacitance to improve device switching performance. It is yet another object of the present invention to provide a simplified bipolar transistor process which eliminates the need for a highly doped buried collector layer. It is still another object of the invention to provide a bipolar transistor process which improves voltage breakdown control by device scaling which is independent of photolithographic operations. An additional object of the invention is to provide a bipolar transistor that reduces the effect of parasitic emitter to base diode characteristics. Finally, it is a further object of the present invention to provide a bipolar transistor process that is (automated) layout compatible with CMOS manufacturing processes.

In accordance with the present invention there is provided a method of manufacturing a bipolar semiconductor device having reduced dimensions and improved operating characteristics while being process compatible with MOS device structures. An intrinsic base region is formed in a epitaxial layer overlying an insulator and a polysilicon layer is thereafter deposited, patterned and etched to form emitter regions. An insulating layer is formed on the upper surfaces and side walls of the polysilicon emitters to provide a first sidewall spacer. The single crystal silicon is then selectively etched through a major portion of the intrinsic base and self-aligned to the sidewall insulator covering the emitter regions. A heavily doped base contact region is then formed adjacent at least one side of the base-emitter pedestal previously formed and a second sidewall insulating spacer is formed over the base-emitter structure. The collector contact region is formed adjacent a second side of the base-emitter structure by implanting the appropriate dopant while using the second sidewall spacer as a portion of the implant mask to offset the heavily doped collector contact region from the intrinsic base. Finally, the insulating layer on the surface of the polysilicon emitter regions is patterned and etched and emitter, base contact, and collector contact regions are silicided. The device may then be processed using standard methods to provide appropriate interconnect metallization and passivation.

A technical advantage is provided in that by separating the base and collector contacts from the emitter in the vertical direction, parasitic diode action between the base and collector contacts is reduced or eliminated. A further technical advantage is the improved device switching speed resulting from the close proximity of the collector contact to the emitter which allows for a reduction in the area of the lightly doped collector and a corresponding reduction in the amount of stored charge in this region. In addition, improved device switching performance is attained by a reduction in the extrinsic base area and a resulting reduction in associated parasitic capacitances. A further technical advantage is the close spacing of collector contact and emitter regions which allows for the elimination of the heavily doped buried layer and buried layer contact which simplifies the manufacturing process. Yet another technical advantage of the present invention is the reduction in area required for the scaled bipolar transistor which greatly improves packing density allowing higher levels of device integration. Finally, an additional technical advantage is the improved breakdown voltage control resulting from a device scaling method which is independent of photolithographic limitations. Additionally, the process disclosed herein is compatible with CMOS device processing and numerous bulk and silicon isolation schemes making it ideally suitable for BiCMOS VLSI applications.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates the initial structure of a preferred embodiment of the transistor which includes an epitaxial layer overlying an oxide insulator and trenches through the epitaxial layer which are filled with insulating material for device isolation;

FIG. 2 illustrates a cross-sectional view of the isolated structure after the formation of the intrinsic base region in an upper portion of the epitaxial layer with a protective oxide layer in place;

FIG. 3 illustrates the structure after removal of the protective oxide from the active device region;

FIG. 4 illustrates a cross-sectional view of isolated base structure after the formation of oxide capped polysilicon emitter regions thereon;

FIG. 5 illustrates a cross-sectional view after the formation of a first sidewall insulator spacer on the sides of the capped emitter structure;

FIG. 6 illustrates a cross-sectional view of the active device structure after the process of selectively etching portions of the base layer to form stacked emitter-base structures in the active device regions;

FIG. 7 illustrates a cross-sectional view of the device after the implantation of the self-aligned extrinsic base.

FIG. 8 illustrates a cross-sectional view of the transistor structure after the formation of a second sidewall insulator spacer on the sides of the stacked emitter-base structure;

FIG. 9 illustrates a cross-sectional view of the device after collector contact patterning and ion implantation;

FIG. 10 illustrates a cross-sectional view of the device structure after the removal of the emitter oxide cap and the formation of a metal silicide on the base, emitter and collector silicon surfaces; and

FIG. 11 illustrates a cross-sectional view of the transistor structure after deposition, patterning and etching an interconnect insulating layer.

FIG. 12 illustrates a top view of the transistor structure.

Referring to FIG. 1, there is shown a cross-sectional view of a silicon on insulator structure that includes a semiconductor layer 10 having an overlying oxide layer 12 and an epitaxial silicon layer 20 overlying layer 12. Totally isolated epitaxial silicon islands may be formed by etching isolation trenches 26 through layers 20 and subsequently refilling these trenches by depositing an oxide or suitable insulating material 14. This method results in closely spaced epitaxial substrate regions 20 that form the active device areas. A similar structure may be fabricated by using the method disclosed in U.S. Pat. Application Ser. No. 810,001, filed Dec. 17, 1985 and entitled "Semiconductor Isolation Using Trenches and Oxidation of Anodized Silicon Sublayer". An additional description of an isolated silicon structure which would be suitable for use in the present method may be found in U.S. Pat. Application Ser. No. 806,258, filed Dec. 6, 1985 and entitled "High Definition Anodized Sublayer Boundary". The two patent applications cited above are herein incorporated by reference. It should also be noted that the bipolar transistor structure of the present invention may be formed in a silicon substrate that is not totally surrounded by insulating material. That is to say that the method need not start with a silicon on insulator active area but may begin by forming these active areas by using traditional bulk silicon isolation techniques. Such techniques may include recessed or non-recessed LOCOS isolation or various deep trench isolation methods.

Referring now to FIG. 2, the process continues by growing protective oxide layer 16 on the surface of the structure as shown in FIG. 1. This oxide may be grown to a thickness of, for instance, 120 Angstroms. Following this oxidation step, a base blocking photoresist layer 17 is deposited and patterned to define intrinsic base regions in the desired epitaxial silicon layers. Photoresist 17 is etched and Boron is implanted in the upper portion of epitaxial layer 20 to a dosage of approximately 1.5E14 at an implant energy of 60 KEV to form intrinsic base layer 21. Portions of base layer 21 will become the base region of bipolar NPN transistors to be described in detail hereinbelow.

With patterned photoresist layer 17 remaining in place, the portions of protective oxide layer 16 that cover base layer 21 are etched as is shown in FIG. 3. The photoresist layer 17 is then stripped. Referring next to FIG. 4, a layer of undoped polysilicon is deposited by using a low pressure chemical vapor deposition (LPCVD) technique. This polysilicon layer is then doped by implanting phosphorus to a dosage of approximately 2.0E16 at an implant energy of 100 KEV. Thereafter an insulating layer of oxide is deposited to a thickness of approximately 2000 Angstroms. The oxide deposition utilizes a process referred to as Tetraethoxysilane (TEOS) deposition which forms an insulator that etches at a faster rate than thermally grown oxide. Next, a layer of photoresist (not shown) is deposited and patterned to define the self-aligned polysilicon emitter structure. The TEOS layer is then selectively etched and following that operation, the polysilicon layer is etched away in those areas not covered by the remaining TEOS pattern. As shown in FIG. 4, the resulting structure includes at least one polysilicon emitter 22 formed on extrinsic base layer 21 an capped with insulating TEOS layer 15.

The process continues by depositing a insulating TEOS layer approximately 2000 Angstroms in thickness. This layer is then patterned and anisotropically etched to leave only the sidewall oxide spacer 18 on the sides of the capped polysilicon emitter structure (layers 22 and 15) as shown in FIG. 5. The sidewall oxide spacer 18 serves to "nest" the polysilicon emitter 22 by totally surrounding it with insulating material and also provides a masking material for subsequent etching steps and implantation operations.

As shown in FIG. 6, the structure is next patterned and the epitaxial silicon intrinsic base layer 21 is etched to a depth of approximately 3500 Angstroms to form contact recesses 30. The recesses etched in the silicon during this step of the process should penetrate at least a major portion of base layer 21 and will form the base and collector contact recessed regions. The resulting structure includes isolated stacked structures which have an N type polysilicon emitter 22 overlying a P type base layer 21 on an N type epitaxial silicon layer 20.

Referring now to FIG. 7, a base contact blocking resist layer 13 is formed over the structure and patterned to define base contact regions 23 in the contact recesses 30 on one side of the base-emitter stacked structure. Boron is then ion implanted at a dosage level of approximately 5.0E15 and an implant energy of 50 KEV to form the base contact regions 23 in epitaxial silicon layer 20. Note that the sidewall oxide spacer 18 on the base-emitter structure forms an appropriate implant mask during this operation and the heavily boron doped region 23 makes contact to base layer 21.

The process continues by depositing an insulating TEOS layer having a thickness of approximately 3500 Angstroms. This layer is then patterned an anisotropically etched to form a second sidewall oxide spacer 19 which covers the sides of base layer 21, sidewall oxide spacer 18 and the sides of the oxide isolation material 14 while exposing reduced area contact regions in the base-collector contact recesses 30 as shown in FIG. 8.

A layer of collector contact blocking resist 11 is next deposited and patterned to define the collector contact region 25. After etching layer 11, phosphorus is ion implanted at a dosage of approximately 2.0E16 and an implant energy of 100 KEV to form a heavily doped collector contact region 25 as shown in FIG. 9. Note that the sidewall oxide spacer 19 serves as a mask during this operation to ensure that contact region 25 is appropriately spaced from base layer 21. The structure may now be subjected to a high temperature emitter anneal process of, for example, 900 degrees centigrade for 10 to 15 minutes. From an examination of the transistor structure at this stage of the process, it can be appreciated that by the use of the silicon etch and the two sidewall oxide spacers, the active emitter is separated from the heavily doped base and collector contacts in the vertical direction allowing a reduction in overall transistor area. In addition, this is accomplished without the limitations of photolithographically defining a lateral spacing between diffusions. Moreover, the ability to space the heavily doped collector contact in close proximity to the base layer 21 provides a transistor with a low Rcs value thereby eliminating the need to incorporate a low resistance, deep collector region.

Referring next to FIG. 10, the process continues by depositing and patterning a cap oxide resist (not shown) and thereafter etching the polysilicon emitter cap oxide 15 to expose the upper surface of the phosphorus doped emitter 22. A layer of metal such as platinum having a thickness of approximately 450 Angstroms is next deposited and thereafter sintered to form metal silicide layers 32 on polysilicon emitter 22, base contact regions 23, and collector contact region 25. The portions of the platinum that do not react to form titanium disilicide are stripped using an appropriate etchant. The siliciding process is described in U.S. Pat. No. 4,545,116, which is incorporated herein by reference and will not be further described here.

As shown in FIG. 11, an oxide insulating layer 24 is next deposited on the surface of the structure and thereafter planarized to provide acceptable contours for subsequent interconnect metallization. Oxide layer 24 is then patterned and etched to form suitable contact vias 28 in the desired emitter, base and collector contact regions. A first level metal pattern of, for instance, an aluminum-titanium tungsten alloy may then be formed to make contact to the desired silicided surfaces through vias 28 and patterned/etched to form an appropriate interconnect. Additional levels of interconnect may be desirable as dictated by the complexity of the circuit design.

In summary, there has been provided a method for fabricating a scaled, self-aligned bipolar transistor. The method includes a first step of forming a shallow intrinsic base region in an isolated epitaxial silicon layer and thereafter forming oxide capped polysilicon emitters which are nested by forming a first oxide insulator on the sidewall of the emitter structure. A silicon etch is used to form recessed contact regions for base and collector contacts and the base contact is formed by a self-aligned ion implantation of a suitable dopant using the first sidewall oxide as a part of the implantation mask. A second sidewall oxide spacer is formed on the sides of the on the emitter-base stacked structure and the collector contact is formed by ion implanting into an appropriate recessed contact region a suitable dopant using the second sidewall spacer as a portion of the implantation mask. The collector contact so formed is spaced from the base by the second sidewall spacer and because this dimension may be made very small, the need for a heavily doped buried collector region is eliminated. The bipolar transistor proposed herein may be incorporated into a standard double polysilicon CMOS process flow having fewer additional photomasking steps than conventional BiCMOS processes. In addition, the bipolar transistor disclosed herein is fully compatible with silicon on insulator (SOI) technology. The presence of a buried oxide completely confines the heavily doped P-type depletion region at the silicon oxide interface which significantly reduces the extrinsic base capacitance.

Although the present invention has been disclosed and claimed herein, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims.