Current to Voltage Interface

This invention relates to a current-to-voltage interface circuit for translating the current output of a device to a logic level voltage for interfacing to a logic circuit.

In logic systems, it is often advantageous to use devices which produce outputs in the form of current, rather than voltage, signals. Transmission of current signals from one circuit to another can be accomplished with relatively small voltage levels. This reduces the potential for noise generation in the circuit due to capacitive coupling between connecting leads. This is especially important in chip-to-chip signal transmission where lead lengths are relatively long.

An example of such an application is the use of a high speed analog comparator, having current signal inputs and outputs, in an analog to digital converter (Harris Corp. part number HI574A). This comparator has an input current terminal, a reference current terminal, a strobe terminal, and first and second output current terminals. Under normal conditions, the strobe is inactive and the output stage of the comparator goes into a preferential state in which it sinks a constant current of approximately 500 microamps through the first current output, while no current flows in the second current output. When the strobe is activated, the comparator assumes one of two states: (1) if the input current is greater than the reference current, the output stage remains in the preferential state, with currents flowing in the first and second current output as stated above; (2) if the input current is less than the reference current, the output stage switches the current flows such that a constant current of approximately 500 microamps is sunk through the second current output, while no current flows in the first current output. When the strobe is active, the comparator inputs are disabled and the outputs remain in the state mandated by the condition of the inputs when the strobe was activated. When the strobe is inactive, the output stage of the comparator returns to the preferential state.

To utilize a comparator of this type in a digital logic circuit, it is necessary to translate, or convert, the described states of the current outputs to logic level voltage signals. The interface circuit must have current inputs, for connection to the current outputs of the comparator, and a logic level voltage output for interfacing to logic circuits. When the comparator is in the preferential state (i.e., current is flowing in the first current input), the interface circuit assumes a first logic level at the voltage output. If the comparator input current is greater than the reference current when the strobe is activated, the comparator remains in the preferential state and no logic level transition occurs at the interface circuit voltage output. Thus, the logic switching time delay for this condition is essentially zero. If the comparator input current is less than the reference current when the strobe is activated, a transition to a second logic level voltage will take place at the voltage output of the interface circuit in response to the switching of current flows in the current inputs. Thus, a particularly advantageous circuit for this application is one in which the logic switching time delay for the transition from the first logic level voltage to the second logic level voltage has been minimized. This can be achieved at the expense of a relatively slow second-to-first logic level transition (i.e., the circuit recovery time), since recovery to the preferential state takes place between clock pulses when the comparator/interface circuit combination is not being called upon to make a decision. As will be discussed in detail below, the interface circuit of the present invention has these advantageous features.

Accordingly, it is an object of the present invention to provide a circuit for interfacing comparators, and other devices having current signal outputs, with digital logic circuits.

Another object of the present invention is to provide an interface circuit of relatively simple design which can be implemented with a minimal number of devices in a relatively small area.

Still another object of the present invention is to provide an interface circuit wherein the switching delay for a transition from a first logic level output to a second logic level output is minimized.

A further object of the present invention is to provide a circuit with a high immunity from noise and erroneous signals when the output is in the first logic level state.

A still further object of the present invention is to provide a circuit wherein the first-to-second logic level voltage transition time and the second-to-first logic level voltage recovery time are easily adjusted by altering the relative sizes of circuit components.

These and other objects of the invention are attained by a current-to-voltage interface circuit which produces a first logic level voltage at a logic voltage output when current flows in a first current input, and which produces a second logic level voltage at the logic voltage output when current flows in a second current input. The interface circuit comprises an input stage and a logic stage. The input stage has first and second current inputs and a voltage output. The logic stage has an input connected to the voltage output of the input stage, and an output at which logic level voltages are produced. The input stage comprises a first circuit, a second circuit, and a switching device. The first circuit includes the first current input, a first current source and voltage clamping element, and a first voltage output connected to the switching device. The second circuit includes the second current input, a second current source and voltage clamping element, and a second voltage output connected at a node to the switching device and to the input of the logic stage. The switching device is connected to a voltage source and, in response to a voltage produced at the first voltage output by the first circuit, connects the voltage source to the logic stage input. Logic level voltage transitions are produced at the logic stage output in response to the voltage changes produced at the node where the logic circuit input, the second voltage output and the switching device are connected. The first-to-second and second-to-first logic level voltage transition times are adjustable by selecting first and second transistors in the first circuit such that, when both transistors are biased with the same voltage, the current established in the first transistor will be a selected multiple of the current established in the second transistor.

For a better understanding of the present invention, reference is made to the following detailed description of a preferred embodiment and the accompanying figures in which:

FIG. 1 shows the interface circuit of the present invention coupled to the current outputs of a high speed analog comparator; and

FIG. 2 shows the voltage/time wave forms at several nodes within the interface circuit of FIG. 1.

FIG. 3 shows a timing diagram which illustrates the circuit transition times relative to the strobe signal and a clock signal.

A preferred embodiment of the present invention is shown in FIG. 1. The interface circuit, generally indicated by reference numeral 10, is shown coupled to the current outputs of high speed analog comparator 14. Comparator 14 has an input terminal 16, a reference terminal 18, a strobe 20, and current outputs 22 and 24. In operation, comparator 14 compares the magnitude of the current at the input terminal 16 to a reference current at reference terminal 18. Under "normal" conditions, strobe 20 is not active and the output stage of comparator 14 goes into a preferential state in which approximately 500 microamps is sunk by current output 22, while approximately 0 microamps flows in current output 24. When strobe 20 is activated, comparator 14 can assume one of two states: (1) If the current flowing in input terminal 16 is greater than the reference current flowing in reference terminal 18, comparator 14 remains in its preferential state with approximately 500 microamps flowing in current output 22 and 0 microamps flowing in current output 24; (2) if the current flowing in input terminal 16 is less than the reference current, approximately 500 microamps is sunk by current output 24, while approximately 0 microamps flows in current output 22.

Interface circuit 10 includes an input stage, indicated generally by numeral 12, and a logic stage, indicated by numeral 13.

Current outputs 22 and 24 are coupled to input pads 23 and 25, respectively, which are also connected to current inputs 26 and 28 of input stage 12. Input stage 12 and logic stage 13 are connected to a voltage source, V.sub.L, at pad 30, and to a voltage reference, V.sub.REF, at pad 32. In the present embodiment, V.sub.L is approximately 5 volts and V.sub.REF is approximately 0 volts. Input stage 12 also has an output node 42 which is connected to the input of logic stage 13. Logic stage 13 has an output connected to pad 34 where logic level voltages are produced in response to currents flowing in current inputs 26 and 28, as will be explained in detail below.

Input stage 12 includes a first circuit which comprises current input 26, P-channel transistor 36, bipolar transistor 48, and an output voltage node 38. Input stage 12 also includes a second circuit which comprises current input 28, bipolar transistor 50, and an output voltage node 42. Input stage 12 further comprises a switching device, represented by P-channel transistor 40, which serves to connect node 42 to V.sub.L in response to a voltage produced by the first circuit at node 38.

When comparator 14 is in its preferential state (i.e., approximately 500 microamps flowing into output 22 and substantially zero current flowing in output 24), current is supplied to current input 26 by P-channel transistor 36 which is connected at its source to V.sub.L, and which is connected at its gate and drain to current input 26 at node 38. Node 38 is also connected to the gate of P-channel transistor 40. The source of transistor 40 is connected to V.sub.L, while the drain is connected to current input 28 at node 42. Node 42 is connected to the input of logic stage 13 which comprises an inverter formed by complementary transistors 44 and 46. The source of transistor 44 is connected to V.sub.L, the drain of transistor 44 and drain of transistor 46 are connected together at output pad 34, and the source of transistor 46 is connected to V.sub.REF. The gates of transistors 44 and 46 are connected together at node 42.

The remaining components making up interface circuit 12 are bipolar transistors 48 and 50. Although transistors 48 and 50 are shown as NPN devices, it should be readily apparent that PNP devices could also be used. The collectors of these transistors are connected to V.sub.L, their bases are connected to V.sub.REF, and their emitters are connected, respectively, to nodes 38 and 42 (current inputs 26 and 28). When a CMOS process is used to produce field effect transistors 36, 40, 44 or 46, transistors 48 and 50 are preferably NPN substrate transistors. When connected as shown in FIG. 1, they function as protective voltage clamps to prevent nodes 38 and 42 from being pulled below minus 0.7 volts when a sudden demand for current is made from one of the comparator outputs and as back-up (transistor 48) and primary (transistor 50) current source elements. The NPN substrate transistor produced by the CMOS process is often connected in this, or a similar fashion, to protect CMOS devices from latching-up. This problem results when the substrate is driven to a low enough potential to forward bias a substrate junction. Current flowing in this junction can remain after removal of the voltage, causing damage to the CMOS devices.

The circuit operation will now be described. When the comparator is in the preferential state, a constant current of approximately 500 microamps is demanded from current input 26, while substantially zero current flows in current input 28. The 500 microamps is supplied by transistor 36. Transistor 36 is connected as a resistor and is of sufficient size to supply the required current. It should be noted at this point, that if more current is demand from current input 26 than transistor 36 can supply, transistor 48 will supply the balance. As more current is conducted by transistor 36, the voltage drop across this transistor increases and, accordingly, the voltage at node 38 decreases. When the voltage reaches -0.7 volts, i.e., for a voltage drop across transistor 36 of 5.7 volts, transistor 48 turns on to supply the remaining current. Transistor 48 thus sets, at -0.7 volts, the minimum voltage to which node 38 can fall. Referring to FIG. 2, it can be seen that the lowest voltage to which node 38 falls in this particular embodiment is approximately 1.2 volts. Thus, under these particular circuit conditions, transistor 48 will not be called upon to supply current.

As noted, the current through transistor 36 establishes a voltage of approximately 1.2 V at node 38. This relatively low voltage turns on transistor 40 and connects node 42 to V.sub.L. No current flows through transistor 40 at this time since none is demanded from current input 28. The high voltage level at node 42 turns on transistor 46 and, thus, provides a low logic level voltage at output pad 34.

This is the state of interface circuit 10 which corresponds to the preferential state of comparator 14. The voltages at nodes 34, 38 and 42 are shown in FIG. 2 for this preferential state, which corresponds to the interval marked 54 in FIG. 2. For purposes of clarity the waveforms in FIG. 2 are marked by the number of the node represented. Of the remaining intervals, 52 indicates the recovery time from the non-preferential to the preferential state (from high-to-low logic level output voltage), 56 indicates the transition time from the preferential state to the non-preferential state (low-to-high logic level output voltage), and 58 indicates the non-preferential, or high output, state.

When the comparator changes state, current ceases to flow in current input 26 and approximately 500 microamps is demanded from current input 28. At the instant of transition, transistor 40 is turned on and its gate is biased by the voltage at node 38. Transistor 40 is selected so that, when biased at this level, preferably on a linear portion of the characteristic curve, it will supply approximately 50 microamps, or about 1/10 of that being supplied by transistor 36 whose gate is similarly biased. In short, transistor 40 is chosen to be 1/10 the size of transistor 36. Thus, at the moment of transition, approximately 500 microamps will be demanded from current input 28, and approximately 50 microamps will be available from transistor 40. The net current flowing out of node 42 (approximately 450 microamps) will be large enough to rapidly drain the capacitances associated with this node and cause the node voltage to drop rapidly. This is apparent from waveform 42, interval 56, in FIG. 2. As seen there, the voltage at node 42 continues to drop until, at approximately - 0.7 volts, transistor 50 is turned on to supply the current demanded and clamp the node voltage at this level. By selecting transistor 40 to be larger or smaller, this transition time (interval 56) can be increased or decreased, respectively.

The rapid drop in voltage at node 42 turns transistor 46 off and turns transistor 44 on producing a logic level transition at node 34 to a logic high level. The low-to-high transition at node 34 is very rapid, as can be seen in FIG. 2, while the high-to-low transition is relatively slow. This is an intentional result accomplished by increasing the size of transistor 44, relative to transistor 46, to insure that, as with input stage 12, the more rapid transition of logic stage 13 occurs when the comparator switches from the preferential to the non-preferential state.

When the comparator outputs revert to the preferential state, the interface circuit recovers as indicated by interval 52 in FIG. 2. For this preferred embodiment, the recovery time is relatively slow due to the relatively small size of transistor 40 and the correspondingly long time needed to charge the capacitances associated with node 42. This recovery time can be shortened by increasing the size of transistor 40 (which will lengthen the transition time as described above), or by decreasing the size of transistor 36 to decrease the bias voltage, and thus increase the current through, transistor 40. Thus, by adjusting the relative sizes of transistors 36 and 40, the transition time and recovery time of the input stage 12 can be altered. Similarly, adjusting the relative sizes of transistors 44 and 46 will alter the recovery time of logic stage 13.

FIG. 3 illustrates the manner in which the comparator and interface circuit combination interacts with an external circuit. Starting at the left of FIG. 3, the voltage waveforms at nodes 42 and 38 are shown with the comparator in the preferential state. The first strobe pulse occurs when the input current is presumed to be higher than the reference current and the comparator does not change states and the waveforms at nodes 38 and 42 do not change. Thus, when the external clock pulse arrives an interval of time 60 after strobe activation, a logic level low signal is present at node 38 as an input to the external circuitry. The switching delay time for the interface circuit in this case is zero.

Following time interval 62, a second strobe pulse occurs. Assuming the current in input terminal 16 is less than the reference current, a change of state will result. Time interval 64 represents the time necessary for the comparator to react to the strobe signal, and time interval 66 represents the interface circuit transition time (time interval 66 in FIG. 3 corresponds to time interval 56 in FIG. 2). As can be seen, the transitions at nodes 38 and 42 occur before the arrival of the clock pulse represented by interval 68. Recovery to the preferential state occurs in the relatively long time interval 70. Thus, the strobe and clock pulses, along with the circuit noise they are capable of producing, are confined to relatively brief intervals, separated by longer, relatively quiet intervals represented by 62 and 70 in FIG. 3. Since recovery to the preferential state occurs in these relatively long intervals, the circuit can be designed to optimize the speed of the preferential-to-nonpreferential transition, thus, optmizing the overall decision making speed of the circuit.

Although this invention has been described and illustrated in detail, it is to be clearly understood that this description is not to be taken by way of limitation. The spirit and scope of the invention are to be limited only by the terms of the appended claims.