Analog to Digital Interface Circuit

The subject matter of the subject invention is related to the subject matter of an application entitled "Current Ramping Controller Circuit", Ser. No. 166,866 by Jarrett et al filed concurrently herewith which is assigned to Motorola, Inc.

1. Field of the Invention

The present invention relates to interface circuits and more particularly to an interface circuit for providing a set and reset pulse to an Integrated Injection Logic (I.sup.2 L) latch circuit in response to an analog signal provided thereto.

2. Description of the Prior Art

There are many interface circuit applications requiring ramping capacitor time generators for supplying digital output signals therefrom. An example for such an application is in electronic ignition systems. In some contemporary electronic ignition systems, in response to a timing signals generated in timed relationship to the operation of the engine, there is provided a series of firing command signals for creating spark to operate the engine. The ignition systems usually require at least one and usually more than one capacitor to be ramped up and down, as understood, to generate the aforementioned firing command signals. For example, U.S. Pat. No. 4,041,912 to Charles Session, assigned to Motorola Inc., shows the need of such ramping capacitors and ramping circuits. The ramping capacitor may be clamped at upper and lower voltage levels in order to derive a delayed, well defined rectangular square wave output which is utilized to generate the foregoing firing command signals. In an electronic ignition system incorporating the embodiment of the present invention, the upper and lower capacitor voltage clamp levels are utilized to drive an I.sup.2 L latch circuit for providing the aforementioned rectangular output square wave. However, I.sup.2 L latches generally do not have immunity to noise induced input signals thereto.

Thus, there is a need for an interface circuit responsive to capacitor upper and lower voltage clamp levels for providing inputs to an I.sup.2 L latch circuit while providing high noise immunity.

Accordingly, it is an object of the present invention to provide an interface circuit for providing set and reset commands to an I.sup.2 L latch while providing high noise immunity.

It is another object of the invention to provide an interface circuit for utilization in an electronic ignition system.

In accordance with the foregoing and other objects there is provided an interface circuit for providing set and reset command signals at first and second outputs thereof which can be utilized to drive an I.sup.2 L latch circuit in response to an analog signal supplied thereto. The interface circuit comprises a first circuit having first and second inputs which is responsive to an input signal applied to the first input thereof exceeding a reference signal supplied at the second input thereof for providing a first output signal that is compatible for driving an I.sup.2 L latch circuit, for instance. The interface circuit further includes a second circuit having first and second inputs and an output which is responsive to the input signal supplied to the first input thereof becoming less than a second reference potential supplied to the second input thereof for providing an output signal at the output thereof which can be used to drive an input of the I.sup.2 L latch circuit.

In one feature of the invention the outputs from the first and second circuits provide for setting and resetting the I.sup.2 L latch circuit.

FIG. 1 is a schematic diagram of the preferred embodiment of the invention; and

FIG. 2 is a waveform useful for explaining the operation of the invention of FIG. 1.

Turning to the figures there is shown interface circuit 10 of the present invention which provides first and second output signals at output terminals 14 and 16 respectfully that may be utilized to set and reset Integrated Injection Logic (I.sup.2 L) latch circuit 12. As shown, interface circuit 10 is responsive to capacitor 18 being charged and discharged between two levels to supply the foregoing set and reset signals however it is to be understood that any other analog signal of the same form could be utilized. Capacitor 18 is charged at a rate proportional to the current I supplied through current source 20 when switch S1 is closed. Alternately, capacitor 18 is discharged at a rate proportional to the current I sunk by current source 22 whenever switch S2 is closed. Capacitor 18, which may be a discrete capacitor, is connected to the current ramping controller circuit comprising current sources 20 and 22 at node 24. The current ramping controller circuit along with interface circuit 10 and I.sup.2 L latch circuit 12 are suitable to be manufactured in integrated circuit form, as is understood, with interface circuit 10 being shown included within the dashed outline. The current ramping controller circuit insures that capacitor 18 is charged and discharged at the same proportional rate. Any such circuit can be utilized in the present invention with one type of current ramping controller circuit being shown by the aforereferenced Jarrett et al patent application which is incorporated herein by reference. As shown in FIG. 1, current source 20 is connected between a power supply conductor 26 which is adapted to receive a source of operating potential V.sub.cc and node 28 which serves as an input to interface circuit 10. A first circuit including transistors 30 and 32 is provided for providing an output signal at terminal 14 whenever the voltage level appearing across capacitor 18 becomes substantially equal to or greater than the value of the reference potential level, V.sub.1, provided at the base of transistor 30. The collector of transistor 30 is connected to power supply 26 with the emitter thereof being coupled through resistor 34 to a terminal at which is supplied a ground reference potential, as understood a current source may replace resistor 34. The emitter of transistor 30 is also connected to the base of PNP transistor 32 with the emitter of the latter being connected to node 28. Transistor 32 is shown as being a multicollector transistor having collectors 32A and 32B. It should be understood that transistor 32 could be a single collector transistor wherein collector 32A would not be connected to the ground reference potential but rather as shown single collector 32B would be connected to output terminal 14. Resistor 36 is shown connected between output terminal 14 and the ground reference potential across which the output signal from the subject circuit is produced. In operation then, the reference potential level supplied at the base of transistor 30 is translated down by the base-to-emitter voltage drop of transistor 30 and then is translated up by the base-to-emitter voltage drop of transistor 32 whereby the voltage level at node 28 must become substantially equal to or greater than the reference potential level V.sub.1 before transistor 32 is rendered conductive. When transistor 32 is rendered conductive the output signal is generated across resistor 36 and appears at output terminal 14.

Similarly, a second circuit is shown comprising transistors 40, 42 and 46 which produces an output signal at output terminal 16 across resistor 48 whenever the voltage level appearing across capacitor 18, at node 38, becomes substantially equal to or less than the magnitude of the reference potential level V.sub.2 supplied at a second input, the base of PNP transistor 40. The collector of transistor 40 is connected to the ground reference potential with the emitter coupled both to the base of NPN transistor 42 and current source 44; current source 44 is returned to power supply conductor 26. Although not shown it is realized that a resistor could be substituted for current source 44. The emitter of transistor 42 is coupled to node 38 and serves as a first input to this circuit, the collector is coupled both to the base and collector 46B of PNP multicollector transistor 46. The emitter of transistor 46 is returned to power supply conductor 26 with the collector 46A being connected to output terminal 16. As will be explained hereafter, the collector areas of 46A and 46B are ratioed with respect to one another wherein the area of collector 46A is equal to the dimension A and the area of collector 46B being equal to a constant, k, times the area A. In the preferred embodiment, with transistor 32 being a multicollector transistor with each collector thereof having an equal area, the constant k of transistor 46 would be equal to 2.

In operation, the reference potential level V.sub.2 is first translated down and then translated up through the emitters of transistors 40 and 42 accordingly, such that transistor 42 is rendered conductive only when the magnitude of the voltage level appearing across capacitor 18 becomes less than the value of V.sub.2. When transistor 42 becomes conductive, transistor 46 is rendered conductive wherein the current supplied via transistor 46 produces the output drive signal across resistor 48 at terminal 16. Thus, the voltage magnitude appearing across capacitor 18 is clamped between the reference levels V.sub.1 and V.sub.2 as shown by waveform 58 of FIG. 2.

A significant aspect of the foregoing described operation of the preferred embodiment of the present invention is that whenever the voltage magnitude appearing across capacitor 18 is between the two reference levels V.sub.1 and V.sub.2, interface circuit 10 is in a nonconductive state, i.e., the two circuits aforedescribed are biased in an off condition such that interface circuit 10 provides noise immunity between capacitor 18 and the inputs of I.sup.2 L latch circuit 12.

I.sup.2 L latch circuit 12 shown in logic form is generally known in the art and comprises NPN inverted transistor type devices 50 and 52 coupled with NAND gates 54 and 56. The output of NAND gate 54 provides the Q output of the latch circuit with the Q output thereof being provided at the output of NAND gate 56. Thus, the output signal generated at output terminal 14 of interface circuit 10 acts as a set signal to the latch circuit 12 forcing the Q output thereof to go high. Similarly, the high output signal generated at output 16 of interface circuit 10 corresponds to a reset signal such that the Q output of latch circuit 12 is forced high. Hence, in response to capacitor 18 being charged and discharged between voltage reference levels V.sub.1 and V.sub.2, a well defined rectangular pulse is generated at the outputs of latch circuit 12 which is delayed in time by a predetermined and fixed interval from the ramping and discharging of capacitor 18.

Hence, what has been described above is an analog to logic interface circuit for providing good noise immunity to the logic circuit. In response to the analog signal there is generated a well defined rectangular pulse at the output of the logic circuit which is delayed a predetermined and fixed time interval from the applied analog signal to the interface circuit.