US 4,500,849 AGrant
Low Noise Power Amplifier Circuit
Issue Date:1985-02-19
•3 Claims
•2 Drawing Sheets
Abstract
A low noise power amplifier in which a buffer including a field effect transistor coupled in a source follower configuration is interposed between a voltage amplifying stage and a power amplifying stage, the latter utilizing a single-ended push-pull emitter follower configuration. A cascode transistor is cascade connected with the field effect transistor. A constant current source is provided for supplying current to the source of the field effect transistor. Field effect transistor buffers are preferably provided between the voltage amplifying stage and both positive and negative amplifying portions of the power amplifying stage.
Metadata
Assignee
- Pioneoer Electronic Corporation
Inventor
- Kazuaki Nakayama
Application Information
Application Number:US 463764&
Filing Date:1983-02-04
Priority Date:1982-02-05
Art Unit:252
Classifications
IPC:
H03F 316H03F 326
Field of Search:
330264;269;273;277;300;310;311;156
Patent Drawings (2 sheets)
Description
Background of the Invention
The present invention relates to an amplifier circuit. More particularly, the invention relates to an amplifier circuit having an output power amplifying stage having transistors connected in an SEPP (Single-Ended Push-Pull) emitter follower configuration.
An amplifier circuit having a power amplifying stage of the Class B SEPP type employing an emitter follower configuration and utilizing bipolar transistors has been known. This circuit suffers from a problem of distortion in the output signal due to the output stage of the circuit operating as an emitter follower circuit. The reasons for this will be described in detail with reference to FIG. 1.
Assuming that the base current of the emitter follower transistor Q.sub.1 is represented by i.sub.b, the base-emitter voltage of the transistor Q.sub.1 is represented by V.sub.BE, and the current amplification factor thereof is represented by h.sub.fe, the following equation may be written:
where, e.sub.o and e.sub.i represent output and input voltages of the circuit, respectively, and R.sub.g represents its input resistance. Since i.sub.b may be expressed as: ##EQU1## equation (1) can be rewritten in the form: ##EQU2##
From this equation, it is apparent that the factors which can contribute to distortion of the output e.sub.o are nonlinearities in the terms V.sub.BE and h.sub.fe. In equation (3), V.sub.BE cannot be zero, but the righthand term of the denominator can theoretically be reduced to zero by making the input resistance R.sub.g =0. However, it is of course impossible to realize R.sub.g =0, and in an ordinary SEPP circuit, a relation of: ##EQU3## holds. Any attempt to realize R.sub.g <<R.sub.L (1+h.sub.fe) by, for instance, increasing the number of stages in a Darlington circuit has the restriction that the output load impedance R.sub.L of the circuit will be made very low. As a consequence, the output of the SEPP circuit of the emitter follower type is most strongly distorted by nonlinearities in the term h.sub.fe. Hence, elimination of such distortion has been strongly desired.
The input impedance Z.sub.i of an emitter follower circuit can be expressed as:
where, h.sub.ie represents the input resistance of the transistor Q.sub.1 with the emitter grounded. The principal factors which can cause distortion of Z.sub.i are h.sub.ie and h.sub.fe. Although h.sub.ie varies with current, the impedance Z.sub.i is principally defined by R.sub.L and h.sub.fe since h.sub.ie <<R.sub.L (1+h.sub.fe). Among these, h.sub.fe is nonlinear as described above, and in a case where an actual load such as a loudspeaker is utilized as R.sub.L, the input impedance Z.sub.i inevitably exhibits not only a significant nonlinearity, but also a wide phase variation. Since the input impedance Z.sub.i acts as a load on the preceding stage of the overall circuit, variations of the input impedance Z.sub.i cause severe distortion in the preceding circuit. Furthermore, if negative feedback is used in the circuit, the transient characteristics of the circuit are degraded.
Accordingly, an object of the present invention is to provide an amplifier circuit in which distortion present in an ordinary SEPP circuit of the emitter follower type is minimized, and undesirable effects of the load R.sub.L on the input impedance Z.sub.i of the SEPP circuit are eliminated, thereby improving the transient response characteristics of the circuit.
Summary of the Invention
In accordance with these and other objects of the invention, there is provided an amplifier circuit including a buffer amplifier composed of one or more field effect transistors connected in a source follower configuration provided between a voltage amplifier stage and an emitter follower type SEPP power amplifier stage. The buffer preferably includes a cascode transistor which is cascode connected with the field effect transistor. The buffer may further include a constant current source which supplies current to the source of the field effect transistor.
Brief Description of the Drawings
FIG. 1 is a circuit diagram used in explaining the reasons for distortion in a prior art emitter follower circuit; and
FIGS. 2 and 3 are circuit diagrams of preferred embodiments of amplifier circuits of the present invention.
Description of the Preferred Embodiments
The invention will now be described in detail with reference to the accompanying drawings.
FIG. 2 is a schematic diagram of a preferred embodiment of an amplifier circuit of the present invention. In this diagram, reference numeral 1 designates a voltage amplifying stage which operates in a Class A mode, and reference numeral 3 designates a power amplifying stage of the Class B type composed of complementary bipolar transistors Q.sub.2 through Q.sub.5 connected in an SEPP configuration. More specifically, NPN transistors Q.sub.2 and Q.sub.3 and PNP transistors Q.sub.4 and Q.sub.5 are connected in Darlington pairs, with the emitter follower outputs of the transistors Q.sub.3 and Q.sub.5 driving a load such as a loudspeaker (not shown) in a push-pull manner through resistors R.sub.1 and R.sub.2. A resistor R.sub.3 is further provided between the emitters of the transistors Q.sub.2 and Q.sub.4, and a biasing diode D.sub.1 is connected between the bases of the transistors Q.sub.2 and Q.sub.4.
Reference numeral 2 designates a source follower buffer circuit implemented with FETs (Field Effect Transistors). In this circuit, the source output of an N-channel FET Q.sub.6 is connected to drive the base of the transistor Q.sub.2, and the source output of a P-channel FET Q.sub.7 is connected to drive the base of the transistor Q.sub.4. The output of the voltage amplifying stage 1 is applied across the gates of the FETs Q.sub.6 and Q.sub.7 through resistors R.sub.7 and R.sub.8. A resistor R.sub.6 is connected between the gates of Q.sub.6 and Q.sub.7, and a bias diode D.sub.2 is connected between the input terminals of the resistors R.sub.7 and R.sub.8 for supplying bias voltages to the transistors Q.sub.2 through Q.sub.5 and the FETs Q.sub.6 and Q.sub.7.
An NPN transistor Q.sub.8 and a PNP transistor Q.sub.9 are connected between the drain of the transistor Q.sub.6 and the positive terminal of the power supply and between the drain of the transistor Q.sub.7 and the negative terminal of the power supply, respectively, in a cascade manner. Constant current sources I.sub.1 and I.sub.2 are provided to cause constant currents to flow through resistors R.sub.4 and R.sub.5 and also the diode D.sub.1. The voltages thereby developed across the resistors R.sub.4 and R.sub.5 are applied to the bases of the cascade transistors Q.sub.8 and Q.sub.9, respectively.
With the above-described construction of the amplifier circuit, the source follower operation of the FETs Q.sub.6 and Q.sub.7 permits direct application of the output voltage from the voltage amplifying stage 1 to the bases of the transistors Q.sub.2 and Q.sub.4 of the power amplifying stage 3, thus providing an SEPP operation similar to that of the conventional circuit. However, since the FETs theoretically have a current amplifying factor of zero, the distortion component related to the h.sub.fe term, which caused the greatest part of the total distortion in the prior art circuit discussed above with reference to FIG. 1, is substantially completely eliminated. Furthermore, since the input impedance of the buffer circuit 2 as seen from the voltage amplifying stage 1, which is the input impedance of the FET buffer circuit, is extremely high, the buffer 2 is not affected by variations of the load R.sub.L as was the circuit of FIG. 1. Moreover, the presence of the buffer circuit 2 does not adversely affect the operation of the voltage amplifying stage 1, so that stable operation thereof as a negative feedback circuit is assured.
Furthermore, since the FET buffer circuit 2 has a cascade construction, it retains the merits of the earlier cascode amplifier, thus providing very desirable characteristics for the amplifier circuit. Particularly, the voltages V.sub.DS between the drains and sources of the FETs Q.sub.6 and Q.sub.7 are maintained at values equal to the voltage drops across the resistors R.sub.4 and R.sub.5 due to the constant current sources I.sub.1 and I.sub.2, respectively (neglecting the V.sub.BE drops of the transistors Q.sub.8 and Q.sub.9), and hence the operation of the FETs Q.sub.6 and Q.sub.7 is made extremely stable.
In the circuit of this embodiment, however, constant current sources I.sub.1 and I.sub.2 must be provided for supplying current through the resistors R.sub.4 and R.sub.5. Therefore, a diode (D.sub.1) must be connected between the resistors R.sub.4 and R.sub.5. This inevitably increases the number of the elements (PN junctions) of the diodes D.sub.1 and D.sub.2, which are multiple junction devices. In addition, such a construction entails a drawback in it being difficult to maintain the currents flowing through the FETs Q.sub.8 and Q.sub.9 at constant values.
The circuit shown in FIG. 3 eliminates such difficulties. In FIG. 3, components similar to those seen in FIG. 2 are designated by like reference numerals.
In FIG. 3 a FET buffer circuit 2 is composed of a P-channel FET Q.sub.10, the source of which is connected to the base of a transistor Q.sub.2, and an N channel FET Q.sub.11, the source of which is connected to the base of a transistor Q.sub.4. As cascade transistors for the two FETs Q.sub.10 and Q.sub.11, a PNP transistor Q.sub.12 and an NPN transistor Q.sub.13, respectively, are provided. The collector of the transistor Q.sub.12 is connected to the negative terminal of the power supply, while the collector of the transistor Q.sub.13 is connected to the positive terminal. Constant current sources I.sub.1 and I.sub.2 are also provided for supplying current to the sources of the FETs Q.sub.10 and Q.sub.11 through source resistors R.sub.9 and R.sub.10, respectively. Portions of the currents supplied from the constant current sources I.sub.2 and I.sub.1 are applied to the bases of the cascode transistors Q.sub.12 and Q.sub.13, respectively. The output signal of the voltage amplifying stage 1 is directly applied across the gates of the two FETs Q.sub.10 and Q.sub.11. The construction of the remainder of the circuitry shown in FIG. 3 is similar to that of FIG. 2.
The circuit of FIG. 3 has the same advantageous characteristics as the circuit shown in FIG. 2. In addition, the circuit of FIG. 3 exhibits further advantageous features such as the operation thereof being stable because the source currents of the FETs Q.sub.10 and Q.sub.11 are determined by the currents from the constant current sources I.sub.1 and I.sub.2 and the circuit having a current limiting characteristic because an output current of no more than h.sub.fe (of the output transistor) multiplied by the current output I.sub.o of the constant current sources I.sub.1 and I.sub.2 flows through the output transistors when the output terminals of the circuit are short-circuited. Furthermore, there is another advantage of not requiring the multiple junction diode D.sub.1 which is essential to the circuit of FIG. 2.
As described above, according to the present invention, output distortion of the SEPP circuit is minimized, and adverse effects of a load to the preceding stage are eliminated regardless of the amount of the load. As a consequence, a negative feedback amplifier circuit having very little distortion, a stable operation, and good transient characteristics is obtained. Furthermore, since the circuit has a current limiting characteristic, no additional overcurrent protecting circuit is required, and the construction of the circuit is much simplified.
Claims
I claim:
1. A low noise power amplifier circuit comprising: an NPN first transistor having a collector connected to a positive terminal of a power supply; a first resistor coupled between an emitter of said first transistor and an output terminal; a PNP second transistor having a collector connected to a negative terminal of said power supply; a second resistor connected between an emitter of said second transistor and said output terminal; an NPN third transistor having a collector connected to said positive terminal and an emitter connected to a base of said first transistor; a PNP fourth transistor having a collector connected to said negative terminal and an emitter connected to a base of said second transistor; a third resistor connected between said bases of said first and second transistors; an NPN fifth transistor having a collector connected to said positive terminal; a first constant current source connected between said positive terminal and a base of said fifth transistor; a fourth resistor connected between said base of said fifth transistor and a base of said third transistor; a PNP sixth transistor having a collector connected to said negative terminal; a second constant current source connected between said negative terminal and a base of said sixth transistor; a fifth resistor connected between said base of said sixth transistor and said base of said fourth transistor; a first multi-junction diode connected between said bases of said third and fourth transistors; an N-channel FET seventh transistor having a drain connected to an emitter of said fifth transistor and a source connected to said base of said third transistor; a P-channel FET eighth transistor having a drain connected to an emitter of said sixth transistor and a source connected to said base of said fourth transistor; a sixth resistor connected between gates of said seventh and eighth transistors; a voltage amplifier having positive and negative outputs; a seventh resistor connected between said positive output of said voltage amplifier and said gate of said seventh transistor; an eighth resistor connected between said negative output of said voltage amplifier and said gate of said eighth transistor; and a second multi-junction diode connected between said positive and negative outputs of said voltage amplifier.
2. A low noise power amplifier circuit comprising: an NPN first transistor having a collector connected to a positive terminal of a power supply; a first resistor connected between an emitter of said first transistor and an output terminal; a PNP second transistor having a collector connected to a negative terminal of said power supply; a second resistor connected between an emitter of said second transistor and said output terminal; an NPN third transistor having an emitter connected to said positive terminal and a collector connected to a base of said first transistor; a PNP fourth transistor having a collector connected to said negative terminal and an emitter connected to a base of second transistor; a third resistor connected between said bases of said first and second transistors; a PNP fifth transistor having a collector connected to said negative terminal; an NPN sixth transistor having a collector connected to said positive terminal; a first constant current source connected between said positive terminal and a base of said sixth transistor; a second constant current source connected between said negative terminal and a base of said fifth transistor; a P-channel FET seventh transistor having a drain connected to an emitter of said fifth transistor and a source connected to a base of said third transistor; a fourth resistor connected between said base of said sixth transistor and said base of said third transistor; an N-channel FET eighth transistor having a drain connected to an emitter of said sixth transistor and a source connected to the base of said fourth transistor; a fifth resistor connected between said base of said fifth transistor and said base of said fourth transistor; a voltage amplifier having positive and negative outputs, said positive output being connected to a gate of said seventh transistor and said negative output being connected to a gate of said eighth transistor; and a multi-junction diode connected between said positive and negative outputs of said voltage amplifier.
3. A low noise power amplifier circuit comprising: a voltage amplifying stage; a power amplifying stage of a single-ended push-pull type having driver output transistor pairs connected in an emitter follower configuration; a field effect transistor coupled in a source follower configuration for coupling an output of said voltage amplifying stage to an input of said power amplifying state; a cascade transistor cascade connected with said field effect transistor; and a constant current source for supplying a constant current to a source of said field effect transistor; wherein one said field effect transistor, cascade transistor and constant current source is provided for each of positive and negative polarity portions of said power amplifying stage.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4390852 | 1983-06-01 | Addis |