Apparatus for Efficient Use of a Microprocessor to Control Thyristors

The present invention relates to gating control systems for an array of thyristors in general, and more particularly to static controlled converter systems embodying such a gating control system.

Firing of thyristors in a polyphase converter system involves sequential selection of a thyristor to be fired, and proper timing with respect to the applied AC power supply, in order to establish a firing delay angle which determines a predetermined converter system output.

The firing of thyristors is caused by a pulse generator outputting a hard pulse triggered in accordance with both a signal reference which is representative of the intended delay angle and a time signal which is representative of the electrical angle on the fundamental wave of the AC power supply.

It is known to use digital techniques for the generation, in relation to the fundamental AC supply voltage, of a time wave reference and for the logic selection of the thyristor "next" to be fired. See for instance U.S. Pat. Nos. 4,017,744 of F. O. Johnson and 4,173,722 of R. L. Detering. The prior art, however, uses hardwired logic as opposed to numerical techniques for the generation of the time wave reference signal, which may be digital or analog in nature, and for the comparison between time wave reference signal and delay angle reference signal, the latter which may also be either analog or digital in nature.

With the advent of microprocessing, solid state motor drives have evolved in which a microprocessor is at the center of the system regulation and control. See for instance "Adjustable Speed AC Drives-A Technology Status Review" by Bimal K. Bose IEEE Proceedings Vol. 70, No. 2, February 1982, pp. 116-135.

The present invention resides in method and apparatus for the determination of the delay angle in a thyristor pulse generator and for the controlled firing of thyristors in a polyphase static converter system with such method and/or apparatus.

While the use of microprocessing techniques in a solid state motor drive is known, the present invention takes advantage of the availability of a microprocessor in such a motor drive to effect thyristor control accessorily with the other microprocessor control operations in the motor drive, in contrast to multi-microprocessor control.

The gating control system according to the invention triggers the firing of the thyristors of an array hooked upon the AC power supply in accordance with a countdown effected from a preset value calculated by a microprocessor and defining by anticipation the time interval running until the firing event. The calculation is performed in relation to a master counter synchronized with the fundamental AC power wave and to individual numerical ramps derived therefrom in relation to each thyristor-related AC phase line. The microprocessor main tasks are interrupted after thyristor firing to allow calculation and counter presetting for a given delay angle regarding the thyristor "next" to be fired.

FIG. 1 is a six-pulse 3-phase AC/DC converter as can be used with the gating control system according to the invention;

FIGS. 2A and 2B are vectorial representations of the phase-to-neutral and the interphase voltages of the bridge of FIG. 1;

FIG. 3 shows with curves delay angle control of the thyristors of FIG. 1 by the ramp interception method according to the prior art;

FIG. 4 is a block diagram of the firing control system according to the invention;

FIG. 5 shows the master ramp and the auxiliary ramps derived therefrom by microprocessing according to the invention in the illustrative situation of FIG. 1;

FIG. 6 illustrates with curves the time relationship between the counts, microprocessor interrupts and gating instants in the firing control system of FIG. 4;

FIG. 7 is a firing circuitry as can be used for the firing circuits associated with the thyristors of FIG. 1 and the block diagram of FIG. 4;

FIG. 8 is a functional block diagram of the hardware that can be used with the microprocessor of FIG. 4;

FIG. 9 illustrates the organization of one printed board circuit like those multiplexed in the block diagram of FIG. 8;

FIG. 10 is illustrative of the SYNC pulse circuitry that can be used with the block diagram of FIG. 8;

FIG. 11 shows with curves the timing relationship between the SYNC pulse and the line voltages;

FIG. 12 is illustrative of a numerical relationship between the auxiliary ramps for delay angles ranging from 0.degree. to 180.degree.; and

FIG. 13 is a chart indicating the tasks and their timing as they occur during one cycle delineated by two successive thyristor firing instants.

Referring to FIG. 1, a bridge comprised of six-thyristors TH.sub.1 -TH.sub.6 is connected between DC output terminals +T.sub.A, -T.sub.B such that nodal points R, S, T between pairs of thyristors (TH.sub.1, TH.sub.4), (TH.sub.3, TH.sub.6), (TH.sub.5, TH.sub.2) respond to phase lines A, B, C of a three-phase AC power supply. For instance, phase A is at a voltage V.sub.AN to neutral and there is an interphase voltage V.sub.AB between phases A and B. The output of the bridge is V.sub.O, which includes a ripple due to the phase succession and the notch caused by the delay angle. The DC output is V.sub.DC beyond the filtering combination of a series combination of an inductance L.sub.1 and a parallel capacitor C.sub.1. The output current is I.sub.DC.

Curves V.sub.AB, V.sub.CB and V.sub.AC under (a) in FIG. 3 are the interphase voltages at the input of the converter bridge. The vectorial relation is shown in FIGS. 2A, 2B. The phase-to-neutral voltages V.sub.AN, V.sub.BN, V.sub.CN are, clockwise, successive vectors at 120.degree. to one another. The interphase voltages V.sub.AB, V.sub.AC, V.sub.BC, V.sub.BA, V.sub.CA and V.sub.CB are, clockwise, successive vectors at 60.degree. to one another. The corresponding curves are shown in succession under (a) in FIG. 3. When thyristors TH.sub.1 and TH.sub.6 are concurrently conductive, the voltage V.sub.o indicated in solid line appears between phases A and B, e.g. under voltage V.sub.AB. This situation is illustrated by curves (b) which indicate the periods of conduction of thyristor TH.sub.1 -TH.sub.6. NC are the intersecting points between successive curves V.sub.AB, V.sub.AC, V.sub.BC which are the natural commutation points, e.g. for zero delay angle.

When the operative point is on curve V.sub.CB, for instance, while thyristors TH.sub.5 and TH.sub.6 are conductive, at terminals +T.sub.A, -T.sub.B appears a voltage V.sub.o derived from nodes S and T. Thus, V.sub.o =V.sub.CB. If firing of thyristor TH.sub.1 is delayed by an angle .alpha., as shown in FIG. 3, the operative point goes beyond natural commutation point NC, following the solid line there beyond. When TH.sub.1 is fired, it commutates thyristor TH.sub.5 OFF, and output terminals +T.sub.A, -T.sub.B are now drawing from nodal points R and S, whereby V.sub.o has become V.sub.AB while thyristors TH.sub.1 and TH.sub.6 are concurrently conducting. The average of V.sub.o is V.sub.DC outputted by filter L.sub.1 C.sub.1, as shown in dotted line. The maximum value of the output voltage V.sub.DC occurs for .alpha.=0, e.g. when the firing instant t.sub.i is coinciding with the natural commutation time instant t.sub.o, from one thyristor to the next. The amplitude of delay angle .alpha. depends upon the size of a reference signal v.sub.c which defines the intersection with a time wave reference which may be a cosine wave when using the cosine wave crossing control principle (B. R. Pelly "Thyristor Phase-Controlled Converters and Cycle Converter" chapter 10, p. 249), or a ramp, as illustrated by curves (c) of FIG. 3. The ramps (R.sub.1 -R.sub.6) of FIG. 3 define a range of 180.degree. for angle .alpha., each ramp being at 60.degree. to the next.

In the known analog implementation of the ramp interception method, the natural commutation points NC are detected via a zero-crossing detector circuit and each analog ramp is started in coincidence with such NC point. The ramp is reset after 180.degree. electrical degrees. A common reference level R,.sub..alpha. defined by the reference signal v.sub.c representative of the desired delay angle, is established on the ramp by comparison. The corresponding thyristor is gated upon such interception and typically maintained in conduction for 120.degree.. End stops are implemented by applying a lower and upper limit to the range of variation of v.sub.c. See for instance U.S. Pat. No. 4,028,609 of R. L. Detering.

It is known to generate with a digital counter a discrete time representation of the electrical degrees running along the fundamental wave, and to logically derive therefrom successive digital ramps affected to the respective thyristors to be fired in succession. Each individual ramp is converted to an analog ramp for comparison purpose with the delay angle reference signal v.sub.c. See for instance U.S. Pat. Nos. 4,017,744 of F. O. Johnson and 4,028,609 of R. L. Detering.

It is now proposed to implement both the ramp generating function and the signal comparison function with the assist of a microprocessor. For such implementation the time reference interception method must be performed with numerical means, e.g., the signals converted to numbers are to be processed via arithmetic, logical and relational operations by the registers inside the processor. The first approach conceivable is to duplicate each of the steps known in the analog approach of the prior art and perform them by numerical means via a microprocessor. Ramps will be reproduced by periodically incrementing data memory locations. The reference signal v.sub.c will be digitized and the comparison performed digitally for each ramp. The state of one of the six output lines at a selected port will be changed once the interception has been detected, thereby causing a corresponding thyristor to be gated.

This approach, however, is objectionable and impractical for two reasons:

First, the processor must be continuously busy keeping track to check whether the interception has been reached. Since the variations of the controlling signal v.sub.c are unpredictable, the intersecting point R.sub..alpha. must be tracked constantly and the processor has to remain on a standby to initiate gating almost at any moment, while comparisons between a ramp and R.sub..alpha. are being performed routinely, most of the time. Therefore, the processor is unavailable for other tasks requiring processor use.

Another problem lies in the fact that performing a comparison involves the performance of many processor instructions. This is time consuming. The time it takes determines the resolution within which the delay angle is ascertained. Unless a very fast processor is called for, the achievable resolution is unsatisfactory for many applications in practice.

For these reasons a mere numerical transposition of the analog "ramp interception" gating method is not used. Instead, microprocessor-based gating approaches encountered in the prior art burden the system with hardware such as counters, registers, gates, flip-flops, . . . which are provided externally of the microcomputer in order to implement the gating function under proper supervision by the microprocessor. It is highly desirable to eliminate such hardware.

FIG. 4 is a block diagram illustrating the operation of the microprocessor in terms of the SYNC signal, the delay angle signal reference v.sub.c and the firing sequence to the driven circuits of the thyristors. The central processing unit involves a microprocessor including program memory and data memory. A first timer T.sub.1 in the form of a down-counter is programmed to be reset to an initial count upon each occurrence of a SYNC pulse and to proceed with a count-down between consecutive SYNC pulses. The initial count of T.sub.1 is set via software to be such that the timer reaches the terminal count, i.e. zero, at the instant the reset SYNC pulse is generated. Thus, the contents of timer T.sub.1 can be represented by a descending ramp R* as shown in FIG. 5. The SYNC pulse is derived on line 2 from a SYNC circuit SC responsive to the line voltage on line 1. The SYNC circuit detects the zero-crossings of the line voltage and generates a pulse on each such occurrence, as shown in the afore-mentioned Johnson and Detering patents. The SYNC pulse is coincident with one of the six NC points of FIG. 3, and thus exhibits the same periodicity as one of the AC lines (typically 60 Hz). The delay angle .alpha. is determined by a reference voltage signal v.sub.c appearing on line 5. Such voltage signal is converted into a binary signal by an analog-to-digital converter 6. The binary value R.sub..alpha. is supplied via line 7 to the CPU.

The CPU periodically reads the value of R* on the master ramp from line 3. Through simple arithmetic operations such readings are converted by the CPU so as to indicate counts on six secondary ramps R.sub.1 -R.sub.6 of same slope and same initial maximum count. These ramps which are shifted each by 1/6 of the period of the master ramp, e.g. 1/6 of the time interval between two consecutive SYNC pulses. The delay angle .alpha. is counted from the front edge of each secondary ramp, e.g. from one of the NC points such as shown on FIG. 3, until the count has become equal to R.sub..alpha., the reference value.

Expressing the parallel translation from the master ramp, for the respective ramps R.sub.1 -R.sub.6, each reading R* on the master ramp appears on the respective secondary ramps reduced by a quantity k, 2k, . . . 6k, where k is 1/6 the difference between the initial count on the master ramp and the initial count on the secondary ramp at zero delay angle.

Referring to FIG. 5, for reasons of simplicity, k is chosen to be equal to half the initial count of the master ramp. If the initial count of each secondary ramp is R, 6k=2R. The CPU periodically reads the value of R* on the master ramp. Timer T.sub.1 is programmed so as to reset the master ramp to the initial count 2R upon each occurrence of the SYNC pulse, and to count down between SYNC pulses. The initial count of T.sub.1 is set via software to be such that the terminal count-zero is reached at the instant of the next SYNC pulse. Therefore, on line 3 of FIG. 4, a descending master ramp appears as shown in FIG. 5.

For the secondary ramps R.sub.1 -R.sub.6, if the initial count is R=1/2 R*, the instantaneous count on a secondary ramp is given by the following relations:

(1) R.sub.1 =R*-R

(2) R.sub.2 =R*-(2/3)R

(3) R.sub.3 =R*-R/3

(4) R.sub.4 =R*

(5) R.sub.5 =R*+R/3, when R.sub.5 is smaller than R

(6) R.sub.5 =R*-(5/3)R, when R.sub.5 is larger than R

(7) R.sub.6 =R*+(2/3)R, when R.sub.6 is smaller than R

(8) R.sub.6 =R*-(4/3)R, when R.sub.6 is larger than R.

The CPU reads the value of R* from line 3 and performs the above transformations, thereby defining an operative point on one of the six secondary ramps. The CPU also reads from line 7 the numerical value of reference R.sub..alpha. defining the delay angle. This value is in fact stored in memory as a result from regulation algorithms performed under the controlled process. According to the present invention, the operative point at a given instant on a given ramp R.sub.1 . . . R.sub.6, e.g. for a thyristor next to be fired, is used as a count which is compared with R.sub..alpha. by the CPU in order to ascertain how far in the future is the gating instant for the particular thyristor, and such future gating instant is instantaneously projected as a count in a second timer T.sub.2 which, so loaded, will count down and reach a terminal count exactly at the projected gating instant.

Thus, the operation of timer T.sub.2 of FIG. 4 is programmed by the CPU so that a count calculated on the basis of the set of relations (1) to (8) and on the basis of T.sub.2 =R.sub.N -R.sub..alpha. is loaded, by line 8, as an initial count into T.sub.2. The count-down by T.sub.2 is initiated immediately after loading. Count-down proceeds at a known decrementing clock rate which matches the master ramp decrementing rate. After loading T.sub.2, the CPU terminates its gating activity and returns to other tasks. When counter T.sub.2 reaches its terminal count, it causes by line 9 a signal interrupt I to force the CPU to interrupt its other tasks and implement gating, by changing the state of the bits at the exit port, so that the proper thyristor is gated.

It is observed that in the process of reading R* on the master ramp, of comparing at a given instant the count which is indicative of the operative point on the selected ramp R.sub.1 . . . or R.sub.6, of calculating a preset value for timer T.sub.2, loading timer T.sub.2, counting down such preset value and sending an interrupt command to the CPU in order to cause a triggering pulse to be applied to the thyristor driver circuit, several dead times have to be accounted for. These amount to offsetting the down-counter T.sub.2 by as much as to cause the occurrence of the firing pulse in real time at the anticipated instant for such event. This is a programming technique which is illustrated herein in the Appendix, by reference to FIG. 13.

Referring to curve (a) of FIG. 6, one secondary ramp is shown with the prospective gating instant T.sub.g ' corresponding to R.sub..alpha. on the ramp. Curve (c) shows down counting of timer T.sub.2. The latter reaches zero at an instant for which curve (b) shows an interrupt pulse I. As a result of such recognition earlier by the CPU, gating of a preceding thyristor occurred at the gating instant T.sub.g. Following gating of such thyristor, the CPU effects at instant T.sub.r a reading R(N) of the ramp, and calculates the difference d between such reading R(N) and R.sub..alpha. (line 7). Actually, the CPU calculates a function of the difference, typically d minus a constant. Immediately, via line 8, such count derived from d is loaded into the timer T.sub.2, namely at instant T.sub.rt. This is also the end of the gating activity of the CPU until instant T.sub.g ', the future gating instant. Indeed, T.sub.g ' is determined, like earlier instant T.sub.g, by the terminal count of counter T.sub.2.

It appears that, with this approach, the CPU is active with the gating function only for short intervals immediately before and after gating, six times per AC wave period. Accordingly, the CPU remains available for other tasks most of the time between gatings. It also appears that hardware peripheral to the microprocessor is limited to timers. For instance, when using INTEL processors, a timer peripheral, known as INTEL 8253, can be used which is a chip containing three 16-bit down-counters, of which two can serve as timers T.sub.1 and T.sub.2 of FIG. 4. The counters can be read at any moment by the microprocessor. They can be triggered by external signals and they generate external signals upon the occurrence of a terminal count. They are clocked externally by the same clock as the CPU, or a submultiple thereof. Other manufacturers than INTEL Corporation provide similar chips on the open market. Each timer is a register, typically 16-bit wide, the binary contents of which are decremented by one at each clock period. Line 10 of FIG. 4 indicates a port providing six lines energizing the gates of the six thyristors via gate drive amplifiers, as generally known.

It is observed that the resolution with which the delay angle .alpha. is determined is independent from microprocessor instructions execution time. It depends only upon the number of bits in timer T.sub.1 and timer T.sub.2 registers, and upon the clock rate. Typical values, in this regard, are 16 bits and 2 MHz. This makes it easy to achieve delay angle accuracies and resolutions better than 1/4 degree, even with relatively slow processors.

Gating implementation is achieved with no hardware peripheral to the microcomputer system other than a programmable interval timer which is standard with most microcomputer boards. Moreover, the processor uses a small fraction of its time, about 15%, in carrying out the gating function. This leaves plenty of time for the other tasks, such as current or voltage servo-regulation and the power converter supervisory functions.

The implementation of the firing circuitry is illustrated in FIG. 7. The six-thyristor bridge of FIG. 1 is, there; shown with one of the six firing circuits FC.sub.2 associated with thyristor TH.sub.2. Line 10 (which is one of six lines, in FIG. 4, at the output of the CPU) receives a gating pulse G.sub.2 causing transistor TR.sub.1 to be conductive. This causes in turn, via optico-coupler GE, transistor TR.sub.2 to be conductive, thereby discharging capacitor C.sub.2 between lines 11 and 12 on the gating terminals of thyristor TH.sub.2. The circuitry shown is conventional.

Referring to FIG. 8, a functional block diagram illustrates the implementation of the circuit of FIG. 4 on an INTEL ICS-80 chassis. This implementation is based on a standard three-phase bridge AC/DC converter used in the rectification mode to drive a DC motor M. The selected microprocessor hardware is taken from the Industrial Control Series (ICS) of Intel Corporation, which includes an ICS-80 chassis with a 640 Power Supply (PS) and a 614 Card Cage (CC). The digital circuitry is selected from the Single Board Computer Series (ISBC) of Intel, including a 569 Intelligent Digital Controller Board (IDC), containing an 8085 CPU and two external timers T.sub.1, T.sub.2, which performs all the calculations, and a 732 Combination Analog Input/Output Board (ADB) which performs the required A/D conversions.

The 569 IDC is a Single-Board Computer based on the 8085 CPU. It is utilized as a stand-alone digital controller in the system. The 569 IDC contains 2K bytes of RAM and sockets for up to 8K bytes of EPROM. In this application, less than 2K bytes of EPROM are required to store the main program. About 18 bytes of RAM are required to store values of variables and the register contents when they are pushed on the stack.

The 569 IDC contains three programmable counters on an 8253 chip. Of these three counters, a first counter (No. 0 on the 8253 chip) is used as counter T2 and connected directly to an edge triggered interrupt input of the CPU. This allows it to be used as the interrupt timer. When the counter reaches zero count, an interrupt is generated and applied to the CPU. The CPU then starts executing instructions at the interrupt vector memory location 003C (hexadecimal). Actually, a jump instruction to the actual interrupt service routine is placed here by the user. During the execution of the service routine, the next thyristor in sequence is fired and counter No. 0 is reloaded with the number of counts before the thyristor firing, and the process repeats itself. This mode of operation is achieved by programming counter No. 0 to operate in the software triggered strobe mode (Mode No. 4 on the 8253 chip). A second counter, (counter No. 1 on the 3253 chip) is used as the master ramp timer T.sub.1. It is programmed in the hardware triggered strobe mode (Mode No. 5), so the SYNC pulse triggers it to down count every cycle. The counter is rising-edge triggered and the SYNC pulse is applied directly to its gate input. The timer clock frequency is 1.3824 MHz so that 20,040 counts correspond to 1 cycle.

The 569 board IDC contains sockets for three programmable Input/Output ports that function as intelligent slaves to the host CPU. This allows the I/O processing to be custom-tailored to the required application. Either the Intel UPI-41A, or a 941 Industrial Digital Processor (IDP), on FIG. 8, may be used in these sockets. The 941 IDP at the interface seves as Exit port. Because the 941 IDP can execute nine dedicated I/O algorithms and eight common data manipulations, it is preferred for the simple I/O operations required in the power controller. Six of the 16 available I/O lines are used to latch the present thyristor firing sequence when it is output by the CPU. Eight of the lines are used to latch the binary representation of the present delay angle. The routine required to latch these outputs on the 941 IDP are discussed hereinafter.

The 569 communicates with other boards in the cardcage CC through the Intel MULTIBUS data bus DB. MULTIBUS DB is a standard data bus structure in which each output pin has a standard signal function.

The 732 ADB board is used to digitize the analog representation of the delay angle received on line 51 after transfer into the 614 card cage CC by a 910 analog terminating panel ATP, which is responsive to the reference signal v.sub.c on line 5, as well as to the SYNC pulse of line 2. The A/D converter is a 12-bit, 34 .mu.s successive approximation device with a sample-and-hold amplifier which can be jumper-selected for a 0 to +5 V, 0 to +10 V, .+-.5 V, or .+-.10 V input range. In this instance, the board is wired for the 0 to +10 V range. The board has up to 16 differential, or 32 single-ended inputs. Only one single-ended input is used here for the delay angle. The ADB board includes a DC/DC converter module which supplies +15 V and -15 V power at 150 mA to the analog circuits. The +15 V supply is used to supply voltage to a potentiometer P.sub.1 which serves to adjust the delay angle outputted on line 5. To this effect, the +15 V voltage is dropped through a 5K resistor ahead of a 10K delay angle potentiometer P.sub.1 providing the required 0 to 10 V range.

The 732 ADB board communicates with the 569 IDC board through the MULTIBUS DB. The 732 ADB board interfaces as external memory, and any of the memory reference instructions from the 8085 CPU can be used to read from the 732 ADB board.

Signal conditioning is provided at the analog inputs by a 910 analog termination panel ATP. Similarly, a 920 digital termination panel DTP responds to outputted digital requests from the 614 card cage CC in providing the firing word on lines 10 to the thyristor firing circuitry (FC) and, via 12, to a 3-digit display by a light emitting diode display LED for the delay angle .alpha..

The Signal Conditioning/Termination Panels ATP and DTP are heavy duty printed circuit board with screw terminators to which users can easily connect heavier gauge field signal wiring. These signals are then connected to flat ribbon cables on the board which then connect to the single board computer boards.

The mounting technique is illustrated for the 920 board DTP by FIG. 9. The IDC board carries the Exit port in the form of a 941 industrial digital processor IDP. The output goes to a driver device DS.sub.1 and the so outputted signal is transmitted over a ribbon cable RC to the driver device DS.sub.2 on the digital termination panel DTP. Device DS.sub.2 is connected to the base of a transistor TR.sub.3 which drives a diode DS.sub.3 and an LED device LED.sub.3. The output is between screw terminators from which lines 10 and 12 are derived.

The 920 board DTP provides sockets for line drivers, or opto-isolators, that can turn on the LED diodes on the board when the output signal is high. FIG. 9 shows how the line drivers IDP are configured on the 920 board DTP, to switch via lines 10 and 12 the LED OFF and ON.

A SYNC pulse is required to keep the Master Ramp timer T.sub.1 synchronized with the line voltage. A rising edge of a pulse to the gate input of the Master Ramp T.sub.1 counter resets it to start down-counting from a preset value. The SYNC circuitry illustrated in FIG. 10 performs this function. The input line to neutral voltage V.sub.AN is first low-pass filtered by a T network composed of resistors R.sub.7, R8 and capacitor C.sub.3. This filtering is required to remove any noise spikes from the line voltage that would result in spurious SYNC pulses. The transfer function of this network is such that the voltage v.sub.c across capacitor C.sub.3 lags the input, V.sub.AN, by 30.degree.. The SYNC pulse will then lag the A-phase by 30.degree.. As FIG. 11 shows, this point corresponds to the natural commutation point of the line-to-line voltages, V.sub.AB and V.sub.CB. Therefore, the first thyristor firing in each cycle should correspond to the V.sub.AB phase.

At the output of the filter network diodes D.sub.4 clip the sinusoidal line voltage to approximate a square wave. The latter is then applied to a transformer TRF which steps up the voltage so that the slope of the square wave will be very steep at the zero-crossings. This steep transition will help minimize the effects of any spurious noise in the vicinity of the zero-crossing, where the sync pulse should occur. A 100K resistor R.sub.9 and a 100 pF capacitor C.sub.4 also provide some low-pass filtering before the final output on line 2.

A CMOS Schmitt trigger circuit, including these NAND gates GT.sub.1, GT.sub.2, GT.sub.3, provides hysteresis in the output to prevent OFF-ON flickering of the SYNC pulse. The three gates GT.sub.1 -GT.sub.3 are tied together at the output to provide enough current drive for a TTL load.

During the period between T.sub.2 timer interrupts, the microprocessor outputs the latest value of the delay angle. This value is latched onto the 941 IDP output port, and routed out to the 920 digital output board DTP. This 8-bit representation of the delay angle is then converted to BCD code and displayed by 7-segment LED's.

In the thyristor firing circuit of FIG. 7, when the gate G.sub.2 of line 10 goes low, TR.sub.1 turns ON and current is provided for the LED in the opto-isolator GE. This turns ON the transistor in the opto-isolator which turns ON TR.sub.2. The collector current from TR.sub.2 provides a positive voltage across a 100.OMEGA. resistor. This pulse which is about 1 V, triggers the gate of the corresponding thyristor TH.sub.2.

The following chart shows the firing words delivered by the 569 IDC board in the order that they occur during one complete cyle. It is observed that, through its software, the microprocessor actually outputs the complement of the firing words shown, but these words are inverted by a 7437 chip at the output of the 569 board IDC.

Referring to FIG. 12, the six ramps R.sub.1 -R.sub.6 of FIG. 5, are shown in hexadecimal representation for a 8253 timer T.sub.1 at 2 MHz of counts for 60 Hz (ora along the abscissa). The ordinates read 6400 H for R* on ramp R.sub.4 ; 5355 H for ramp R.sub.3 ; 42AB H for ramp R.sub.2 ; 3200 H for ramp R.sub.1 ; 2155 H for ramp R.sub.6 and 10AB H for ramp R.sub.5. The useful range for the delay angle is limited to between an upper limit UL for 300 (at 29AB H) and a lower limit LL for 150.degree. (at 855 H). The value of R is 3200 H which corresponds to 1/2R* max. and represents a range of 180.degree. from 0 reached at the maximum of R.sub.1.

The sequence of events in the digital hardware, typically, is as follows:

1. Timer T.sub.2 has been loaded with the number of counts before the next thyristor sequence should be fired. Upon reaching terminal count, timer T.sub.2 interrupts the CPU.

2. The CPU recognizes the interrupt and outputs the next thyristor firing word on line 10. As an example, this may be 100001, indicating thyristors TH.sub.1 and TH.sub.2 in FIG. 1 should be ON.

3. The CPU reads the present value R* of the Mater Ramp from timer T.sub.1.

4. With this value R*, the CPU calculates the value of one of the ramps R.sub.1 -R.sub.6 corresponding to the next thyristor to be fired.

5. Given the value R*, and the value R.sub..alpha. for the delay angle .alpha., the CPU calculates the number of interrupt counts d that should pass before the thyristor "next" in the sequence can be fired.

6. The CPU loads timer T.sub.2 with the value d, and timer T.sub.2 starts counting down.

7. The CPU can perform other functions, or wait, until the next interrupt occurs, and the process repeats itself.

Referring to FIG. 13, a chart is provided to indicate the tasks of the CPU and their timing as they occur during one cycle delineated by two successive thyristor firing instants, namely at 104 and at 116 on the chart. FIG. 13 will be explained with peculiarity in the Appendix attached hereinafter to provide in detail, with a listing, routines and subroutines as can be used according to one embodiment of the invention which is illustrative of a possible implementation thereof.

Summarizing the main steps indicated by reference numerals on FIG. 13, the following remarks are in order:

The figure represents the count of time T.sub.2 as a function of time. Following initialization, at time t.sub.1 initial loading of timer T.sub.2 takes place at time t.sub.2. After counting down to zero, the down counter of timer T.sub.2 jumps back to its full value (FFFFH from 0000) at step 100. A variable interrupt time lapses until 101 which is followed by latching the wraparound value at 102. At 103 the CPU executes the delay subroutines, then exits at 104, at which time the thyristors are being fired, thus in accordance with the preceding firing cycle. The new firing cycle starts at 105 by reading R.sub.60. At 106 timer T.sub.2 has its counter latched with the wraparound value. Then, at 107, after a constant time interval A, the value R* is read on the ramp. The time interval until firing extends from 107 until 116. In the meantime the CPU effectuates the following tasks:

At 108 the RI subroutine is executed and at 109 the CPU returns with the number of counts, corresponding to d on FIG. 6, which results from a comparison between R.sub..alpha. and R*. Actually, this number of counts represents the time interval between when R* was last latched (at 106) and the anticipated "reset" firing point (at 116). At 110 the wraparound value is latched from the counter of timer T.sub.2. At 111 the counter is loaded, an operation which actually lasts until 112. From 112 until 115 lapses a time interval which is the time conversion of the loaded count. From 115 to 116 a constant time interval C, identical to the one from 100 to 104, elapses. From instant 110 to instant 112 the time interval B is constant. The "actual time" that should be loaded into the T.sub.2 counter extends from 112 to 115 and is equal to Y+A-X-C-B, as can be seen from the chart of FIG. 13.

The Appendix A will now provide a detailed functional explanation of the software implementation of the heretofore described invention and it is followed by Appendix B providing a program listing for this software implementation.

(The following page is Appendix page A1.)

It is recalled that when translating a count R* read from the master timer T.sub.1 ramp, the following set of equations is used taking into account the facing remarks:

In the implementation, a first requirement limits the range of magnitude of the delay angle to between 30.degree. and 150.degree. for practical reasons. Another requirement limits the change of the delay angle between two consecutive thyristor firings to a maximum of 20.degree. so that the possibility of a negative time interval never exists. The manner in which these restrictions apply to the microprocessor design is a follows:

1. After R.alpha. has been scaled, the values read by the processor CPU should correspond to angles only in the range of 30.degree. to 150.degree.; and

2. The difference between any two consecutive values of R.alpha. should not represent an angle greater than 20.degree..

There are other microprocessor considerations which may be mentioned. First, a certain interrupt latency time exists within most microprocessors. This means that real time occurrences and microprocessor time occurrences are not synchronized. Two other considerations are peculiar to the 8253 programmable timer used for T.sub.1. First, this timer has the capability of being read without interrupting its timing sequence. Moreover, this timer continually counts and overlaps itself in any mode of operation.

One suitable example of an illustrative software implementation of the present invention is shown in FIG. 13. There, a functional diagram illustrates as a function of time the successive steps performed with the assist of the CPU that controls the three-phase power converter. The first CPU action is, at time t.sub.1, to initialize any ports, memory locations, and timers required to control the converter. At time t.sub.2 toward the end of the initialization process, the timer T.sub.1 corresponding to ramp R* is loaded so that it reaches terminal count in 1/60 of a second. Timer T.sub.1 is reinitialized with every SYNC pulse and its function is to provide the microprocessor with a timing reference between SYNC pulses. This timing reference is utilized by the processor to determine the firing times of the thyristors.

Once the R* timer is loaded at t.sub.2 with the proper value, a start-up routine is entered. This routine simply polls the R* timer for a particular range of values corresponding to angles less than or equal to 10.degree. on secondary ramp, for instance R.sub.1. When a value in this range is found, the routine calculates the count value that should be loaded into the interrupt timer so that upon interrupt recognition the thyristors for ramp R.sub.1 are fired at a delay angle of 90.degree.. Firing the thyristors of ramp R.sub.1 with an initial 90.degree. delay angle produces zero output voltage.

The first ramp R.sub.i illustrated in FIG. 13 is the one associated with the initial interrupt timer T.sub.2 counting sequence. During this time interval, the processor simply waits until it is interrupted by the terminal count of the interrupt timer. Immediately after the interrupt timer reaches terminal count it wraps around to FFFF H and continues to down count. The second ramp R.sub.W represents this wraparound counting sequence. As shown in the trapezoid portion of ramp R.sub.W (between 100 and 101), there is a certain variable interrupt recognition time associated with the 8085 microprocessor. The range of this variable interrupt recognition time is one to nineteen states of the processor.

At 101 upon interrupt recognition, all the registers are saved on the stack so that control can be transferred back to a user program at a later time. At 102, the interrupt counter T.sub.2 wraparound value is latched to determine the number of states associated with the interrupt latency time. This value is also used to transfer control to one of ten delay subroutines which correct the interrupt latency time by making it a constant 23 states. The idea here is that there are only ten possible values which can be read from the interrupt timer when it is latched since the frequency of the 8253 is 1/2 the frequency of the processor and the variable interrupt time is one to nineteen states of the processor. Once control is returned from the delay subroutines at 104, the thyristors corresponding to a particular ramp are fired.

The interrupt routine continues with the processor preparing to calculate the next value that should be loaded into the interrupt timer. First, at 105 the processor reads in a new value of R.alpha.. This is accomplished by executing the R.alpha. subroutine which, in addition to obtaining the present value of R.alpha., also performs the following two checks:

1. The angle R.alpha. represents must be within the practical angular limits of the converter.

2. The variance of the angle that R.alpha. represents must be less than 20.degree. between two consecutive readings.

If either of these checks is positive, the microprocessor alerts the converter operator and implements the two following solutions:

1. If the value of R.alpha. corresponds to an angle out of the angular limits of the converter, R.alpha. is forced to be the closest end stop value.

2. If the variance of R.alpha. exceeds 20.degree., the variance is forced to exactly 20.degree..

After obtaining a new R.alpha. value the interrupt routine at 106 latches and saves the present interrupt counter wraparound value for a future calculation. Then, at 107 a new value of the master ramp R* is read by executing the subroutine R*. This subroutine checks to insure that the read in value of R* does not exceed the maximum allowable value. If the value of R* does exceed the maximum value, R* is forced to zero. This error occurs due to counter wraparound and lack of synchronization between the SYNC pulse and the terminal count of the R* timer T.sub.1.

Once recent allowable values have been obtained for R.alpha. and R* the interrupt routine at 108 transfers control to one of six RI subroutines (for the respective ramps R.sub.1 -R.sub.6). These subroutines have two purposes. First, they make sure that R* is in the proper range for the future calculation of the parameter "Y". This eliminates the possibility of a drastic error such as a missed syn pulse or time malfunction. For instance, if a SYNC pulse were not detected the value of R* would remain equal to zero for several consecutive readings, thereby, enabling these routines to detect such an error. The second function of these six subroutines is to calculate the value of the parameter Y which is the time between 107 and 116 when the next thyristor is to be fired. This is done, in this instance, with the use of the equations from Equation Set #1 and the most recent values of R.alpha. and R*.

When control is transferred back at 109 to the interrupt routine, another interrupt counter wraparound value is latched, at 110 so that the variable "X" (between 106 and 110) may be calculated. The parameter "X" is a variable due to the fact that there are six different RI subroutines and each particular RI subroutine has different limit checks to perform within itself. Upon determining the variable X and Y, the processor calculates the actual time to load the interrupt timer T.sub.2 with, by solving the following equation:

Actual time=(Y+A)-X-C-B, (where A is a constant time interval between 100 and 104 as well as between 106 and 107; B is a constant time interval between 110 ans 112; C is a constant time interval between 115 and 116). The various parameters are illustrated in FIG. 13. Once this calculation is completed, the interrupt timer T.sub.2 is loaded with the actual time and the necessary steps to return program control to a user program are executed.

The third sloping ramp R'.sub.W is the counting down slope associated with the interrupt timer T.sub.2 for the "next" thyristor to be fired and the process repeats itself from thyristor to thyristor.

The following is a program outline summarizing the detailed steps of a software program given hereinafter.

A. Program a counter of the 8253 CPU to operate in mode four. This mode of operation is initiated at t.sub.2 by simply loading counter T.sub.2 with a given count down value. The output of this counter should be connected to an edge sensitive interrupt of the processor. This counter is the interrupt timer T.sub.2.

B. Program a counter of the 8253 CPU to operate in "mode five". This mode of operation is initiated by a rising edge pulse applied to the gate input. This counter should be loaded such that it down counts to zero f times per second where f is the frequency of the sync pulse (60 Hz in the example). This counter is the master ramp (R*) timer T.sub.1.

C. Initialize the Stack pointer.

D. Initialize the ports necessary for program control:

1. 12 inputs for the A to D converter which varies the value of R.alpha..

2. 2 ports, one an input and one an output, to control the A to D.

3. 6 outputs for gating the thyristors.

4. If desired, additional inputs and outputs for Alert programs.

E. Initialize the following memory locations:

1. CHECK--This memory location maintains the value of the previous thyristor firing angle so that the maximum allowed variance of 20.degree. may be checked. In this program, CHECK is initialized with a value corresponding to 90.degree. so that the first thyristor firing will not participate in any power conversion.

2. SEQ--This memory location maintains the gating sequence of the thyristors and is initialized so that the thyristors corresponding to ramp R.sub.1 are fired.

3. RI--This memory location is used to store the beginning location of one of six calculation subroutines.

F. Load the counter which is programmed for mode five with the maximum value of R*.

G. Enable interrupt RST 7.5 so that the interrupt timer is utilized properly.

A. Continually read in the value of the R* timer until a value is read which corresponds to an angle .gtoreq.0.degree. but .ltoreq.10.degree. on the R.sub.1 ramp FIG. 4 illustrates this region on the master ramp by the checked section which ends with the hex number 6139.

B. Calculate the time necessary to load the interrupt timer so that the thyristors corresponding to ramp R.sub.1 are fired at an angle of 90.degree..

C. Load the interrupt timer.

D. Continue with other user programs.

Entry Point: The interrupt sequence is initiated when the interrupt timer times out. Actually, the interrupt sequence begins one count of the 8253 after the terminal count of the interrupt timer is reached. This is due to the fact that the RST 7.5 is rising edge triggered.

A. Save all user registers so the program that was interrupted may be continued.

B. Read in the contents of the interrupter timer.

1. The interrupt timer will overlap and immediately begin counting down from FFFF after the interrupt terminal count is reached. Therefore, by reading this counter upon interrupt recognition, it is possible to calculate the exact interrupt latency time.

C. Transfer control to the delay subroutine which will make the variable interrupt latency time a contstant.

1. The transfer of control to the delay subroutines is accomplished by knowing there are only certain possible values that will be read from the interrupt timer.

D. Upon return from the delay subroutines, fire the proper thyristor sequence.

E. FIG. 13 illustrates the entire interrupt routine timing by following the interrupt timer T.sub.2 as it overlaps and continues to count down. The specific time occurrences 100-116 in the interrupt routine are exemplified in this functional diagram.

A. Latches onto the contents of the R* timer.

B. Checks to make sure the value read in is less than the maximum R* value. This eliminates the possible error of counter wraparound by forcing any value greater than the maximum R* to zero.

1. The maximum value of R* is determined by the clock frequency of the 8253 CPU timer.

Exit Points: This subroutine returns the value of R* in two locations:

1. HL register.

2. R*STAR memory location.

A. Reads in the 12-bit value from the A to D converter which represents the upper four bits of the high order byte are masked off.

1. The value read in from the A to D should be scaled so that its maximum value is an integer multiple of 1/2 R* max. This integer multiple should be as small as possible, thereby maintaining the degree per bit accuracy as high as possible.

B. Multiply the value read in for R.alpha. by the necessary integer to make its full range of values be 0 to 1/2 R* max.

C. Make sure this multiplied value of R.alpha. does not represent an angle outside the range of 30.degree. to 150.degree.. If it is out of this range, force R.alpha. to be one of the end stops.

D. Make sure the new value read in for R.alpha. does not represent an angle which differs from the angle the old value of R.alpha. represented by more than 20.degree.. If it does differ by more than 20.degree., force the angle to differ by exactly 20.degree..

Exit Points: This subroutine returns the value of R.alpha. in three locations:

1. HL register.

2. DE register.

3. CHECK memory location.

Exit Points: Two memory locations must be occupied before entering this subroutine:

1. R* memory location must contain the most recent value of the master ramp.

2. The DE register must contain the most recent value of R.alpha..

A. Check to make sure R* is in the proper range so that the future calculation of Y in FIG. 13 is possible.

Example: Assuming the thyristor in the sequence corresponding to the ramp R.sub.6 was just fired, the thyristor firing point is located on the ramp of FIG. 13. Once the thyristor corresponding to ramp R.sub.6 has been fired, new values for R.alpha. and R* are read. The RI subroutines are then entered. In this particular case, the R.sub.1 subroutine would be initiated. The first thing accomplished by this subroutine is to check whether the last value read for R* is in the range of possible values corresponding to ramp R.sub.6. This check eliminates the possible error of a missed SYNC pulse.

B. Calculate the next R* firing value by using the equations in Equation Set 1.

C. Calculate the variable Y of FIG. 13 by subtracting the next R* firing angle from the one last read.

D. Push the value of the variable Y on the stack.

E. Load memory location RI with the beginning location of the next successive RI subroutine.

F. Load memory location SEQ with the next thyristor firing in the sequence.

Exit Point: This subroutine returns the value Y in one location, the stack.

The purpose of these subroutines is to time the firing of the thyristors as close as possible. The need of these routines arises from the indefinite time period associated with interrupt recognition. If the timing of the CPU 8085 microprocessor is studied closely, it can be shown that there are only a few possible values that can be read off the interrupt timer T.sub.2 immediately after interrupt recognition.

Timing Facts Pertinent to the hardware used.

A. One clock count of the 8253 CPU timer T.sub.1 passes after terminal count before rising edge is applied to the "RST 7.5" input of the CPU 8085. This is taken into account when loading the interrupt timer.

B. Response time on the CPU 8085 microprocessor may vary between 1 and 19 states.

C. 12 states of the microprocessor are required for pushing the program counter on the stack.

D. 10 states of the microprocessor are required for jumping from the ROM interrupt vector to the RAM interrupt vector.

E. 10 states of the microprocessor are required for jumping from the RAM interrupt vector to the interrupt program.

F. 65 states of the microprocessor are required for latching onto the contents of the interrupt counter and saving the user registers.

Total Time:

98 to 117 states on the CPU 8085;

49 to 58 counts on the 8253 timer T.sub.1 ;

Therefore, the possible values that can be read from the interrupt timer T.sub.2 upon interrupt recognition are: ##EQU1## G. The least significant hex digit is used to determine which delay routine is executed. The following table illustrates the delays associated with each digit.

H. The Delay Subroutine function to make the number of delay states equal to 23 in all cases.

The following pages are a typical control program based on an ISIS-II 8080/8085 Macro Assembler as used for the 569 IDC Board of FIG. 8. The instruction program listing is written in the assembly language of the Intel 8085 microprocessor. This instruction program listing is included to provide an illustration of one suitable embodiment of the present invention that has been developed. ##SPC1## ##SPC2##