Digital Firing Pulse Generator for Thyristor Power Converters

The present application is related to the following concurrently filed patent application which is assigned to the same assignee as the present application:

Ser. No. 642,809, which was filed on Dec. 22, 1975 by Richard L. Detering.

The invention relates to firing pulse generators for thyristors, and similar types of static electric valves such as used for power conversion in polyphase electrical supply. Digital firing pulse generators are known from "Thyristor Phase-Controlled Converters and Cycloconverters" by B. R. Pelly, chapter ten, pages 248-277 - John Wiley and Sons 1971. Of importance with such systems is the reliability and accurcy of the control pulses. Phase-locked oscillator techniques have been used in order to obtain pulse timing which is independent from actual fluctuations in the power lines, so that, for the purpose of establishing an accurate firing angle, the firing instant is fixed in electrical degrees. Thus, U.S. Pat. No. 3,534,285 entitled "Digital Phase Control Circuit for Synchronizing an Oscillator to a Harmonic Or a Reference Frequency" by P. J. Kobold et al issued Oct. 13, 1970 teaches a system where a signal is applied to a phase detector which in turn controls a voltage controlled oscillator that generates a signal applied to a counter for providing a binary output.

Such a voltage controlled oscillator when synchronized with the phase line of a polyphase AC power system, as described in U.S. Pat. No. 3,891,912 of Watanabe, may provide a binary output to be compared with a voltage reference signal for generating firing pulses, at selected firing angles, to thyristors connected in a polyphase arrangement on the power lines. The thyristors in the Watanabe Patent are fired in succession by a ring counter triggered on each comparison. At the same time, the binary count in the counter is modified in its most significant digits so as to generate in a ring fashion, upon each triggering by the comparator, a binary representation of the subsequent phase of the power lines in which the next controlled rectifier to be fired is connected. However, in the Watanabe system, should a lack of concordance occur during transition of the ring counter, the binary counter, or both, a proper correspondency between the phase represented by the digital count and the selected rectifier to be fired no longer exists. Improper firings will result.

In order to overcome this drawback, the present invention proposes that the comparator trigger only the ring counter and that the ring counter be locked with the digital counter used for the determination of the firing angle and the generation of a triggering pulse.

The invention relates to digital phase controllers as can be used for controlling the firing angles of a polyphase AC converter system. The digital phase controller according to the present invention establishes a firing angle for successive power thyristors of a converter system, as prescribed by a reference analog or digital signal and low level logic signals are generated as output signals for firing control.

The digital phase controller according to the present invention includes a circuit for the generation of an electrical signal representinng the desired electric angle from a point in time corresponding to zero crossing of the AC supply. A variable frequency oscillator generates between successive zero crossings in one direction N pulses at a frequency which depends upon the length of the fundamental cycle, so that each pulse represents an exact increment of 2.pi./N of electrical angle. An instantaneaous count of said pulses is derived in digital from which represents an electrical angle counted for each phase line from a corresponding crossover. For each such count a saw-tooth signal is derived so as to integrate the digital count, for the purpose of analog comparison with the analog reference signal. When the comparator reaches equality the firing pulse is triggered and a pulse is applied to the power thyristor of the associated phase and appropriate polarity.

The apparatus according to the present invention may take two forms. In one form a hybrid analog-digital circuitry is used including a digital-analog converter for the comparator. The second is all digital circuitry. In the latter case, if the reference signal is analog, it is first converted into digital form so that comparison can be performed digitally.

The invention also provides for effective rectification and inversion end stops. The rectification end stop limits the firing angle advance so that the power thyristor does not receive a gating fire pulse before it is capable of conducting. The inversion end stop limits the firing angle retardation so that the power thyristor receives the gating fire pulse before the available commutating voltage has become too low.

FIG. 1 shows diagrammatically the digital pulse generator according to the present invention;

FIG. 2 shows the phase voltages of the power supply with the periods of conduction of the thyristors, and three timing waveforms (a), (b), (c) used with a reference voltage to establish the firing angle;

FIG. 3 shows the phase locked oscillator generating synchronized clock signals and the associated digital counter in a preferred implementation of the digital pulse generator of FIG. 1;

FIG. 4A shows a preferred implementation of the circuitry of the ramp generator and multiplexer of FIG. 1;

FIG. 4B is a graphical representation of the output gate drive waveforms used to build the timing waveforms;

FIGS. 5A and 5B are a graphical representation of the timing waves and control pulses generated by the circuits of FIGS. 3 and 4A;

FIG. 6 illustrates in a preferred implementation the ring counter, the analog comparator and the distributor circuits of FIG. 1;

FIG. 7 is a graphical representation of the operation of the 3-stage counter and of the distributor of FIG. 6 for various firing angles;

FIG. 8 illustrates the phase controller operation when transferring from "rectification" to "inversion";

FIG. 9 shows a second embodiment of the digital pulse generator according to the present invention;

FIG. 10A shows a preferred implementation of the analog comparator circuit of FIG. 9;

FIG. 10B illustrates the 9-stage counter and level amplifiers of FIG. 9;

FIG. 10C shows the 7-stage comparator;

FIG. 10D shows the end-stop circuitry and the set gate;

FIG. 10E illustrates the digital comparator in a specific embodiment of FIG. 9 and the 3-stage section of the digital comparator of FIG. 9;

FIGS. 11 and 12 are graphical representations illustrating the operation of the analog comparator of FIG. 9;

FIG. 13 is a graphical representation of the operation of the 3-stage counter and of the distributor of FIG. 10E.

FIG. 1 shows a bank B.sub.1 of six bridge power thyristors T.sub.1 - T.sub.6 connected across a balanced three-phase system supplying voltages V.sub.A, V.sub.B, V.sub.c on three busses 1, 2, 3. The thyristors are gated for conduction from separate lines 25. The firing circuit in accordance with the present invention includes a zero-crossing detector 5 supplied on line 4 with a reference wave V.sub.AB corresponding to one phase of the power supply. Each time the reference waveform passes by zero in one direction, zero-crossing detector 5 generates a pulse which is synchronized with such passing through zero. A variable frequency oscillator 7 generates a clock signal on line 8 which has a frequency determined by the relation between two input signals fed on respective lines 6 and 11. The clock signal on line 8 is fed into a digital counter 9 thereby to generate in digital form, on lines 10, a digital representation of the number of clock pulses received since the last passing by zero of the reference waveform. N pulses are thus generated between two successive synchronization signals on line 6, so that between each clock signals a time interval equal to 2.pi./N is established. The digital counter has a selected number of digits, ten in this case. The Nth, or most significant digit, is fed back on line 11 as a second input to variable frequency oscillator 7. The variable frequency oscillator 7 is so arranged that the frequency of the oscillator is decreased whenever an Nth pulse characterizing a ONE is generated on line 11 before the occurrence of the expected synchronized pulse on line 6, and that the frequency of the oscillator 7 is increased whenever the Nth pulse on line 11 occurs after such synchronized pulse. When the occurrence of the Nth pulse on line 11 coincides with the occurrence of the synchronized signal on line 6 e.g. it is concommitant with a zero-crossing, the digital counter totalizes exactly N pulses spread over 360.degree. electrical angles, thus between two zero-crossings in one direction. In other words, the time spread of the N pulses digitally stored between successive zero-crossing of the reference waveform V.sub.AB is kept such that it matches exactly the cycle of the power supply. Digital counter 9 is reset via line 12 thereby to initiate a new count of N pulses. Should the phase, or the frequency, of the power supply be altered by some transient variation, the synchronized signal is retarded, or advanced, to the same extent. Such lag, or lead, on line 6 will accordingly create an opposite change in the occurrence of the Nth pulse fed back on line 11 so that the variable frequency oscillator will experience a correspondiing change in the frequency of the clock signals on line 8. Therefore, the count in digital counter 9 will bring the Nth pulse in time concordance with the line zero-crossing. The N pulses will have been compressed, or decompressed, so as to maintain an electric angle between each pulse which is always equal to 1/N .times. 360 degrees. As a result, counting in digital counter 9 will occur by increments representing 2.pi./N of the V.sub.AB sinusoidal time reference.

The zero-crossing detector 5, the variable frequency oscillator 7 and the digital counter 9 together form a phase locked digital device 26 providing at its output, on lines 10, a digital representation of the instantaneous electric angle of the reference waveform V.sub.AB between two successive zero-crossings. The phase locked digital device 26 is, according to the present invention, used for the generation of firing pulses with improved accuracy to provide improved control in a power converter system which, although schematized in FIG. 1 as a bridge, or a bank B.sub.1 of thyristors, may be other types of AC to DC, or AC to AC converter, or a cycloconverter.

The digital output of the phase locked digital device 26 on lines 10 is converted by a ramp generator 13 into three timing waveforms i.sub.A, i.sub.B, i.sub.C representing in analog form the successive counts of digital counter 9 for three phases shifted relative to each other by 60.degree.. Generator 13 provides in fact an analog representation in amplified form of the electrical angle given digitally by counter 9, and such representation is linear as a function of time. Accordingly, the sinusoidal wave of the reference phase V.sub.AB one line 4 has in fact been converted into a linear function i.sub.A having a slope selected as required for an accurate control of the firing angle. Since, as shown by curves (a) on FIG. 2, phases A, C', are shifted relative to one another by 60.degree. , only one phase is necessary for establishing the electrical angle at any given time and a similar electrical angle is also established for each of the other phases.

Generator 13 repeatedly derives a ramp (i.sub.A i.sub.A ', i.sub.B, i.sub.B, i.sub.C, i.sub.C ', on FIG. 2) synchronized with the reference V.sub.AB. Therefore, signal i.sub.A actually consists in a series of saw-toothes i.sub.A, i.sub.A ' of 180.degree. width for alternate polarities. Similarly, signals i.sub.B, i.sub.B ' and i.sub.C, i.sub.C ' are derived which are identical to i.sub.A, but shifted by 60.degree. from one another in succession. Signals i.sub.A, i.sub.A ', i.sub.B, i.sub.B ', i.sub.C, i.sub.C ' appear at the output of generator 13 on lines 14. Each signal such as i.sub.A, i.sub.B or i.sub.C, is a timing waveform representing the electrical angle instantaneously along the voltage curve V.sub.AB, V.sub.BC or V.sub.CA. A multiplexer 15 selects successively one of these signals after being gated by a select signal on line 22. Such selected signal appears on line 16 at the output of multiplexer 15, in accordance with the selected phase A, B or C of the power supply.

An analog reference singal I.sub.R (FIG. 2) on line 17 determines the firing angle (.alpha.) of the selected thyristor, or thyristors. For the purpose of illustration, the firing angle .alpha. is shown by reference to T.sub.1 and T.sub.4 for the common phase V.sub.AB, on FIG. 2. The delay from the instant of zero-crossing (which is time t.sub.OA for the positive polarity, and t.sub.OA ' for the negative polarity) is established by a concurrence in time between the ramp of the representative signal on line 16 and the analog reference signal I.sub.R supplied on line 17. Coincidence is established by a comparator 18, which upon equality generates a firing control signal on line 19. Since, as indicated earlier, each representative signal is shifted by the same phase 60.degree. , only one comparator is necessary. A ring counter 20, actuated by the firing control signal on line 19, is provided in order to strobe a distribution and gating circuit 24 via line 21. Circuit 24 shapes and generates firing pulses in accordance with a logic pattern which is effective to gate the selected thyristor, or thyristors, such as T.sub.1 - T.sub.6 in bank B.sub.1 on FIG. 1. In the example shown, T.sub.1, T.sub.2 and T.sub.3 are affected to respective phases A, B, C for one polarity. T.sub.4, T.sub.5, T.sub.6 correspond to the second polarity. The ring counter 20, also sets the multiplexer 15 via line 22 thereby to select the subsequent representative signal to be derived from lines 14 after a firing operation.

The operation of the digital firing pulse generator is as follows:

The digital counter 9 is driven synchronously with the AC supply frequency by means of the synchronization signal on line 6. The digital counter drives the ramp generator 13 which produces the indicated set of twin precision timing waveforms i.sub.A, i.sub.A ', i.sub.C, i.sub.C ', and i.sub.B, i.sub.B '. These timing waveforms are identical and mutually displaced from each other by sixty electrical degrees. They are so synchronized with the supply voltage (60 Hz), for instance, that i.sub.A is exactly in phase with voltage v.sub.AB but at twice the frequency. It follows that, for a balanced three phase power source, i.sub.C ' and i.sub.B are similarly inpahse with -V.sub.CA and v.sub.BC respectively. In the same fashion, i.sub.A ', i.sub.C, i.sub.B ', are in phase with -V.sub.AB, V.sub.CA and -V.sub.BC, respectively.

The crossover between a given timing waveform and the analog reference signal (i.e., when the magnitude of i.sub.A transfers from a value greater than the magnitude of I.sub.R to a value less than I.sub.R) determines when gate drive to a given thyristor in the power converter should be initiated. The greater the value of I.sub.R the earlier in the half cycle this crossover will occur, and vice versa as I.sub.R is decreased.

The timing waveforms i.sub.A, i.sub.B, and i.sub.C are sequentially compared to I.sub.R in the analog comparator 18 by means of multiplexer 15, causing a selective switching for one of the timing waveforms. Switching is determined by a three stage counter which has six discrete states. Three switches S.sub.A, S.sub.B, S.sub.C are permitted to conduct each during a given period. Assume S.sub.A is closed so that i.sub.A is being compared to I.sub.R. As i.sub.A becomes less than I.sub.R the analog comparator produces a pulse to advance the three stage counter by one state thus causing S.sub.A to open and S.sub. C to close. Thereafter, i.sub.C is being compared to I.sub.R, and so on. The states of the three-stage counter are appropriately decoded by the logic of the distributor 24 so as to produce a set of six pulse waveforms which serve as the gate drive waveform for the respective power thyristors, T.sub.1 - T.sub.6 on FIG. 1. For a given value of I.sub.R, each gate logic signal is a logic zero for 60.degree. and a logic one for 300.degree. of a cycle. Gate drive for the converter thyristor associated with a particular gate logic signal is initiated as the logic signal transfers from a ONE to a ZERO.

The phase displacement of an ON period for a given gate drive waveform with respect to its respective timing waveform is determined by the magnitude of I.sub.R. This phase displacement is commonly called the firing angle and may, theoretically, rage over 180.degree.. For practical purposes, the range is typically limited to about 150.degree. to assure proper commutation of the power thyristors in the converter. So-called rectification and inversion end stops are introduced, as explained hereinafter, in order to constrain the maximum advance nd retardation of a given firing angle to about 10.degree. and 160.degree. respectively. The end stops are effected by appropriately clamping the maximum and minimum values of the analog reference within the Reference Amplifier 35 and consequently limiting the range over which a comparison can be made from line 17 between the timing waveforms and the output of the reference amplifier.

Alignment of the three-stage counter 20 with the reference wave v.sub.AB is required in order to obtain proper output gate drive waveforms. This is achieved by the set gate 63.

FIG. 3 shows in more details the phase locked controller 26. The digital counter 9 is shown as a 10-stage digital counter consisting of 10 flip-flops A.sub.1 - A.sub.10. The number of flip-flops in the digital counter is prescribed by the desired accuracy of the control. An accuracy of 1% of full converter output voltage is desired for this particular application of the invention. The relationship between converter output voltage and firing angle, .theta., is E.sub.o = E.sub.MAX cos .theta. (for continuous current operation) The maximum sensitivity is in the region where .theta. = 90.degree. .

It follows that 0.5.degree. control resolution for .theta. will provide in the worst case, an accuracy for the converter output voltage of (cos 89.5.degree. - cos 90.degree.) .times. 100% = 0.87%. The digital counter is conveniently designed to have seven bits for each 60 electrical degrees thereby to afford a resolution of 60/2.sup.7 = 60/128, thus smaller than 0.5.degree.. The first seven flip-flops, A1 - A7, of FIG. 3 are connected as a conventional serial divider. Flip-flops A8 and A9 perform a divide by three function in order to permit identification of each of the three phases and A10 divide by two operation in order to identify each polarity. As a result A1 through A9 perform for each phase a cyclic operation every 180.degree. at a rate of 120Hz (for a 60 Hz supply frequency) and A10 discriminates between half cycles of the 60 Hz output. This counter, when driven by the N pulses of the synchronized clock, will output a digital representation of a time interval which is synchronized with the supply frequency. The outputted digital count is divided into segments of 60.degree. which are multiplexed to develop a balanced three-phase output as will be described hereinafter in relation to the ramp generator 13.

The phase locked digital device 26 will now be considered in detail by reference to FIG. 3.

A first feature is the generation of a synchronization pulse 6 by the zero-crossing detector 5. With the line-to-line voltage V.sub.AB as reference wave, a reference voltage is derived via an isolation transformer T.sub.1 and a phase shifting network R.sub.1, C.sub.1. The reference voltage is sinusoidal and lags by 60.degree. the line-to-line voltage V.sub.AB. Zero-crossing is detected when the reference voltage crosses zero in the positive direction. At this point the counter 9 is set via line 12 to a state where all outputs of flip-flops A.sub.1 - A.sub.10 are ZEROS.

Transistors Q.sub.1, Q.sub.2 and the associated components form a one-shot oscillator which is triggered by each negative going zero-crossing of the base voltage of Q.sub.1. R.sub.1 and C.sub.1 are selected so that the voltage V.sub.c1 between terminals of capacitor C.sub.1 lags -V.sub.AB by slightly more than 60.degree. with the loading on R.sub.2 due to V.sub.C1. R.sub.1, R.sub.2, R.sub.3, C.sub.1 and P.sub.1 are precision components with low thermal drift coefficients. When V.sub.c1 is sufficiently positive Q.sub.1 is saturated and Q.sub.2 is blocking. As a result the logical state on the collector of transistor Q.sub.2 is a ONE. As V.sub.c1 approaches zero, while decreasing, transistor Q.sub.1 transfers to a blocking state and Q.sub.2 saturates for a period of about 0 microseconds. Accordingly the logic state on line 12 is now ZERO. As a result, the reset terminals of J-K flip-flops A.sub.1 - A.sub.7, A.sub.8, A.sub.9 and A.sub.10 are held at a logic zero forcing the counter to the desired state. Potentiometer P.sub.1 is adjusted so that the transfer of Q.sub.1 to a blocking state, thus resetting the counter, occurs 60.degree. after -V.sub.AB crosses zero.

The synchronized pulse resets all the counter stages to zero and forces transistor Q.sub.3 to block for a 50 microsecond period. The voltage controlled oscillator 7 is initially set into oscillation as a result of the .+-. 15 volt power supply on lines 26, 27 being applied by field transistor Q.sub.9, and a pulse is generated which is amplified by transistor Q.sub.8. The initial voltage on capacitor C.sub.2 is zero and consequently the oscillator formed with transistors Q.sub.7, Q.sub.8 operates at a frequency lower than the desired synchronous frequency of 128 .times. 6 .times. 2f = 1.536 .times. 10.sup.3 f, where f is the supply frequency (60 Hz). With the oscillator operating at a subsynchronous frequency the counter will be running slow with respect to the supply frequency. Consequently, when the synchronized pulse on line 6 causes transistor q.sub.3 not to conduct, flip-flop A.sub.10 will exhibit a ONE on line 11, while A.sub.2 and/or A.sub.3 will have ZERO. Therefore, capacitor C.sub.4 is being charged from line 26, via diodes CR3, and CR11 or CR12. As a result Q.sub.5 will produce a current proportional to the voltage on capacitor C.sub.4 which will charge C.sub.2 during the time interval that Q.sub.3 is blocking. The additional voltage on C.sub.2 will cause the collector current of Q.sub.6 to increase and consequently shorten the conduction period for Q.sub.8 in the oscillator. As long as the counter continues to operate at a subsynchronous frequency, additional charge will be added to capacitor C.sub.2 upon each occurrence of a synchronized pulse. The voltage on C.sub.2 will increase until the resultant increases in Q.sub.6 collector current and oscillator frequency reach steady state synchronous operation. if V.sub.c2 increases too much the frequency of the oscillator will drive the counter faster than the supply frequency. This causes A.sub.10 to reach a zero state before the synchronized pulse occurs and C.sub.4 to discharge before Q.sub.3 assumes a blocking state. Thus, no charge will be added to C.sub.2 during the synchronized pulse. The constant load on V.sub.C2, R11 and R12, will cause V.sub.C2 and the oscillator frequency to decrease slightly until a steady state mode of operation is reached. The steady state operating condition exists and voltage V.sub.C2 has a quiescent value when the amount of charge added to capacitor C.sub.2 during the duration of the synchronized pulse equals that discharged through R11 and R12 during the remainder of the cycle. The circuit is designed so that the voltae remainding on C.sub.4, during its discharge after flip-flop A.sub.2 and A.sub.3 have each assumed the state ONE and while Q.sub.3 is blocking, produces the necessary current from Q.sub.5 to maintain the proper voltage on C.sub.2.

Steady state synchronous operation is reached after a period of about one second following the application of the .+-. 15 volt supply 28, 29. During synchronous operation the relative conduction periods of Q.sub.7 and Q.sub.8 in the oscillator are such that the voltage on C.sub.7 never reaches the peak point voltage of field effect transistor Q.sub.9, and Q.sub.9 is inactive.

Referring to FIG. 4A the circuitry of ramp generator 13 will now be described in detail.

A series of transistor, switches Q.sub.10 through Q.sub.22 are controlled by the respective outputs A.sub.1 - A.sub.9, A.sub.8 and A.sub.9 of flip-flops A.sub.1 - A.sub.9, as shown. Switches Q.sub.17, Q.sub.18 combine with Q.sub.10 - Q.sub.16 to define waveform i.sub.A, i.sub.A ', switches Q.sub.19, Q.sub.20 combine with Q.sub.10 - Q.sub.16 to define waveform i.sub.B, i.sub.B '. Similarly Q.sub.21, Q.sub.22 are affected with Q.sub.10 - Q.sub.16 to waveform i.sub.C, i.sub.C '. The resulting composite saw-tooths are shown in FIG. 5B as curves k, l, and m. Appropriately weighted resistors R45-R71 associated with the outputs of these transistors derive from the +10 volt regulated supply on line 28 currents in a ladder of respectively weighted magnitudes proportional to the digital significance of flip-flops A.sub.1 through A.sub.9. These currents for each ladder are summed up to develop the sets of precision digitized ramp timing waveforms i.sub.A, i.sub.B, i.sub.C indicated in FIG. 2. The circuitry presents several features which assure a high quality for the ramp waveform. Speed-up capacitros C.sub.9 - C.sub.19 and shunting resistors R26-R38 contribute to a fast switching of transistors Q.sub.10 - Q.sub.22. Also, resistors R40-R44, along with shunt FET' s Q.sub.24 and Q.sub.25, minimize the interaction between the three outputs due to the potentials developed across the anti-parallel diode networks CR28-CR33 which clamp the voltages developed when (i.sub.A - I.sub.R), (i.sub.B - I.sub.R) and (i.sub.C - I.sub.R) are not zero. Transistors Q.sub.24 and Q.sub.25 conduct when Q.sub.15 and Q.sub.16 block, respectively, and vice versa when transistors Q.sub.15 and Q.sub.16 are conducting. A forced gain of about 0.5 is used for each of the transistors Q.sub.10 and Q.sub.22 in order to limit the collector-emitter saturation voltages to a typical level of 20 mV which is 0.2% of the 10V reference voltage.

With each ladder of current is associated a switch (S.sub.A, S.sub.B, or S.sub.C) controlled by a signal G.sub.A, G.sub.B or G.sub.C, performing within multiplexer 15 the function of selecting a corresponding ramp waveform. These switches consist of FET devices Q.sub.26 - Q.sub.28 connected at the outputs of respective resistor networks. They conduct individually and in a sequential pattern as prescribed by their gate drive wave-forms G.sub.A, G.sub.B, G.sub.C. The generation of the gate drive wave-forms is discussed hereinafter. The output voltage e.sub.1 on line 16 to the Analog Comparator 18 is representative of the difference between the reference current i.sub.R and the timing waveform current as selected by the conducting switch S.sub.A, S.sub.B or S.sub.C.

The operation of ramp generator 13 in relation to digital counter 9, can best be understood by reference to FIG. 5A in which:

Curve (d) represents the serrated saw-tooth generated when transistors Q.sub.10 - Q.sub.16 are successively switched ON and OFF under digital control from counter 9. As a result the sums of the currents flowing through parallel resistors R45-R65 add up to form the curve represented by d in FIG. 5A. The digital counter includes 128 digital combinations from the seven flip-flops A.sub.1 to A.sub.7. Therefore, each serrated saw-tooth on curve d has 128 steps. When all the resistors are switched in parallel the maximum current is I.sub.1, as determined by the regulated 10V source on line 28.

Generator 13 also includes three pairs of transistors, namely Q.sub.17 - Q.sub.18, Q.sub.19 - Q.sub.20 and Q.sub.21 - Q.sub.22 which are associated by pairs with the respective switches S.sub.A, S.sub.B, and S.sub.C. Q.sub.17 is controlled by output (A.sub.8) from flip-flop A.sub.8. Q.sub.18 is controlled by output (A.sub.9) from flip-flop A.sub.9. Q.sub.19 is controlled by inverted output (A.sub.8) from flip-flop A.sub.8. Q.sub.20 is controlled by output (A.sub.9) from flip-flop A.sub.9 and A.sub.8 from flip-flop A.sub.8. Q.sub.21 is controlled by inverted output (A.sub.9) from flip-flop A.sub.9 while Q.sub.22 is controlled by both outputs (A.sub.8) and (A.sub.9) from flip-flops A.sub.8 and A.sub.9 respectively. Curves e to j on FIG. 5A show the time relation between the periods of conduction of transistors Q.sub.18, Q.sub.17, Q.sub.19, Q.sub.20, Q.sub.22 and Q.sub.21 respectively. The currents represented by each pulse has an amplitude of I.sub.1. The vertical angle represented by each of the saw-tooths of curve d is 60.degree.. The pulses shown by curves e to j last either 60.degree. (Q.sub.17, Q.sub.20, Q.sub.21) or 120.degree. (Q.sub.18, Q.sub.19, Q.sub.22). Operation on phase A for the positive polarity (TA) in relation to switch S.sub.A is illustrated by the combination saw-tooths 1, 2, 3 of curve d and the first pulse of curves e and f. This results in a saw-tooth i.sub.A shown by curve k. The pulses when added up to the saw-tooth of curve d, generate a total current which decreases by very small steps continuously from 3I.sub.1 to zero over an 180.degree. electric angle.

When current pulses of curves g and h are flowing through respective transistors Q.sub.19, Q.sub.20, concurrently with saw-tooth 2 of curve d, a saw-tooth current i.sub.C ' is being generated regularly decreasing from 3I. This saw-tooth is initiated 60.degree. after the intiation of saw-tooth i.sub.A. After another phase shift of 60.degree., the saw-tooth current i.sub.B is generated in the same fashion, then followed by saw-tooth i.sub.A ' , and so on until all the saw-tooths i.sub.A - i.sub.C ' have been successively generated.

Referring to switches S.sub.A, S.sub.C, S.sub.B of FIG. 4A which include FET devices Q.sub.26 - Q.sub.28, respectively controlled by gate signals G.sub.A, G.sub.C, G.sub.B, it is observed that the currents from the three phases i.sub.A, i.sub.C, i.sub.B are in opposition to parallel reference currents I.sub.R derived on parallel resistors R75-R77 from a reference voltage -E.sub.R. Anti-parallel diodes CR28, CR29, CR30, CR31, CR32, CR33 connected to ground on one side and to the junction points of the opposite current paths (i.sub.A, I.sub.R ; i.sub.C, I.sub.R and i.sub.B, I.sub.R) establish a potential at one end of the associated switch depending on the current differences .vertline.i.sub.A - I.sub.R .vertline., .vertline.i.sub.C - I.sub.R .vertline. and .vertline.i.sub.B - I.sub.R .vertline.. When the FET device is gated, a signal e.sub.1 is generated on line 19' at the other end of the FET device (Q.sub.26, Q.sub.27 or q.sub.28) which is the comparison signal used by the analog comparator 18. When e.sub.1 is equal to zero, the comparator generates the firing control signal in relation with the phase corresponding to the gating signal G.sub.A, G.sub.C or G.sub.B. Counter 9 recurrently selects i.sub.A i.sub.C ', i.sub.B, i.sub.A ', i.sub.C, i.sub.b ' and so on. Then, multiplexer 15 is controlled by one of the lines 60, 61 or 62 to have transitions at .alpha..sub.A, .alpha..sub.C ' , or .alpha..sub.B etc. Conduction of the fired rectifier extends between two successive such transitions along the curve k, l or m.

The schematic diagram for this section is shown in FIG. 6. The analog comparator section includes a high speed differential voltage comparator, a pulse generator, and the control circuitry for switches S.sub.A, S.sub.B, and S.sub.C of FIG. 4A. The input to the voltage comparator on line 16 is the voltage e.sub.1 derived as shown in FIG. 4A. e.sub.1 is respectively proportional to (i.sub.A - I.sub.R), (i.sub.c ' - I.sub.R), (i.sub.B - I.sub.R), etc. depending on the states of S.sub.A, S.sub.B and S.sub.C. Effectively e.sub.1 is > O when (i.sub.A - I.sub.R) > O, and < O when (i.sub.A - I.sub.R) < O while S.sub.A is conducting. A similar relation exists for the period when S.sub.C, or S.sub.B, is conducting. A matched pair of MOS transistors, Q.sub.29, provides a very high impedance to relatively low impedance transfer function with negligible offset voltage to suitably drive the voltage comparator without adversely loading e.sub.1. The output of the voltage comparator 18 drives Q.sub.34 into saturation when e.sub.1 is positive and into a blocking state when e.sub.1 is negative. About 10 microsecond after Q.sub.34 transfers from a saturated to a blocking state, capacitor C.sub.20 is being charged sufficiently to cause a programmable unijunction transistor (PUT) Q.sub.36 to fire. As Q.sub.36 fires, Q.sub.35 saturates producing a trigger pulse on line 19 that advances the state of the 3-stage counter (Q.sub.X, Q.sub.Y, Q.sub.Z) by one step.

The least significant change in e.sub.1 must be greater than the sensitivity of the voltage comparator which is in this case about 3 mV. The component values used in the embodiment are such that the minimum change in e.sub.1 is about 12 mV.

The three-stage counter 20 is comprised of J-K flip-flops 40, 41 and 42. Flip-flops 40 and 41 perform a divide by three function and the flip-flop 42 performs a divide by two operation in the same manner as A.sub.8, A.sub.9 and A.sub.10 in the digital counter. Six discriminate states are developed in this counter which are used to:

1. determine which timing waveform i.sub.A, i.sub.B, or i.sub.C is to be compared to I.sub.R at any given instant, and

2. develop the desired gate drive patterns for the converter power thyristors. The three-stage counter 20 operates in a ring-counter mode driven by the trigger pulses on line 19 from the analog comparator. During a steady state condition (when E.sub.R is constant) flip-flops 40, 41 and 42 operate synchronously but out of phase with A.sub.8, A.sub.9 and A.sub.10 as illustrated in FIG. 7. The phase displacement is dependent on the magnitude of the control reference signal E.sub.R which is supplied at 36 as input to operational amplifier Q.sub.37 of reference amplifier 35 (FIG. 6). For E.sub.R = E.sub.MAX, the simultaneous zeros of Q.sub.X, Q.sub.Y and Q.sub.Z start near the beginning of the simultaneous zeros for A.sub.8 A.sub.9 and A.sub.10 and this represents a firing angle condition of about 10.degree.. For E.sub.R = E.sub.MIN, the simultaneous zeros of Q.sub.X, Q.sub.Y and Q.sub.Z start just before the beginning of the one state for A.sub.10 representing a firing angle condition of about 170.degree.. With E.sub.R = (E.sub.MAX + E.sub.MIN)/2, a firing angle of about 90.degree. is created.

NAND gates G.sub..sub..phi.A, G.sub..sub..phi.B, G.sub..sub..phi.C, G.sub..sub..phi.A ', G.sub..sub..phi.B ', and G.sub..sub..phi.C ' of FIG. 6 decode the states Q.sub.X, Q.sub.Y, and Q.sub.Z of flip-flops 40, 41, 42 to obtain a set of six control waveforms as illustrated in FIG. 7. These exhibit the phase dependency of Q.sub.X, Q.sub.Y and Q.sub.Z on E.sub.R.

The reference amplifier 35 is comprised of operational amplifier Q.sub.37, emitter-follower Q.sub.38, and the associated components indicated in FIG. 6. The output -E.sub.R ' is a negative voltage proportional in magnitude to signal E.sub.R *. The input voltage E.sub.R normally will vary from 0 volts to about +12 volts. Diodes CR41 - CR44 constrain the magnitude of E.sub.R * to within a range of about =0.7 volts to =10.7 volts. -E.sub.R ' is proportionately limited so that the range of I.sub.R is controlled and end stops for the phase controller are produced. An intentional lag in the dynamic response of -E.sub.R ' to E.sub.R is introduced by capacitor C23 so that -E.sub.R ' will not vary instantaneously. This delay enables the analog comparator to accurately discriminate every crossover that exists during the dynamic response due to a step function change in the input.

The delay is not symmetrical for both directions of response. For increasing values of .vertline.-E.sub.R '.vertline. the delay exponential time constant is approximately R99.sup.. C23 which is about 100 microsecond. As illustrated in FIG. 8 at point t.sub.1, the response in the converter output voltage, e.sub.o, to a rapid increase in -E.sub.R ' is practically instantaneous. An equivalent decrease in -E.sub.R ', at point t.sub.2, results in a converter output response as indicated by the dotted portion of the waveform in line d. A problem arises because the analog comparator accepts the crossover at point 1 on the i.sub.C ' timing waveform as a valid crossover. Furthermore, the subsequent crossovers at points 2 and 3 on i.sub.B and i.sub.A ' are also accepted. The result of these "extra" crossovers is that a 180.degree. reversal in the output of the phase controller has occurred which is not corrected until point t.sub.3 is reached, at which time a reset pulse (to be described later) to counter 20 realigns the phase controller.

A R100.sup.. C23 time constant of about 2 milliseconds delays the negative transient response of .vertline.-E.sub.R '.vertline. as indicated by the solid portion of .vertline.-E.sub.R '.vertline. in line C following t.sub.2. The corresponding desired response of e.sub.o is illustrated by the solid portion of line d. Line e shows the gate drive patterns which produces the converter response indicated by the solid lines whereas line f shows the gate drive pattern for the dotted line response.

Transistor Q.sub.39, NAND gate 63 and the associated components perform a set function which properly aligns the Q.sub.X, Q.sub.Y and Q.sub.Z counter. This counter is capable of operting in a mode where Q.sub.Z would be 180.degree. out of phase with its proper alignment since the selection of timing waveforms for the analog comparator is dependent only on the states of Q.sub.X and Q.sub.Y. When the magnitude of .vertline.-E.sub.R '.vertline. is sufficiently low Q.sub.39 assumes a blocking state such that when e.sub.s ', which occurs simultaneously with e.sub.s for the 10-stage digital counter, momentarily assumes a one state, and an output pulse from set gate 63 (from a one to a zero back to a one) is produced on line 23b. This pulse sets flip-flops 40, 41 and 42 of the ring counter 20 into the desired states if they are not already there at that instant. As the magnitude of -E.sub.R ' increases the reset pulse from set gate 63 must be prevented in order not to interfere with the proper operation of the circuit. Thus, when .vertline.-E.sub.R '.vertline. is greater than a certain level, Q.sub.39 saturates and forces the output of set gate 63 to remain in the ONE state.

The control circuit 32 for selector switches S.sub.A, S.sub.B, and S.sub.C of FIG. 4 is shown in FIG. 6. When the potential Q.sub.Y of flip-flop 41 corresponds to a ONE state (>6V) transistor Q.sub.33 is cut-off so that the voltage at G.sub.A is -15V which holds Q.sub.26 (S.sub.A in FIG. 4A) in a blocking state. As Q.sub.Y goes to the zero state (<1V), Q.sub.33 conducts pulling G.sub.A up to a potential of about -0.2V which enables Q.sub.26 to conduct. Q.sub.31 and Q.sub.32 act similarly to control the conduction of Q.sub.28 and Q.sub.27 (S.sub.B and S.sub.C. See FIG. 4A. Since only one of Q.sub.X, .beta., and Q.sub.Y is at a zero state at a given time, only one of S.sub.A, S.sub.B, or S.sub.C are able to conduct during that period.

If an analog reference signal is supplied an A/D converter is employed to convert the analog reference signal into a digital reference signal. A block diagram of the digital phase controller is shown in FIG. 9. The synchronized clock 60 is equivalent to the combination of the zero-crossing detector 5 and the variable frequency oscillator 7 of FIG. 1. The 7-stage counter 61 and the 3-stage counter 62 together form a ten-stage counter 100 equivalent to the digital counter 9 of FIG. 1. As in FIG. 1, the most significant digit of the 3-stage counter 62 generates the Nth pulse on line 11 which serves to synchronize the clock pulses at the output on line 8. Also on FIG. 9 a set gate 63 is provided responsive to the synchronizing pulse on line 23a to generate a signal on line 23b for aligning the ring counter 20 which controls the distributor and gating circuit 24. The main difference here resides in that comparator 118 of FIG. 9 is a digital comparator whereas comparator 18 of FIG. 1 is analog. As in FIG. 1, and according to the present invention, the comparator triggers the ring counter 20. Ring counter 20 establishes via lines 21, 22 a concordance between its own digital state and the state of the multiplexer so as to insure tht the proper phase selection is made at the time of reading the digital output of the 3-stage counter 62. The selected waveform is digital and appears on lines 116a from the 3-stage counter 62 and on lines 116b from the 7-stage counter 61. Lines 116a and 116b correspond to line 16 of FIG. 1. The digital count on lines 116a, 116b is compared with the reference digital count 117 in the digital comparator 118. The triggering signal is generated on line 19.

In the embodiment of FIG. 9 the digital reference is obtained after conversion from an analog reference. The A/D converter is comprised of a high-speed clock 50, a 9-stage counter 51, level amplifiers 52, an analog comparator 53, and a shift register 54. The high-speed clock 50 drives the 9-stage counter 51 at a rate significantly higher than that of the synchronous clock 60. The level amplifiers 52 produce an analog equivalent of the state of the 9-stage counter 51. Whenever the output of the level amplifiers becomes less than the analog reference the analog comparator produces a hold pulse which stops the high-speed clock 50 and momentarily retains the 9-stage counter 51 in a fixed state equivalent to a comparison between said counter state and the analog reference. During the hold period the information represented by the state of the 9-stage counter is transferred to the shift register when a gate is released by the analog comparator. Thereafter, the gate is "closed" to retain the shift register in a fixed state as a reset signal is being produced to set the 9-stage counter in its "starting" state. After this is accomplished, the hold on the high-speed clock is released and the A/D converter proceeds to make another comparison. Following each comparison the information in the shift register is updated in order that the output of the shift register be representative of the analog reference existing at that instant and such representation is held until the next comparison is to be made.

Functionally, the digital phase controller of this second embodiment operates in the same manner as the hybrid analog digital phase controller of the first embodiment. The synchronous clock 60, the 7-stage counter 61, and the 3-stage counter 62, respectively perform the same functions as the synchronized counter 26 in the hybrid analog digital phase controller of FIG. 1. The 3-stage counter 62 and distributor 24 also operate in the same manner as did their counterparts. There is no similarity however, in how the timing waveforms are produced, compared with synchronous counter 26 since here the timing waveforms are digital and are compared to the digital reference directly by the digital comparator 118. As each comparison is made by the digital comparator 118 a trigger pulse is produced which advances the 3-stage counter 62 and causes multiplexer 15 to set up the next "digital" timing waveform and appropriately changes the output of distributor 24.

FIGS. 10A and 10B show the circuitry for the high-speed clock 50, 9-stage counter 51, level amplifiers 52, analog comparator 53, and shift register 54.

The high-speed clock 50 consists of Q.sub.17 - Q.sub.19, NAND gate Q.sub.16, and associated components. Q.sub.17 and Q.sub.19 comprise a Schmidt trigger which is forced to oscillate due to the negative feedback from Q.sub.18. When Q.sub.19 and Q.sub.18 are blocking, Q.sub.17 conducting, the voltage on the capacitor C.sub.13 increases until Q.sub.17 is cut off. As Q.sub.17 cuts off Q.sub.19 and Q.sub.18 conduct forcing the capacitor voltage to decrease until Q.sub.17 turns back on again. As Q.sub.17 - Q.sub.19 oscillates and with e.sub.1 mormally at a potential of about +11V, a train of trigger pulses is produced on line 96 serving as a clock for the 9-stage counter of FIG. 10B.

The 9-stage counter 51 and level amplifiers 52, as shown in FIG. 10B, are basically the same as in the first embodiment and operate in much the same manner. (A tenth stage on the counter is omitted since the function of discriminating between half cycles is not required in the A/D converter.) Reference is made to FIG. 11 to describe the operation of the analog comparator 53. i.sub.1 appearing on line 94 (FIG. 10A) is an analog representation of the instantaneous state of the ring counter. With i.sub.1 >I.sub.R the input voltage to the analog comparator amplifier, Q.sub.11 in FIG. 10A is such that the output of Q.sub.11 is negative. Correspondingly, Q.sub.12 is in a blocking state. The counter continues operating until at t.sub.1, i.sub.1 becomes less than .vertline.I.sub.R .vertline. and Q.sub.11 output goes positive. This turns Q.sub.12 ON and forces the clock output of Q.sub.16 to hold in a one state stopping the counter. A small amount of regenerative feedback is provided through R26 to assure that Q.sub.11 output remains positive. About 4.mu. sec later at t.sub.2, C.sub.11 has discharged so that the output of emitter follower Q.sub.13 enables the state of the digital counter to be transferred via transfer gate line 120 to the shift register comprised of Q.sub.20 - Q.sub.22. At the time t.sub.3, C.sub.10 has discharged sufficiently to cause the output of Q.sub.14 to transfer to a one state which returns the transfer gate (Q.sub.13) to a closed condition. Later, at t.sub.4, C.sub.12 will have charged sufficiently to transfer the output of Q.sub.15 to a zero state which resets the counter. As the counter is reset i.sub.1 on line 94 (FIG. 10A) becomes >.vertline.I.sub.R .vertline. forcing Q.sub.11 and Q.sub.12 to return to a negative output and an OFF state respectively. At t.sub.5, Q.sub.14 returns to a zero state forcing Q.sub.15 to a one state which releases on line 95 the reset to the counter and initiates the start of another comparison. The entire process occurring between t.sub.1 and t.sub.5 takes about 30 microseconds.

The rate at which comparisons are made by the analog comparator depends upon the magnitude of I.sub.R as illustrated in FIG. 12. The larger the magnitude of I.sub.R the greater the rate of comparison. The minimum comparison rate is about 1.4 kHz and occurs when I.sub.r is minimum. A maximum comparison rate for I.sub.R MAX is about 10 kHz.

The synchronous clock, 7-stage counter, and 3-stage counter are the same as in the first embodiment, except that a pre-counter stage 91 having outputs A.sub.o, A.sub.o has been inserted between the clock output and counter input, as schematized in FIG. 9. The additional counter 91 is used in the operation of digital comparator 118. To obtain the same clock rate for the A.sub.1 - A.sub.10 counter stages the synchronous clock is modified to produce an output frequency twice that used in the previous system.

Diagrams of the circuitry of the digital comparator 118, multiplexer 15, 3-stage counter 62, and distributor 24 are shown in FIGS. 13 and 14. The digital comparator is comprised of two sections. The first section (FIG. 10C) compares the first seven bits of the digital reference with those of the 7-stage counter. The net output of the 7-stage counter is a digital timing waveform analogous to that of curve d in FIG. 5A. The equality of the state of this counter to a particular state of the first 7 bits (D1-D7) of the digital reference defines a firing angle within a given 60.degree. segment. The particular 60.degree. segment which is needed to complete the discrimination of a particular firing angle (within a 180.degree. range) is prescribed by the last two bits of the digital reference. The multiplexer 15 and the section of digital comparator indicated in FIG. 10E perform the desired comparison between these two most significant reference bits and the digitalized timing waveform. The multiplexing performed within such selector-digital comparator effectively develops three timing waveforms from the primary timing waveform directly obtained from the 7-stage counter and 3-stage counter. The state of 3-stage counter Q.sub.M, Q.sub.N, and Q.sub.P (FIG. 10D) determines which digitalized timing waveform is being compared to the digital reference. The distributor 24 (FIG. 10E) decodes the states of Q.sub.M, Q.sub.N and Q.sub.P to produce the indicated thyristor gate drive signals.

The 7-stage comparator 61 (NAND gates G1-G19, G1-G7) of FIG. 10C produces a zero output from G9 whenever the digital count of the synchronous 7-stage counter (A1-A7) is less than that represented by the first 7 bits of the digital reference (D1-D7). When the digital count of A1-A7 is greater than or equal to that of D1-D7 the output of G9 is a one. The output of G29 for the digital comparator 118, in FIG. 10E, is dependent on the digital reference signal D8-D9 and the state of the digital timing waveform prescribed by the selector. The dependency is as follows:

1. For D8 and D9 defining a firing angle between 0.degree. and 60.degree., G29 is a one for the timing waveform being within the 0.degree. 14 120.degree. range and G29 = 0 for the timing wave-form being within the 120.degree. 14 180.degree. range.

2. For D8 and D9 defining a firing angle between 60.degree. and 120.degree., G29 = 1 for the timing waveform being within the 60.degree. - 180.degree. range and G29 = 0 for the timing waveform being within the (0.degree. - 60.degree.) range.

3. For D8 and D9 defining a firing angle between 120.degree. and 180.degree. G20 = 1 only for the timing waveform being within the 120.degree. - 180.degree. range. A comparison between the timing waveform and digital reference is made when both G9 and G29 outputs are ones. With both G9 and G29 ones the high frequency pulse train of A.sub.o produces a trigger pulse output from line 10 (FIG. 10C) which advances the Q.sub.M, Q.sub.N, and Q.sub.P counter one step (FIG. 10D). This sets up the next timing waveform and appropriately advances the distributor to produce another gate drive pulse. The oncoming timing waveform being less than the digital reference causes either G9 or G29 or both to return to zero states which prevents another G20 trigger pulse from being produced until another comparison is obtained. Capacitors C.sub.23 and C.sub.24 in FIG. 10C filter out unwanted spikes which occur during the operation of the comparator.

The set gate 63, along with the end stop circuitry shown in FIG. 10D properly aligns the 3-stage counter Q.sub.M, Q.sub.N, and Q.sub.P. The analog reference signal E.sub.REF varies between 0 and -15V. For E.sub.REF between approximately 0 and -2.5V the resultant firing angle of the phase controller is between 150.degree. and 180.degree.. With E.sub.REF within this range Q.sub.32 conducts forcing G38 into a one state and the output 23b of set gate 63 is permitted to respond to the e.sub.S ' signal on line 23a developed by the crossover detector of FIG. 3. With the output of set gate 63 active, Q.sub.M, Q.sub.N, and Q.sub.P are set into properly aligned states. However, as E.sub.REF exceeds -2.5V in the negative direction, Q.sub.32 and G38 reverse their states and G.sub.SET becomes inactive so that the phase controller is not adversely effected by e.sub.S ' as the firing angle advances.

End stops for the phase controller are obtained by limiting the minimum and maximum values of E.sub.REF * on line 93 (FIG. 10A). The setting of potentiometer P2 limits the minimum absolute value of E.sub.REF *. The corresponding firing angle of the phase controller prescribed by ##EQU1## fixes the inversion end stop. Diodes CR65-CR67 limit .vertline.E.sub.REF .vertline..sub.MAX to about -14.3 volts and fixes the maximum value of I.sub.R. For an I.sub.R corresponding to a E.sub.REF * = -15V resulting in a firing angle of 0.degree., a rectification end stop of .about..7/15 .times. 180.degree. .congruent. 8.4.degree. is established. The "rectification" end stop may be changed by suitably changing R27.

The dynamic response of this phase controller is predominately determined by the conversion rate of the A/D converter. The most adverse transient response condition occurs when a step function change from a fully advanced firing angle to a fully retarded firing angle is required. In this case the A/D converter takes about 0.6 msec to effect the change. This length of time is sufficiently short that it produces no noticeable delay in the response of the system.