Load Commutated Inverter Gating Control System and Motor Drive With Such Control System

The present invention relates to a digital gate pulse generator for the control of thyristors, to static inverter and/or converter control with such a digital gate pulse generator, and to control and regulation of a motor drive, in particular of the synchronous motor type, embodying static control through such a digital gate pulse generator.

More specifically, the invention relates to a digital gate pulse generator which is particularly adapted to microprocessing, and which can be integrated in the microprocessing treatment of a regulation and control loop through an inverter, or converter system, as can be formed for speed and torque adjustment in a motor drive. The digital gate pulse generator according to the present invention is particularly applicable to a current-fed inverter and control of the thyristors thereof which are load commutated.

The invention lends itself particularly to thyristor control under varying frequency on the AC lines and is therefore well adapted to speed control of a synchronous motor drive as well as to power conversion through static-controlled frequency changers.

The invention will be described for illustration purpose in the context of a current-fed static-controlled synchronous motor drive. The digital pulse generator according to the invention is part of a control loop including the thyristors of the control system of the motor drive. In contrast to the voltage-fed type, in a current-fed motor drive system the amplitude and the frequency of the alternating current that excites the stator windings of the motor are the control parameters. Typically, the motor is energized by an inverter formed of a plurality of controllable electric valves or switching devices (e.g., thyristors) of the type having the ability to hold OFF forward voltage until turned ON by a pulse from a gate pulse generator. The amplitude of alternating current supplied to the motor can be regulated or controlled as desired by adjusting the average magnitude of voltage impressed on the DC side of the inverter, while the frequency of the current is controlled by appropriately varying the switching frequency of the thyristors of the inverter.

A variable speed motor drive involves frequency adjustment of the power supply to the motor in order to regulate speed. In such a motor drive, gating of the static switches which determine the motor power supply parameters at any speed must be operable at varying frequency and through a range extending down to zero motor speed.

In the prior art systems embodying thyristors which are naturally commutated, the firing angle of the thyristors is controlled by reference to a time wave related to the voltage applied to the main electrodes of the thyristor to be turned ON, at any given moment. The generation of such a time wave reference is disclosed, typically, in U.S. Pat. Nos. 4,173,722 and 4,028,609 of R. L. Detering. There, however, only small variations of frequency are contemplated. Therefore, a digital pulse generator uses a digital counter synchronized in phase and frequency with the fundamental voltage sine wave, and a time wave reference is derived with which to determine the firing angle in relation to a digital counter. A phaselocked loop provides compensation for any change in the fundamental frequency of the AC power supply.

When the motor drive includes a synchronous motor supplied by an inverter, variable speed control through firing angle adjustment of the inverter thyristor is directly related through the time wave reference to the voltage and frequency parameters of the rotating vector derived on the stator, or the rotor of the machine, since there is an inherent synchronism between the two under steady conditions of operation. Accordingly, it has been proposed to use the motor terminal voltage to synchronize the inverter triggering pulses. See H. Le-Huy, A. Jakubowicz and R. Perret, "A Self-Controlled Synchronous Motor Drive Using Terminal Voltage-Sensing," in 1980 IEEE, pp. 562-569. There, the polarity and zero-crossings of the machine voltages are detected by means of terminal sensors from which is derived a speed signal as well as a rotor position signal. Although this prior art technique has been intended to be used as part of a microprocessor-based control system, it lacks the advantage of an all-digital treatment of the information. In particular, three voltage signals are derived and a speed signal is obtained therefrom by a frequency multiplier, the operating frequency range depending upon a counter length, the frequency of a clock and a chosen multiplying factor. These four signals are used to provide a controllable delay angle between the inverter triggering pulse and the machine voltages. Based on linear digital ramp technique the angle control word issued by a microcomputer is converted to a corresponding delay angle. Typically, the 8-bit input control word used there contains mode operation as well as delay-angle information. These are typically defined by the first bit and the remaining 7 bits, respectively, as explained in H. Le-Huy, R. Perret and D. Roye, "Microprocessor Control of a Current-Fed Synchronous Motor Drive" in 1979 IAS 79:29A pp. 873-880. Pulse generation, which is to be implemented either by software or by hardware, is also shown to use a single processor and hardwired logic circuits to convert the CPU commands to appropriate triggering pulses for the converter.

Another approach to firing angle determination and implementation within a control system using microprocessor technique is found in "Digitally Controlled Thyristor Source" by Guy Olivier, V. R. Stefanovic and Mohamed Akhtar Jamil in IEEE 1979, Vol. 1ECI-26 No. 3, August 1979, pp. 185-191. There, the transfer characteristic of a sixpulse thyristor bridge is used and a linear transfer relation between the control signal and the output voltage is sought through a PROM containing a table of an arc cosine curve. The SCR firing pulses are delayed by a time period in accordance with a signal derived from a PI controller in a closed-loop, and the output of the PI controller is fed into the linearization PROM memory which gives a digital equivalent of the desired firing angle. Each time a zero-crossing is detected in the bridge input voltage, one of two counters is started counting up until its output becomes equal to or larger than the desired firing angle, and a firing signal is sent to a ring-counter. This technique is more like that with the aforementioned Detering patents since the problem involved here, with a constantly varying frequency, is not encountered.

Microprocessor-controlled speed regulation in motor drives have been used with motor drives. See for instance the following papers:

"Microprocessor-Controlled Fast-Response Speed Regulator For Thyristorized Reversible Regenerative DCM Drives" in IECI 78 Proceedings--Industrial Applications of Microprocessors, March 20-22, 1978, pp. 216-221 by Kenzo Kamiyama, Azusawa and Miyahara.

"Microprocessor Controlled Inverter-Fed Synchronous Motor Drive" by W. Richter, pp. 161-163, 2nd International Conference on Electrical Variable-Speed Drives, 25-27 September 1979, IEEE Power Division (London).

G. A. Tendulkar, "Measurement of Speed, Position and Acceleration of Electrical Drives in Microprocessor-Based Control System" pp. 171-175, 2nd International Conference IEEE, London, September 1979.

"Control of DC Drives by Microprocessors" by E. Schneider, pp. 603-608, IFAC Symposium on Control in Power Electronics and Electrical Drives by W. Leonhard, Dusseldorf, 1978.

"Design of An Optical Autodaptive Current Loop for DC Motor Realization with a Hybrid Device Including a Microprocessor" by A. Oumamar, T. P. Louis and A. El-Hefnawy, IFAC Symposium, Dusseldorf, 1978.

The Schneider and Kamiyama papers, for instance, are involved with DC motor drives. Therefore they do not call for a direct derivation of an electrical angle related to rotor positioning and independently of speed, e.g., of frequency.

The invention provides for the repeated computation of the firing angle with the use of a microprocessor for the respective thyristors to be turned ON in an inverter, such firing angle computation being independent of the AC frequency at the thyristor terminals and dispensing from the use of any shaft position encoding device when a synchronous motor drive is involved.

Three counters are run from a common clock, two counters being combined to provide a unit count representative of electrical degrees on the AC terminals in relation to two consecutive zero-crossings of the AC voltage at said AC terminals, the third counter being initiated at a chosen instant to count the number of electrical degrees (t.sub.3) remaining in the phase of a thyristor "next" to be fired up to the total number of electrical degrees defining a predetermined firing angle (.alpha..sub.n).

The computation of such remaining number (t.sub.3) of electrical degrees is based upon the computed operative phase in electrical degrees (.phi.) for the "next" thyristor relative to the zero-crossing of the line phase synchronized voltage and to the count (t.sub.1) of electrical degrees required from the computed phase to reach ninety electrical degrees from said line phase synchronized voltage zero-crossing.

FIG. 1 is a schematic representation of the synchronous motor drive system according to the present invention;

FIG. 2 illustrates with curves the operation of the three counters which are part of the gating system of FIG. 1;

FIG. 3 shows in block diagram the insertion of the three counters of FIG. 2 within the gating system of FIG. 1; and

FIG. 4 is the preferred embodiment of the motor drive system of FIG. 1, namely in association with a microcomputer.

Referring to FIG. 1, a synchronous motor drive control system illustrates in block diagram the preferred embodiment of the invention.

The three-phase, 1640 volts, 60 Hz power supply (L.sub.1, L.sub.2, L.sub.3) is converted into a three-phase (A, B, C) variable frequency (f.sub.n) power supply applied to a synchronous motor M coupled to a load. This conversion is achieved by the conventional combination of an AC/DC converter 1, a DC link including a choke CHK and an inverter 2. The AC/DC converter 1 is gated by a gating circuit GC which is controlled by a current controller CCT which is itself responsive to a feedback signal derived from a current sensor at junction J.sub.1 at the input of the converter, and to a current reference provided by the speed and torque controller 6 of the motor drive. The inverter typically may include six thyristors T.sub.1 -T.sub.6 mounted in a bridge across the DC link, half of them in relation to the positive polarity terminal L.sub.A, the other half in relation to the negative polarity terminal L.sub.B, with three output phases A, B, C connected to the motor M.

The invention pertains to the timely generation of gating pulses on lines 10 (GS.sub.1 -GS.sub.6) to the thyristors of the inverter, so as to establish the proper firing angles which determine the operating condition of the motor, irrespective of the frequency f.sub.n.

The distributor and gating circuit 3 applies on the various channels GS.sub.1 -GS.sub.6 the firing pulses at the desired firing angle .alpha..sub.n when timely triggered on line 11 by the pulse triggering time generator 4 according to the present invention. A speed and torque controller 6 is also provided for establishing and regulating the various parameters of the motor drive, such as speed, voltage, frequency, torque, power factor, start-up, acceleration, . . . Thus, the speed and torque controller receives on line 14 a speed reference and on line 15 the line phase voltage V.sub.CA. A microprocessor 5 is associated via bus line 16 with time generator 4 and via bus lines 19 with speed and torque controller 6 for the repeated computation of a.sub.n within controller 6 and of the exact time which will elapse within the firing angle .alpha..sub.n until the firing instant is reached within circuit generator 4. The firing angle .alpha..sub.n required at any given time for thyristor T.sub.n of rank n in the succession of thyristors T1-T6 is provided in degrees as an input on line 12 to the pulse triggering time generator 4. It is the task of microprocessor 5 and pulse triggering time generator 4 to generate on line 11 to gating circuit 3 a triggering pulse with the exact retardation prescribed by .alpha..sub.n, as will be explained now by reference to the curves of FIG. 2 and the block diagram of FIG. 3. The microprocessor also controls via bus lines 18 the control and distribution of the gating pulse to the proper thyristor by circuit 3.

FIG. 2 shows in solid line on a time axis the line-to-line voltage V.sub.CA as measured at junction J.sub.2 (see FIG. 1) between inverter 2 and the motor M across two phases C and A. In a constant or quasi-constant frequency situation, curve V.sub.CA would be used as a time wave reference and from its zero-crossing Z.sub.1 the firing angle .alpha..sub.n would be determined for firing any particular thyristor, such as T1-T6, in succession. However, since the frequency f.sub.n of the motor is essentially variable over a wide range, the time axis does not provide a direct reference to electrical degrees. An analog, or digital, ramp phaselocked to the line could not be used in the gate pulse generator, as in the aforementioned Detering patents, because phase-locked loops will not operate reliably over such a wide range where the frequency changes rapidly. As a matter of fact, the Detering technique could be used to control the thyristors of the AC/DC converter 1, since the frequency is constant there, except for some automatic correction for small frequency changes. Not so with the inverter 2 in the context of a variable speed synchronous motor M. FIG. 2 shows also the commutating voltage, in dotted line, which is applicable to the thyristor T.sub.n which is "next" to be fired. For the sake of clarity, the other commutating voltages are not represented, while the gating pulses are shown to occur at GP.sub.n-2 for the thyristor of (n-2) order, GP.sub.n-1 for thyristor T.sub.n-1 at present in conduction, GP.sub.n being the gating pulse at .alpha..sub.n firing angle for the thyristor T.sub.n which is "next". Similarly the future gating pulses are GP.sub.n+1,GP.sub.n+2 . . . GP.sub.n-1 in a ring fashion.

It is observed that between each thyristor in succession there is a phase shift .phi..sub.n =60.degree. in the example shown in FIG. 1 of six thyristors T1-T6. However, .phi..sub.n in general is also affected by any phase angle shifts introduced by the sensing circuits when attempting to measure directly at point J the line-to-line voltage. Another cause of small error is introduced by the subtransient reactances in the motor, which are affected by the reactances of the windings, the armature current, the motor speed, and the field current. These "errors," added when ascertaining .phi..sub.n, can be determined and/or calculated. With this understanding it will be assumed hereinafter that .phi..sub.n is free from such "errors" and, in the particular example of FIG. 1, it is understood that .phi..sub.1, .phi..sub.2, .phi..sub.3, . . . will be zero, 60.degree., 120.degree. . . . in the successive order of the thyristors. It is apparent that the successive values of .phi..sub.n-2, .phi..sub.n-1, .phi..sub.n, .phi..sub.n+1, . . . are known and may be considered as passing from negative through zero to positive values while going from one thyristor to the next.

With this understanding, for thyristor T.sub.n, for instance as shown in FIG. 2, the firing angle .alpha..sub.n from zero-crossing Z.sub.n on the commutating voltage curve, is a composite of time interval t.sub.1, time interval t.sub.2 and time interval t.sub.3, which time intervals will be explained hereinafter. Also, the firing instant GP.sub.n for thyristor T.sub.n is at (90.degree.+t.sub.2 +t.sub.3) from zero-crossing Z.sub.1 of the line-to-line voltage V.sub.CA, while (.phi..sub.n +t.sub.1)=90.degree..

Referring to FIG. 3, line 15 from junction J.sub.2 where the line-to-line voltage V.sub.CA is sensed, goes to a 90.degree. phase shifter 20 providing on lines 23, 24 a signal which is at 90.degree. phase shift to curve V.sub.CA. A zero-crossing detector 22 provides a negative zero-crossing indicative signal on line 26, and a zero-crossing detector 21 provides a positive zero-crossing indicative signal on line 25, in response to the outputs 23, 24 from filter 20. The line SYNC signal of FIG. 2 illustrates the opposite states which mark such positive and negative zero-crossing points as detected on lines 25 and 26. Upon positive zero-crossing, a first counter C.sub.O is reset by line 26, while 180.degree. later, e.g., upon the negative zero-crossing, a second counter C.sub.1 is reset by line 25. Each timer is counting under a clock signal on line 30 from an oscillator OSC, typically at 100 KHz. Therefore, the SYNC signal of FIG. 2 represents 180.degree. time intervals in units of time (TIME CLK) which last 1/100 millisecond= 10.0 .mu.sec. On the other hand .phi..sub.n and .alpha..sub.n are known in electrical degrees. It is the purpose of the present invention to convert all units into a basic unit which is independent of frequency by converting all "TIME CLK" units into degrees. Since T.sub.i, the period in units of time of the SYNC signal corresponds to 360.degree., t in degrees is:

where t (time) is in clock units.

Counters C.sub.0 and C.sub.1 count from the same initial value when reset and, under the same clock signal of line 30, they count at the same rate. They start, however, 180.degree. apart. Therefore:

where t.degree..sub.c0 and t.degree..sub.c1 are counter values converted in degrees. Also

where t.sub.c0 and t.sub.c1 are in clock units (TIME CLK).

At any moment, the difference between counters C.sub.0 and C.sub.1 provides a count representing 180.degree. in clock signal unit, and counter C.sub.0 beyond the positive crossing detecting point is in fact counting t.sub.c0xn in clock signal units, the instantaneous value of time interval t.sub.2

Therefore, at such instant X.sub.n (see FIG. 2), it is well known that a time interval t.sub.3 remains until the total number of degrees .alpha..sub.n has been reached on the commutating voltage curve. .phi..sub.n is known for thyristor T.sub.n, and t.sub.1 is known since it is (90.degree.- .sub.n). Thus, at instant X.sub.n the count of t.sub.c2p 32 t.sub.3 can be determined as follows: ##EQU1## where after equation (1) and (2) ##EQU2## Then, at instant X.sub.n ##EQU3##

Binary 2's complement fractional rotation has been chosen for performing the necessary mathematical calculations in the microprocessor (typically, the sixteen bit word includes the sign and 15 bits with the binary point just to the right of the sign bit). Thus, ##EQU4##

Referring to FIG. 4, the circuit diagram of FIG. 1 is shown with more detail regarding pulse triggering time generator 4 and speed and torque controller 6. Counters C.sub.0 and C.sub.1 schematically shown by block 60, respond to the zero crossings Z.sub.1, Z.sub.n relative to V.sub.CA as sensed from junction J.sub.2 and derived on line 15. Within speed and torque controller 6 are included the speed feedback calculator 6'", the speed controller 6" and the gating angle calculator 6', which are under control from the microprocessor by 19'", 19" and 19' respectively, in the dialogue between microprocessor 5 and controller circuit 6 (bus line 19 on FIG. 1). The gating angle calculator 6' outputs on line 12 the value .alpha..sub.n. Pulse triggering time generator 4 includes a delay calculator 4' and counter C.sub.2, within block 4", which both are monitored and controlled, via 16' and 16", respectively by microprocessor 5. Delay calculator 4' provides the count t.sub.3 and starts counter C.sub.2 at the end of time t.sub.2 to initiate counting of the computed count, thus accumulating a real time t.sub.3. When the count t.sub.3 has lapsed, by line 11 the distributor and gating circuit 3 is triggered.

The hardware organization for performing the necessary computations upon each oncoming thyristor T.sub.n-2, T.sub.n-1, T.sub.n, T.sub.n+1, T.sub.n+2 . . . successively, at each instant such as X, and for triggering a gating pulse when the calculated time interval T.sub.c2p has lapsed, is illustrated in block diagram in FIG. 3. From junction point J.sub.2 and via line 15, the sensed line-to-line voltage signal is passed through the 90.degree. phase shift filter 20. The positive and negative zero-crossing detectors 21 and 22 reset, by respective lines 25 and 26, counters C.sub.0 and C.sub.1, that is at 180.degree. time interval from one another on the time scale. The data counts t.sub.c0 and t.sub.c1 at the rate of the clock signal of line 30 are addressed to the microprocessor by bus B.sub.2 from counter C.sub.0, by bus B.sub.3 from counter C.sub.1 onto a bus interface BI and by bus lines B.sub.7 to the multibus system of a microprocessor module which comprises the microprocessor and its support equipment. The bus interface B.sub.1 also communicates with counter C.sub.2 by bus lines B.sub.4, with an interrupt control circuit 35 by bus lines B.sub.5, and counter C.sub.2 is connected to interrupt control circuit by interrupt line 36. The clock signal of line 30 is also applied to counter C.sub.2. Typically, the microcomputer employs a sixteen bit, high speed, bus compatible microprocessor. It also includes the necessary RAM and PROM memory, system interrupt, timers. The PROM stores the instructions set or program for the entire section system operation, including diagnostics. The microcomputer module is used not only for the computations involved in the gating pulse timing process according to the invention but also in connection with the speed and torque controller 6. Thus, besides the basic thyristor gating and protection, the PROM's are programmed to perform current regulation with limits; speed regulation; system sequencing; fault monitoring; diagnostics; and system communications. The systems information bus conforms electrically and mechanically to the proposed IEEE Standard 796, commonly referred to as Multibus.RTM..

Considering counter C.sub.2 which recurrently is started at times X.sub.n-2, X.sub.n-1, X.sub.n1, . . . for count down of the calculated count t.sub.c2p, at instant GP.sub.n-1 counter C.sub.2 causes, via line 36, when it reaches zero an interrupt control circuit 35 to trigger, by bus line B.sub.5, main bus B.sub.1, and the multibus of the microprocessor, the latter to start the calculations for the next firing stage, GP.sub.n. On the interrupt occurrence the gates of thyristor T.sub.n-1 and T.sub.n-2 (which are the pair of conducting thyristors before the incoming thyristor T.sub.n is to be gated) are enabled, provided no gate pulse suppression is called for. Immediately thereafter, as indicated by a hatched area on FIG. 2, the microprocessor makes the calculations which lead to the value t.sub.c2p of equation (3). In these calculations, the microprocessor first uses the 2's complement method to calculate .vertline.t.sub.c0 -t.sub.c1 .vertline.=Ti/2 in units of "TIME CLK" t.sub.1, t.sub. 2, (t.sub.1 +t.sub.2) and finally t.sub.c2p is calculated. The value t.sub.c2p at instant X.sub.n, based on the instantaneous value of t.sub.2 given by running counter C.sub.0, is immediately loaded in counter C.sub.2 which starts counting down. Time interval t.sub.c2p, thus, lapses concurrently with the count down until an instant at which GP.sub.n must be gated and for which .alpha..sub.n exists on the commutating voltage, as intended. At this very moment from interrupt control circuit 35, by bus B.sub.5, main bus B.sub.1 and bus B.sub.6, the output register 27 is selected, and by line 11 onto the gate output drivers 3, the gating pulse generated by block 33 is applied through a corresponding line 10 onto gate G.sub.n of thyristor T.sub.n. As in the afore-mentioned Detering patents, provision is made for a picket fence. To this effect, block 33 includes both a hard pulse generator and a picket fence generator supporting the ignition after the hard pulse has initiated it.

As is well known, when the motor is running at very slow speed, the line-to-line phase voltage V.sub.CA is very low in frequency and the magnitude of the voltage to be sensed for zero-crossing detection becomes so small that gate pulse phase control becomes impractical. The consequence is that at standstill, in the absence of the line voltage, the synchronous motor is unable to start itself. See H. Le-Huy, R. Perret and D. Roye in a paper entitled "Microprocessor Control of a Current-Fed Synchronous Motor Drive" presented on pages 873-880 in IEEE 1979, IAS79 Vol. 29A. As shown in this article, when not in the running mode, a microprocessor is used to start and accelerate the motor until the line-to-line phase voltage is sufficient, and during starting the thyristors are controlled under auxiliary pulse triggering in a forced commutation way. The Le-Huy, Perret and Roye article is hereby incorporated by reference to shown the state of the art. Referring now to FIG. 3 again, it is observed that when in the "pulse start mode," while counters C.sub.0 and C.sub.1 are not used, counter C.sub.2 provides, from firing instant to firing instant, a time interval Tg which represents the firing cycle through the succession of thyristors T.sub.n-2, T.sub.n-1, T.sub.n, T.sub.n+1, . . . A local oscillator generates pulses gating the thyristor at time intervals Tg such that the frequency of occurrence is raised from a few hertz to a minimum frequency f.sub.m for which the line-to-line phase voltage is sufficient for the running mode to take over.

According to the present invention, the change in frequency during acceleratinon is based on a quasi logarithmic mode by keeping .DELTA.f/f=K.sub.1 a predetermined constant percentage of the frequency, thereby to provide an increasing rate of acceleration. Therefore, from zero up to a minimum frequency f.sub.m acceleration will be accomplished by decreasing the gate-to-gate time interval Tg by a constant amount K.sub.1. In addition, still according to the present invention, from the frequency f.sub.m up to a maximum pulse mode frequency f.sub.M, acceleration is accomplished by increasing the gate-to-gate time interval Tg so as to keep hertz/second acceleration constant equal to K.sub.2, another constant. This will keep the torque requirement essentially constant in this range. f.sub.M will be sufficient to acquire a sync signal between motor and inverter in the running mode.

The implementation from zero to f=f.sub.m is based on the calculation by the microprocessor of Tg in accordance with the formula:

Accordingly, the value Tg.sub.n is loaded into counter C.sub.2 at instant t.sub.n-1 which precedes by Tg.sub.n the incoming firing of T.sub.n. Counter C.sub.2 counts down and when it reaches zero by line 36 an interrupt occurs which as earlier explained will cause firing of T.sub.n by interrupt control circuit 35 and outer register 27. Since Tg is decreasing at each successive stage, the frequency of occurrence of the interrupts is increasing, and the motor, through inverter 2, is progressively accelerated.

When f.sub.m is reached, the algorithm .DELTA.f/.DELTA.t=K.sub.2 for linear acceleration is applied, where K.sub.2 is in hertz/sec. Thus, the change in frequency from the end of line cycle (i-1) to the end of cycle i would approximate ##EQU5## where f.sub.i =average frequency during cycle i

f.sub.(i-1) =average frequency during cycle (i-1)

T.sub.i =period of cycle i ##EQU6## If T.sub.i and T.sub.(i-1) are not greatly different, then ##EQU7## If the same logic is applied to gating intervals Tg.sub.n instead of the full line cycles, for linear frequency acceleration:

equation (4) becomes: ##EQU8## where Tg.sub.n =gate interval n

1/6Tg.sub.n =average frequency during interval Tg.sub.n in Hz.

Therefore, the algorithm is: ##EQU9## where K.sub.2 is Hz/sec. and Tg is in seconds. Pulse mode control in the linear acceleration stage is illustrated by the following example where the initial condition is:

The following acceleration steps obtain:

This verifies that operation with the afore-stated mathematical expressions predicting Tg.sub.n based on Tg.sub.(n-1) can be performed with sufficient accuracy.

The following is indicative of a practical method of calculation in the pulse, or acceleration mode, for a synchronous motor drive.

Initially any pair of gates are fired. Also the DC link current is set initially to 60%, and the other current I.sub.F is set at a fixed value, typically 50%. The initial gate interval Tg is loaded into counter C.sub.2, and counter C.sub.2 counts down to zero. The interrupt occurs. Starting at 0.5 hz, the initial value t.sub.c20 is ##EQU10## The clock signal of the oscillator OSC being at 100 kHz, then,

When the interrupt occurs, the current reference is set to zero, the "commutating" flag is set, and the counter C.sub.2 is set to the commutating interval Tg (10 msec). Thus: ##EQU11## On the next interrupt, the "commutating " flag is found to be set. Another routine is used this time to set a new gate pattern for the inverter and initiate the hard pulse. The DC link current reference is set to 60%. The "commutating" flag is reset, and counter C.sub.2 is set to the next gating interval Tg. The interval for both "logarithmic" and linear modes is calculated and the longer one of the two intervals is loaded into counter C.sub.2.

For the "logarithmic" calculation, the method consists in effecting the multiplication

where Tg.sub.n-1 and T.sub.gn are 16-bit integers, K.sub.1 is a 16-bit "fraction," typically in the range 0.900 to 0.999. Since K.sub.1 is always positive, an unsigned integer multiplication becomes most convenient. The result would be in the upper 16-bit answer.

With a linear approach, or "ramp" acceleration in the pulse mode, the method of calculation can be:

The signed integer is multiplied with the answer in the 16 MSB of the result:

Here, the signed integer is multiplied twice with the answer in the 16 LSB and finally,

which involves a simple addition.

Speed Feedback Calculations

Line sync counters C.sub.0 and C.sub.1 per FIGS. 3 and 4.

where T.sub.L is the line period in clock cycles (100 kHz clock).

If line frequency f.sub.1 varies from 2 to 70 Hz, the value .vertline.C.sub.1 -C.sub.0 .vertline.will vary from 1/2.multidot.1/70 to 1/2.multidot.1/2 seconds which, at 100 kHz, is 714 to 12,500 counts.

For a good resolution 11 bits of resolution are used after dividing 714 into a constant assuming the binary 2's complement mathematical method is used with a 16 bit processor. Suppose we divide period (10-15 bits) into a 25 bit constant. The answer would be 15-10bits, which is the resolution that can be measured (no loss of precision in the divide).

Use 12.800.times.10.sup.6 as constant K.sub.s, then: ##EQU12## (The answer is in Hz.times.2.sup.8) ##EQU13## In order to keep ##EQU14## less than 1, each of the fractions is divided by 4 before multiplying ##EQU15## It remains to multiply by 4 to get correct scaling, before subtracting t.sub.clxn.

Then, ##EQU16## where

is the output from the speed and torque controller, with a range from 0 to 1, and

is constant for each gate with a range from -1/2 to +1-1/2. .vertline.t.sub.clxn -t.sub.c2xn .vertline. must be .ltoreq.1/2.times.7FFF.sub.4 if we use 16-bit counters and we do not want the sign of the counter to change. Then t.sub.c0xn will be <7FFF.sub.4 also, since

minimum frequency which can be handled:

where .DELTA.t=period of time clock.

If .DELTA.t=10.0 usec:

This is acceptable.

A typical example:

1 second=186AOH (in units of (1/10.sup.5) second) ##EQU17## It is expected that at 6 Hz, Tg=1/36 second and at 2 Hz/sec accel: ##EQU18##

Let 0.25 seconds=186AOH=10.sup.5

This multiplies Tg values by 4.

Then K.sub.2 must be divided by (1/4).sup.2 =1/16

The calculation now becomes:

This involves a .+-.15 bit multiplication and the answer is in 16 LSB

Here, .+-.15 bit is multiplied by the answer in 16 MSB (namely dividing by 2.sup.16 each multiplication step). ##EQU19##

Now there is a .+-.15 bit multiply, answer in 16 MSB (0.323 based on 7FFF=1).

This involves a simple addition. The answer is in clock times.times.4.

The total involves four multiplies and one addition. Even at 6 Hz, several multiplications will not require much time. There is at least a 30 millisecond time interval per gate in the pulse mode.

In the pulse mode, the only counter required is the 60.degree. delay between pulses. From the above calculation,

Pulse Mode: f.sub.min =3.05/6=0.5086 Hz

This is good enough, because the plan is to start at 0.5 Hz. but the frequency could go down to

because all 16 bits could be used for the delay (no sign).