High Speed Comparator Circuit With Input-Offset Compensation Function

1. Field of the Invention

The present invention relates to a comparator circuit for comparing two signals, and more particularly to a comparator circuit provided with an input offset voltage reducing circuit for compensating for the input offset voltage by making use of the voltage-storing function of capacitors.

2. Description of the Prior Art

In a comparator circuit of this kind, the accuracy of a signal comparison operation is substantially determined by the input offset voltage of an initial stage differential amplifier. For compensating the input offset voltage, it has been performed to charge a capacitor with the offset voltage during a standby period and to subtract the voltage stored in the capacitor from the output voltage of the differential amplifier to generate an offset-free output signal during the comparison period. The offset-free output signal i.e. the result of the comparison is latched by a latch circuit during the subsequent period. Usually, the latching operation of the comparison output signal and the operation of the differential amplifier are conducted alternately, and hence the latch circuit is in operation when the differential amplifier is on standby to latch the output signal which has been amplified in the previous period by the differential amplifier. In the conventional comparator circuit thus far described, the pulse period of a control signal controlling a switch circuit used when the capacitor is being charged with the offset voltage and the pulse period of a control signal controlling the latch circuit are equal but have opposite phases. As a result, the sampling period is determined by the period making the offset voltage compensating circuit set, thus making it difficult to realize a fast operation. If the time period for charging the capacitor with the offset voltage is lengthened, more specifically, the charging operation can be completely achieved to increase the accuracy, however, the sampling period is accordingly extended and its high-speed operation is resultantly lost. However, if the sampling period is shortened to aim at a higher speed, on the other hand, the time period available for charging the capacitor with the offset voltage must be shortened to produce the defect that the accuracy is reduced. This makes it impossible to provide a comparator circuit which operates both at a high speed and with a high accuracy.

It is an object of the present invention to provide a comparator circuit which can operate both at a high speed and with a high accuracy.

In the present invention, a control signal having a shorter period than that of a control signal controlling an offset voltage compensating circuit is used for a latch circuit, and the standby period of a differential amplifier is made sufficiently longer than the period of the control signal for the latch circuit. In the present invention, the latch circuit can be operated several times within the time period during which the input offset of the offset voltage compensating circuit is effectively held in the capacitor, so that high-speed comparisons can be realized that are substantially in proportion to the operating period of that latch circuit.

According to one aspect of the present invention, there is provided a high-speed comparator comprising: a differential amplifier provided with an input offset voltage compensating circuit using a DC restorer of the capacitor-coupling type for compensating an input offset voltage; a latch circuit receiving the output of the differential amplifier; a first generator generating a first control signal controlling the differential amplifier in such a manner that an operating period thereof is at least twice as long as a standby period thereof; a second generator generating a second control signal, which has a shorter cycle period than that of the first control signal, controlling the latch circuit; and a status signal generator informing a peripheral of whether the differential amplifier is on standby or is operating.

According to another aspect of the present invention, there is provided a high-speed comparator circuit comprising two sets of a differential amplifier provided with an input offset voltage compensating circuit for reducing the input offset voltage by making use of the voltage-storing function of capacitors and a latch circuit, in which the two differential amplifiers having the input offset voltage compensating circuits can be operated alternately for sufficiently long periods of time, and by operating the two latch circuits at a high speed in response to the same clock signals, the significant comparison outputs, which are generated alternately by the two latch circuits, are multiplexed so as to apparently eliminate the standby time period so that a series of significant comparison output signals can be generated at a high speed.

According to still another aspect of the present invention, there is also provided a high-speed comparator circuit comprising: a first differential amplifier including an input offset voltage compensating circuit making use of a DC restorer of the capacitor-coupling type and operating in response to a first clock signal; a first latch circuit receiving the output of the first differential amplifier and operating in response to a second clock signal of a higher frequency than the first clock signal; a second differential amplifier including an input offset voltage compensating circuit making use of a DC restorer of the capacitor-coupling type and operating in response to a third clock signal which is in a logically complementary relationship with the first clock signal; a second latch circuit receiving the output of the second differential amplifier and operating in response to the second clock signal; and a multiplexer receiving the outputs of the first latch circuit and the second latch circuit to switch one of them in response to the first clock signal in a switching manner.

FIG. 1 is a diagram of a comparator circuit according to the prior art;

FIG. 2 is a timing chart of the waveforms of the signals used in the circuit of FIG. 1;

FIG. 3 is a block diagram of one embodiment of the present invention;

FIG. 4 is a timing chart of the waveforms of the signals used in the circuit of FIG. 3;

FIG. 5 is a block diagram of a second embodiment of the present invention;

FIG. 6 is a timing chart of the waveforms of the signals used in the circuit of FIG. 5;

FIG. 7 is a circuit diagram of a third embodiment of the present invention; and

FIG. 8 is a timing chart of the waveforms of the signals used in the circuit of FIG. 7.

A prior art comparator circuit is shown in FIG. 1. A signal voltage is applied to an input terminal 1 and a reference voltage is applied to an input terminal 2. A switch 10 is so controlled by a clock signal .phi. shown in FIG. 2(a) that it is turned on during a time period I and off during a time period II. Switches 11, 12 and 13 are controlled by a clock signal .phi. shown in FIG. 2(b). The states of the switches in FIG. 1 are those for the time period II. In this period II, the input terminals of a differential amplifier 30 are short-circuited by the switch 11 and commonly supplied with the reference voltage. At the same time, under this state, the offset voltage of the differential amplifier 30 appears as a voltage difference between output terminals 40 and 41. The switches 12 and 13 are on so that the capacitors 20 and 21 are charged with the voltages at the output terminals 40 and 41, respectively. Data concerning the offset voltage is stored as a voltage difference between the capacitors 20 and 21.

A latch circuit 31 is in standby state during the period I, because the control signal .phi. of FIG. 2(b) is applied to a terminal 50 for controlling its write operation, and latches the offset voltage compensated voltage appearing at terminals 42 and 43 during the period II, and generates a comparison result at its output terminal 3.

In the conventional circuit thus far described, the speed and accuracy are determined by the speed at which the capacitors 20 and 21 are charged. If the charging time is sufficiently extended, generally speaking, data relating to the offset voltage can be stored to a sufficiently high accuracy, but the defect arises that the operation speed is reduced. On the other hand, the speed would be increased, but the defect arises that the comparison accuracy is reduced. Thus, the two features of high speed and high accuracy cannot be satisfied simultaneously.

With reference to FIGS. 3 and 4, one embodiment of the present invention will be described in the following.

The differential amplifier 30 has one input I.sub.1 connected by the switch 10 to the input terminal 1 and another input I.sub.2 connected directly to the input terminal 2. The short-circuiting switch 11 is connected between the terminals I.sub.1 and I.sub.2. The switch 10 has a control terminal thereof supplied with the signal .phi. from a control signal generator 70 through a line 60, and the switch 11 has a control terminal thereof supplied, through a line 61, with the signal .phi. which is obtained by introducing the signal .phi. into an inverter 80.

The true output terminal 40 of the differential amplifier 30 is connected to one terminal of the capacitor 20, the other terminal of which is grounded through the switch 12 and connected to the input terminal 42 of the latch circuit 31. The complementary output terminal 41 of the differential amplifier 30 is connected to one terminal of the capacitor 21. The other terminal of the capacitor 21 is grounded through the switch 13 and connected to the input terminal 43 of the latch circuit 31. The switches 12 and 13 have control terminals supplied with the control signal .phi.. This control signal .phi. from the inverter 80 is supplied as a standby instruction signal to a terminal 4 through a buffer 81. The latch 31 has a write control terminal W thereof supplied with a control signal .phi.' from a control signal generator 71, which has a higher frequency than that of the control signal .phi..

With reference to FIG. 4, the operation of the comparator circuit according to the present invention will be described in the following. During the period I in which the signal .phi. is at low level, the switch 10 is open (off). During the period II in which the signal .phi. is at high level, on the other hand, the switch 10 is closed (on). While the switches 11, 12 and 13 are supplied with the control signal .phi. so that they are closed (on) during the period I and open (off) during the period II. As can be understood from these relationships, the offset voltage of the differential amplifier 30 is stored in the capacitors 20 and 21 during the period I, and the input signal is amplified in an analog manner during the period II. The duration of the period I is set by taking the charging rate into consideration so that the desired accuracy can be achieved. The period II can be extended within a range that allows the data relating to the offset voltage stored in the capacitors 20 and 21 to maintain the desired accuracy. Usually when such a circuit is integrated, the data is carried and lost by leakage currents through the p-n junction attendant on the input terminals 42 and 43 of the latch circuit 31. This loss is usually extremely small so that the period II can be made much longer than the period I. In order to provide a better performance than that of the circuit of the prior art, however, the period II must be at least twice as long as the period I. The signal which has been amplified in an analog manner during the period II is applied through the terminals 42 and 43 to the latch circuit 31, in which it is sampled and latched. The latch circuit 31 is supplied through the line 50 with the control signal .phi.', shown in FIG. 4(c), from the control signal generator 71. The latch circuit 31 itself can operate at a high speed so that it can sample several times during the period II. As illustrated in FIG. 4(c), four pulses for the latching operation are generated during the period II so that four sampling operations can be conducted. Generally speaking, the sampling can only be done the number of times set by the operating speed of the latch circuit used. An output is generated from the output terminal 3 of the latch circuit 31 during the period I, since this is meaningless, the peripheral circuits must be informed to inhibit the output during the period I. For this purpose, it may be sufficient to generate the signal of FIG. 4(b) as a standby instruction signal through the buffer 81 and output it from the terminal 4.

In the comparator circuit according to the present invention, as is apparent from the description thus far made, the control signal for the sampling latch is prepared and applied to the latch circuit independently of the control signal reducing the offset voltage, so that the sampling can be conducted at a high speed without reducing the desired accuracy. In other words, it is possible to provide a high-speed comparator.

With reference to FIGS. 5 and 6, a second embodiment of the present invention will be described in the following.

In this embodiment, two comparator units CA and CB are made to operate alternately and the output of the unit in operation is extracted from an output terminal 5 through a multiplexer 34.

Specifically, the switch 10 of the unit CA is supplied with a control signal .phi..sub.2, which is generated by a control signal generator 35, and its switches 12 and 13 have control terminals supplied with a control signal .phi..sub.2, which has the opposite phase to the signal .phi..sub.2 and which compensates for the input offset voltage in response to the control signal .phi..sub.2, to conduct comparisons in response to the control signal .phi..sub.2, and to latch the result of the comparison in the latch circuit 31, which has its writing operation controlled by a control signal .phi..sub.2 ' from a control signal generator 36, the signal .phi..sub.2 ' having a higher frequency than that of the control signal .phi..sub.2. In the unit CB, switches 16 and 17 are turned on in response to the control signal .phi..sub.2 to effect the input offset compensation and compare the signals input thereto in response to the control signal .phi..sub.2. The multiplexer 34 connects the output terminal 3 of the latch circuit 31 to a terminal 5 in response to the signal .phi..sub.2, and a terminal 4 of a latch circuit 33 to terminal 5 in response to the signal .phi..sub.2.

As shown in FIG. 5, switches 10, 15, 16 and 17 are on and switches 11, 12, 13 and 14 are off so that the signal input from terminal 1 and the comparison voltage from terminal 2 are differentially amplified by the action of the differential amplifier 30 and are transmitted through the capacitors 20 and 21 to the input terminals 42 and 43 of the latch circuit 31. The capacitors 20 and 21 are charged with the offset voltages of the differential amplifiers 30 and 32, and the voltages are transmitted to the input terminals 42 and 43 in such a way that the offset voltage of the differential amplifier 30 is excluded therefrom. At the same time, the input terminals of the differential amplifier 32 are short-circuited by the switch 15, and the input signal is blocked by the switch 14. The switches 16 and 17 are turned on so that the offset voltage of the differential amplifier 32 is stored in capacitors 22 and 23. At the same time, the input terminals 46 and 47 of a latch circuit 33 are grounded. The operations thus far described are conducted by the actions of the switches 10 to 17, which are controlled by control signals generated from output terminals 60 and 61 of a control signal generator 35. The switches 10, 15, 16 and 17 are controlled by the control signal from the output terminal 60, and the switches 11, 12, 13 and 14 are controlled by the control signal from the output terminal 61. The latch circuits 31 and 33 are controlled by a control output from an output terminal 52 of a control circuit 36 through control terminals 50 and 51. Both the output terminal 3 of the latch circuit 31 and the output terminal 4 of the latch circuit 33 are connected through the multiplexer 34 to the output terminal 5.

The switches of the circuit shown in FIG. 5 are in the state which is controlled by waveform during the period I of FIG. 6. During the period II, on the other hand, the state of each of the switches is reversed. The significant signal is generated from terminal 3 during the period I and from terminal 4 during the period II. As a result, the multiplexer 34 is controlled so as to connect terminals 3 and 5 during the period I and terminals 4 and 5 during the period II. By adjusting the durations of the periods I and II, the capacitors 20, 21, 22 and 23 can be controlled so as to be charged to the desired accuracy by the offset voltages of the differential amplifiers 30 and 32.

The latch circuits 31 and 32 are enabled by the control signal .phi..sub.2 ' of FIG. 6(c) so that independent rates can be determined for the periods I and II. Generally speaking, a latch circuit can operate at a high speed. It is therefore understood that a circuit according to the present invention can conduct such a high-speed sampling operation with a sufficiently high accuracy to make sufficient use of the high speed of the latch circuit, which has not been utilized in the prior art.

Next, with reference to FIGS. 7 and 8, a third embodiment of the present invention will be described in the following.

In this embodiment, a differential amplifier AM2 for intermediate amplification is inserted between a differential amplifier AM1 corresponding to the differential amplifier 30 of FIG. 3, and a latch circuit 1A, and accordingly, the input offset voltage associated with both the amplifiers AM1 and AM2 are compensated as a whole. A clock signal generator 101 generates a clock signal .phi.' for controlling a latch circuit LA. A frequency divider 102 receives the clock signal .phi.' and generates a clock signal .phi. whose frequency is far lower than that of the signal .phi.'. An inverter 103 generates a clock signal .phi. having the opposite phase with respect to the signal .phi..

The differential amplifier AM1 is constructed of: depletion FETs (D-FETs) Q.sub.3 and Q.sub.4 ; enhancement-mode FETs (E-FETs) Q.sub.5 and Q.sub.6 having gates connected to a power source V.sub.DD ; an E-FET Q.sub.7 whose gate is connected through an E-FET Q.sub.1 to the input terminal 1; an E-FET Q.sub.8 whose gate is connected to the input terminal 2; and an E-FET Q.sub.9 operating as a constant current source. A pair of outputs are extracted from an intermediate node N.sub.1 between the D-FET Q.sub.3 and the E-FET Q.sub.5 and an intermediate node N.sub.2 between the D-FET Q.sub.4 and the E-FET Q.sub.6. These outputs are connected to one terminal each of capacitors C.sub.1 and C.sub.2, respectively. The capacitors C.sub.1 and C.sub.2 are constructed of D-FETs, the gates of which provide the above terminals and the sources, and drains of which together provide the other terminals of the capacitors.

The intermediate amplifier AM2 is constructed of D-FETs Q.sub.10 and Q.sub.11 and E-FETs Q.sub.12 to Q.sub.17 in the same way as in the amplifier AM1.

Both an E-FET Q.sub.18 connected between the gate and drain of the E-FET Q.sub.14 and the E-FET Q.sub.17 connected between the drain and gate of the E-FET Q.sub.15 are turned on together with an E-FET Q.sub.2 by the control signal .phi. so as to charge the capacitors C.sub.1 and C.sub.2 with the input offset voltages relating to the amplifiers AM1 and AM2.

Namely, as well as short-circuiting between the gates of E-FETs Q.sub.7 and Q.sub.8 as the input terminals as the amplifier AM1, the other terminals of the capacitors C1 and C2 are connected to nodes N.sub.5 and N.sub.6 by conducting E-FETs Q.sub.18 and Q.sub.17, in addition to the connections to the gates of E-FETs Q.sub.14 and Q.sub.15, respectively in response to the clock .phi.. Here, the nodes N.sub.5 and N.sub.6 are intermediate junctions between input transistors (Q.sub.14, Q.sub.15) and load circuits (Q.sub.10 and Q.sub.12 ; Q.sub.11 and Q.sub.13) at which amplified signals appear.

According to this feature, the input offset voltage belonging to both the amplifiers AM1 and AM2 are simultaneously compensated.

The latch circuit LA is constructed so that both the parallel circuit of an E-FET Q.sub.19 whose gate is connected to an output node N.sub.3 of the amplifier AM2 and a D-FET Q.sub.20, and the parallel circuit of an E-FET Q.sub.21 whose gate is connected to an output node N.sub.4 of the amplifier AM2 and a D-FET Q.sub.22, are used as loads, while E-FETs Q.sub.24 and Q.sub.25 are cross-connected through connection nodes N.sub.5 and N.sub.6, and writing control E-FETs Q.sub.23 and Q.sub.26 are connected to ground between the connection nodes N.sub.5 and N.sub.6, respectively. The writing control E-MOSTs Q.sub.25 and Q.sub.26 are turned on in response to the clock .phi.' to take in new data which is latched by the E-FETs Q.sub.24 and Q.sub.25 when the E-MOSTs Q.sub.23 and Q.sub.26 are off.

FIG. 8 illustrates specific examples of the signals .phi. and .phi.'.

The signal .phi. can have a high level of 400 ns and a low level of 120 ns whereas the signal .phi.' can have a frequency of 50 to 100 MHz.

Thus, according to the present invention, it is possible to provide a comparator circuit which has an extremely high accuracy and speed.