Automatic Drift Correction

The present invention relates to a method of automatic drift correction in circuits such as may be found in measuring systems, and is applicable to electrical or electro-mechanical systems having a drift in their zero or datum reference point.

Such drift in a circuit arises, for example, as a result of thermal changes in the components of the circuit, ageing, creep in electro-mechanical transducers, and/or leakages due to changes in humidity or contamination build-up; in consequence of such drift, the output of the circuit may be severely distorted and inaccurate.

The present invention provides a method of automatic drift correction in a circuit, which method senses the rate of change of the output of the circuit and distinguishes between a rate of change characteristic of that due to a signal at the input to the circuit, and a rate of change characteristic of that due to drift in the circuit. A compensating signal may then be applied to negate the effect of the drift.

A circuit arrangement for performing the above method includes means for sensing the rate of change of a signal, and means being responsive to the sensed rate of change not exceeding a selected value to apply a drift compensating value to the signal.

Preferred embodiments of the present invention are based on the fact that in particular apparatus, such as many measuring systems, the signal being processed and/or monitored has known characteristics and the output signal or reading should change by increments greater than a certain quantity at a minimum rate, whereas drift in the output due to the causes mentioned above occurs at a rate which is generally much lower.

The criteria set for rate of change and maximum size of increment to be taken as due to drift will depend on the particular application, but may also be varied within any one application according to prevailing conditions, so as to match the expected response to changes in those conditions.

In one example of such an application, the output signal of an electronic digital to analogue (D/A) converter follows inherently discrete steps, and the steps occur at some maximum rate. If the level of the output is monitored, then any changes of less than, say, 1/4 LSB (least significant bit) occurring between one step and the next available step instant must be either a zero/datum voltage drift, or a drift in the volts per bit scale factor. In the case where the latter is known to be significantly better than the former (which is often the case since stable resistors are readily obtainable but semiconductor devices commonly exhibit changes in offset voltage with temperature), the change in output will be mainly due to zero drift and the performance of the D/A converter can be enhanced by applying a correction for this drift. The correction may be purely digital, or by means of analogue circuits such as sample and hold, or by using digital means to store the correction and applying correction via a subsidiary D/A converter possibly having a shorter scale length and lower accuracy than the main converter.

Another example occurs in an electromechanical transducer system using a load cell, amplifier and A/D converter to weight objects. In this case the criteria for determining that a change in reading is due to zero drift are that the signal change shall be less than or equal to one minimum displayed unit (scale interval) increment in a time period chosen to suit the type of use. That is, for weighing a number of items where each item has a weight greater than the scale interval a short time interval could be chosen, but for weighing items whose weight is less than a scale interval a long time interval is more appropriate.

The circuit may include mechanical filters such as dashpots and/or electrical filters to obtain an average and prevent confusion due to vibration and noise.

The correction may be applied by analogue means before digitisation, or by digital means after digitisation. The digital means may be by discrete logic circuits or by using programmable logic such as programmable logic arrays or a computing device such as a microcomputer. A part-analogue circuit/part-digital circuit method is also possible.

Features and advantages of the present invention will become further apparent from the following description of embodiments thereof, given by way of example, when taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a block diagram of a circuit in accordance with one embodiment, suitable for analogue implementation; and

FIG. 2 shows a block diagram of a circuit in accordance with another embodiment, wherein drift compensation is effected by digital means.

Referring to FIG. 1, a circuit 10 assumed to be susceptible to drift includes a signal source 11 and amplifier 12 for amplifying the output of the signal source 11. The signal source may be any device providing a comparatively low-level signal requiring amplification before further processing, such as the aforementioned electro-mechanical weighing transducer. The output of the amplifier 12 would normally be fed to an output device 14, such as a meter, display or pen-recorder, which output device would show an inaccurate reading in the presence of drift in the circuit 10.

In the present instance, the output of the amplifier 12 is fed to the output device 14 via a summing amplifier 15, and a drift compensating signal is applied to another input of the summing amplifier so as to correct the signal fed to the output device 14, as described hereinafter.

The output from the amplifier 12 is additionally fed to a sample/hold circuit 16 and to one input of a window comparator 18. The output of the sample/hold circuit 16 is fed to another input of the window comparator 18, whose output is fed to a second summing amplifier 20. The output of the summing amplifier 20 is fed via second and third sample/hold circuits 21, 22 respectively, both to the drift compensating input of summing amplifier 15, and to the other input of the second summing amplifier 20. A timing control circuit 24 provides timing signals for the sample/hold circuits 16, 21 and 22.

In operation, the output of the amplifier 12 is stored in sample/hold circuit 16 in response to a timing signal from timing control 24. This sampled value is compared with the actual instantaneous output from the amplifier 12 in window comparator 18. If the comparison between the output of the amplifier 12 and the sample/hold 16 output provides a value which falls outside the threshold window set by the comparator 18, no output is produced by the comparator. If however the compared value is within the threshold window, a corresponding signal is fed to the summing amplifier 20. The threshold window is set to provide a maximum rate of change which can be identified as drift, rates of change above this maximum being considered as valid signals. It will be seen that this maximum rate of change is equal to the window of the comparator divided by the time interval between timing signals delivered to sample/hold circuit 16 by the timing control circuit 24. Thus the output of the amplifier 12 at a first instant of time is compared (having been held in sample/hold circuit 16) with the output at a second instant of time.

The arrangement of summing amplifier 20 and sample/hold circuits 21, 22 provides a circulating path for storing the error or compensating signal to be applied to the drift compensating input of summing amplifier 15. Timing signals from the timing control circuit 24 are applied in such a way that this compensating signal is alternately transferred from sample/hold 22 via summing amplifier 20 to sample/hold 21, and then back to sample/hold 22. Any drift updating value derived from the window comparator 18 can be added to the compensating signal as it passes through summing amplifier 20, and the updated compensating signal will then be applied to summing amplifier 15 after passing through sample/hold circuits 21 and 22 in turn.

Thus assuming that the circuit 10 starts with no drift, the circulating compensating signal will be zero at this time, and the reading on output device 14 will be that provided by the amplifier 12. Any drift arising after this time will be first identified as such by the window comparator 18, and then added to the signal already stored by sample/hold 22, from which it will be applied to the drift compensating input of summing amplifier 15 modifying the output thereof to take account of the drift. Any valid signal, i.e. one whose rate of change is rejected by window comparator 18, will however pass unobstructed to provide a valid reading on the output device 14.

FIG. 2 shows an arrangement wherein the circuit 10 is associated with a digital drift compensating system. The principle of operation is similar to that of the analogue arrangement of FIG. 1, and also includes the summing amplifier 15 and analogue output device 14. However, the output of amplifier 12 is first fed to an A/D converter 26, whose digitised output is fed to a memory `A` 27 and to a signal selector circuit 28. Memory `A` 27 also has an output to the signal selector circuit 28, and the arrangement is that the output of A/D converter 26 is stored in memory `A` 27. After a suitable time, the value stored in the memory is compared to the current A/D converter 26 output by an arithmetic unit 30 (via the signal selector circuit 28), the result of the comparison being stored in a memory `B` 32, after passing through a signal routing device 33. The contents of the memory `B` are then compared with preset limits set in a limit store 34, the signals again passing through the signal selector circuit 28, and if within the limits, are added to an offset store, memory `C` 36.

The contents of memory `C` 36 can then be added to the current output of the A/D converter 26 (via the signal selector 28 and in the arithmetic unit 30) so as to provide an output to a digital output device 38. In this case, summing amplifier 15 and analogue output device 14 are not necessary.

Alternatively, the contents of memory `C` 36, which constitute the drift compensating signal in digital form, can be fed via a D/A converter 39 to provide an analogue signal at the drift compensating input of summing amplifier 15 so as to modify the original analogue signal from circuit 10, and correct for drift in the analogue output device 14.

It will be seen that in the case of the FIG. 2 arrangement, the memory `C` 36 holds the drift compensating signal which is periodically updated depending on the comparison between the preset limits in the limit store 35 and the contents of memory `B` 32 which contents are indicative of the rate of change of the output of circuit 10. The preset limits in the limit store 34 are accordingly set in accordance with the criteria set out above, depending on the particular application.