Voltage Comparator Circuit

This invention relates to a voltage comparator circuit, and, more particularly, to a voltage comparator circuit which employs insulated gate-effect transistors (MISFETs which shall be simply termed FETs hereinbelow).

FIGS. 1 and 2 are circuit diagrams each of which shows an embodiment of the voltage comparator circuit according to this invention, and

FIG. 3 is a circuit diagram which shows an example of a prior-art voltage comparator circuit.

FIG. 3 illustrates a conventional circuit for comparing two voltages and detecting the difference between them.

In this circuit, a differential amplifier circuit is constructed of resistances R.sub.1 to R.sub.3 and bipolar transistors Q.sub.1 and Q.sub.2. Input voltages V.sub.1 and V.sub.2 are respectively applied to the bases of the transistors Q.sub.1 and Q.sub.2, and the inverted output of a flip-flop circuit FF connected at the succeeding stage represents the level difference between the inputs.

It is a recent technological trend that most electronic circuits are constructed of semiconductor integrated circuits. Where a voltage comparator circuit is formed as a semiconductor integrated circuit, the employment of FETs is more advantageous than that of bipolar transistors from the viewpoint of the enhancement of the density of integration.

However, where a differential amplifier circuit and an output circuit to be connected thereto (for example, a flip-flop circuit) are made up of FETs, various problems arise.

Since a threshold voltage V.sub.th is necessary for the input FET of the output circuit to operate, the output of the differential amplifier circuit must be at a voltage greater than the value V.sub.th. On the other hand, in order to attain a high operating sensitivity for the differential amplifier circuit, the transfer conductance (g.sub.m) of the FET as the amplifier element must be considerably large. In order to make the value g.sub.m large, the area of this FET must generally be made large.

These problems are attributed to the fact that the difference between the compared voltages is directly applied to the detector circuit.

The present invention has been developed in order to solve these problems, and has as an object the provision of a voltage comparator circuit which is suitable for a semiconductor integrated circuit device.

A fundamental construction of this invention for accomplishing this object is characterized by at least a pair of time constant circuits each of which includes a variable impedance and a capacitor, the variable impedance being controlled by an input voltage, and a flip-flop circuit which is stabilized to predetermined values by comparisons of time variations of the outputs of the time constant circuits.

Another construction of this invention is characterized by at least a pair of integration circuits each of which includes a variable impedance and a capacitor, the variable impedance being controlled by an input voltage, a pair of switching means each of which is driven by a clock pulse, and a pair of logic circuits each of which has two driving elements connected in series with a load element, the pair of switching means being respectively connected across the terminals of said capacitors, the pair of logic circuits constituting a flip-flop circuit in such a manner that the output of one of the corresponding two driving elements of the logic circuits is applied to the input of the other of said corresponding driving elements and that the output voltages of the integration circuits are respectively applied to the inputs of the remaining two corresponding driving elements of the logic circuits, an output of said voltage comparator circuit being derived from the flip-flop circuit, the switching elements being held conductive by the clock pulse during a period of time during which no voltage comparison is made.

Still another construction of this invention is characterized by at least a pair of differentiation circuits each of which includes a variable impedance and a capacitor, the variable impedance being controlled by an input voltage, a pair of switching devices each of which is driven by a clock pulse, and a pair of logic circuits each of which has two driving elements connected in parallel with a load element, a supply voltage being applied to the differentiation circuits through the switching devices, the pair of logic circuits constituting a flip-flop circuit in such manner that the output of each of the logic circuits is applied to the input of one of the driving elements of the opposite logic circuit and that the output voltages of the differentiation circuits are respectively applied to the inputs of the remaining driving elements of the logic circuits, the output of said voltage comparator circuit being derived from the flip-flop circuit, the switching devices being held conductive by the clock pulse during a period of time during which no voltage comparison is made.

With reference to FIG. 1, between a power supply terminal V.sub.DD and ground, an FET M.sub.1 as a variable impedance and an FET M.sub.2 as a switching element are connected in series. An input V.sub.1 is applied to the gate of the FET M.sub.1, while a clock pulse .phi..sub.1 is applied to the gate of the FET M.sub.2. Also, between the power supply terminal V.sub.DD and ground, an FET M.sub.3 as a variable impedance and an FET M.sub.4 as a switching element are connected in series. An input V.sub.2 is applied to the gate of the FET M.sub.3, while the clock pulse .phi..sub.1 is applied to the gate of the FET M.sub.4.

Further, a load FET M.sub.5 and switching FETs M.sub.6 and M.sub.7 are connected in series between the power supply terminal V.sub.DD and ground. The source and gate of the FET M.sub.5 are short-circuited. Thus, a first 2-input logical circuit is constructed. Likewise, a second 2-input logical circuit is constructed which is made up of a load FET M.sub.8 and switching FETs M.sub.9 and M.sub.10.

The gates of the corresponding switching FETs M.sub.6 and M.sub.9 of the two 2-input logic circuits are connected at the outputs of opposite logic circuits, respectively. The gates of the other corresponding switching FETs M.sub.7 and M.sub.10 are connected with the sources of the variable impedance FETs M.sub.1 and M.sub.3, respectively. Thus, a flip-flop circuit is formed.

An FET M.sub.11 which is driven by a clock pulse .phi..sub.2 is connected to an output of the flip-flop circuit. An output terminal V.sub.out is connected to the source of the FET M.sub.11.

Capacitors C.sub.1 to C.sub.4 are the gate capacitances of the FETs, and the FETs M.sub.1,M.sub.3 and M.sub.5,M.sub.8 are of the depletion type.

Initially, in response to the application the clock pulse .phi..sub.1 to FETs M.sub.2 and M.sub.4 the capacitors C.sub.1 and C.sub.2 are discharged. Due to the discharge, the FETs M.sub.7 and M.sub.10 constituting the flip flop circuit become nonconductive, and the capacitors C.sub.3 and C.sub.4 commence charging. Due to the charging of the capacitors C.sub.3 and C.sub.4, FETs M.sub.6 and M.sub.9 become conductive.

Subsequently, when the clock pulse .phi..sub.1 is no longer applied and, simultaneously, input voltages V.sub.1 and V.sub.2 are applied, the capacitors C.sub.1 and C.sub.2 are charged through FETs M.sub.1 and M.sub.3 whose impedances are determined in dependence on the levels of the input voltages V.sub.1 and V.sub.2, respectively.

As a consequence, when, by way of example, V.sub.1 > V.sub.2, the impedance of the FET M.sub.1 becomes lower than that of the FET M.sub.3, and the charge on capacitor C.sub.1 increases faster than that of capacitor C.sub.2. Since the charged voltages of the respective capacitors are supplied to the gates of the FETs M.sub.7 and M.sub.10 constituting the flip-flop, the FET M.sub.7 whose threshold voltage is reached earlier is rendered conductive first. Due to the conduction of the FET M.sub.7, capacitor C.sub.4 is discharged, and the FET M.sub.9 becomes nonconductive. Accordingly, the output of the flip-flop circuit becomes that of the supply voltage V.sub.DD. Even when the FET M.sub.10 becomes conductive when FET M.sub.7 is conductive, the V.sub.DD level on the output remains unchanged because FET M.sub.9 is nonconductive.

When, conversely to the above situation, the two inputs have a relation of V.sub.1 < V.sub.2, ground potential is produced at the output of the flip-flop.

In this way, a voltage comparison is carried out.

The clock pulse .phi..sub.2 is impressed on the gate of the FET M.sub.11 since an output is acquired in conformity with the period of time during which the result of the voltage comparison is to be detected. The clock pulse .phi..sub.1 serves to continuously effect a voltage comparison, and is applied in order to carry out the preparatory operation for the voltage comparison.

As is set forth above, the invention effects a voltage comparison in such a manner that the voltages to be compared are applied to variable impedances causing variations in currents, to charge the capacitors C.sub.1 and C.sub.2, and that the flip-flop circuit is operated in dependence on the difference between the charging periods of time. The invention is therefore advantageous in that the transfer conductance (g.sub.m) need not be considered. Another advantage is that, by using depletion type FETs for the FETs M.sub.1 and M.sub.3 as variable impedances the comparator can be utilized even when the voltages V.sub.1 and V.sub.2 to be compared are below the threshold voltages V.sub.th of the FETs.

The invention is not restricted to the above embodiment.

For example, although in the foregoing embodiment the difference between the charging periods of time of the capacitors C.sub.1 and C.sub.2 is detected on the basis of the difference between the input voltages V.sub.1 and V.sub.2 applied to the FETs M.sub.1 and M.sub.3 functioning as variable impedances, the difference between the discharging periods of time of the capacitors C.sub.1 and C.sub.2 may be detected as illustrated in FIG. 2. This circuit arrangement differs from that of FIG. 1.

As is illustrated in FIG. 2, FETs M.sub.1 and M.sub.3 forming the impedances which are controlled by the input voltages V.sub.1 and V.sub.2 are provided on the ground terminal side, and the FETs M.sub.2 and M.sub.4 which are driven by the clock pulse are provided on the power supply terminal V.sub.DD side. Further, the switching FETs M.sub.6 and M.sub.7 are connected in parallel and they are connected to the load FET M.sub.5, to thus construct a first 2-input logic circuit. Similarly, a second 2-input logic circuit is constructed which is composed of the load FET M.sub.8 and the switching FETs M.sub.9 and M.sub.10. The first and second logic circuits constitute a flip-flop circuit in such a way that the gates of the switching FETs M.sub.7 and M.sub.9 are connected with the outputs of the opposite logic circuits, respectively, and that the gates of the remaining switching FETs M.sub.6 and M.sub.10 are connected with the drains of the variable impedance FETs M.sub. 1 and M.sub.3, respectively.

Here, the capacitors C.sub.1 and C.sub.2 are formed by the gate capacitances of the FETs. The FET M.sub.11 which is driven by the clock pulse .phi..sub.2 is the same as explained in the embodiment of FIG. 1.

Initially, upon application of the clock pulse .phi..sub.1 to FETs M.sub.2 and M.sub.4 capacitors C.sub.1 and C.sub.2 are charged, with the result that the FETs M.sub.6 and M.sub.10 being the inputs of the flip-flop circuit, becomes conductive. Subsequently, when the clock pulse .phi..sub.1 is not applied and the inputs V.sub.1 and V.sub.2 are applied, the impedances of the FETs M.sub.1 and M.sub.3 are determined by the inputs and the capacitors C.sub.1 and C.sub.2 are discharged in conformity with the different impedances, respectively. Due to the difference between the discharging periods of time, either of the FETs M.sub.6 and M.sub.10, being the inputs of the flip-flop circuit, is rendered nonconductive. Thus, the output of the flip-flop circuit is determined, and a voltage comparison is carried out.

With the above circuit, if the clock pulse .phi..sub.1 is applied when V.sub.1 and V.sub.2 are applied, the charging levels of the capacitors C.sub.1 and C.sub.2 will be respectively determined by the impedance ratios between the FETs M.sub.1 and M.sub.2 and between the FETs M.sub.3 and M.sub.4 and, hence, the discharging will provide the nonconductive level of the FET in a very short time. This brings forth the advantages that the operating sensitivity is very satisfactory.

Although, in the embodiments of FIGS. 1 and 2, the gate capacitances of the FETs are employed as the capacitors, this is not restrictive but externally-mounted capacitors may be used.

This invention can be extensively utilized for a voltage comparator employing FETs.