US 9,390,909 B2Grant
Soft landing nanolaminates for advanced patterning
Issue Date:2016-07-12
•18 Claims
•13 Drawing Sheets
Abstract
Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.
Metadata
Assignee
- Novellus Systems, Inc.
Inventors
- Frank L. Pasquale
- Shankar Swaminathan
- Adrien LaVoie
- Nader Shamma
- Girish Dixit
Application Information
Application Number:US 14/194,324
Filing Date:2014-02-28
Priority Date:2013-11-07
Art Unit:2894
Classifications
IPC:
H01L21/00H01L21/02C23C16/34C23C16/40C23C16/455H01L21/66H01L21/033
Field of Search:
H01L 21/0228H01L 21/2186
Patent Drawings (13 sheets)
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 14/074,617, filed Nov. 7, 2013, and titled “METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES,” which is incorporated by reference herein in its entirety and for all purposes.
BACKGROUND
[0002] Fabrication of advanced integrated circuits often involve patterning of 1×nm half-pitch features in high volume manufacturing of semiconductors. Multiple patterning techniques may enable feature size scaling based on lithographic techniques such as 193 nm immersion lithography. Self-aligned double patterning is an example of a multiple patterning technique. Extensions of order multiple patterning techniques to 11 nm half pitch and below present challenges.
SUMMARY
[0003] Provided herein are methods of processing semiconductor substrates to enable deposition of high quality conformal films for use in multiple patterning integration schemes.
[0004] One aspect involves a method of processing a semiconductor substrate by depositing a nanolaminate layer on the substrate and depositing a titanium oxide layer on the nanolaminate layer. The nanolaminate layer may have a thickness between about 15 Å and about 200 Å and may have a density lower than the density of the titanium oxide layer. In various embodiments, the method also includes depositing an amorphous carbon layer. In some embodiments, the amorphous carbon layer is patterned. In various embodiments, the nanolaminate layer includes a stack that includes two or more sublayers. In some embodiments, the two or more sublayers include silicon oxide, or titanium oxide, or combinations thereof. In certain embodiments, the stack includes only two sublayers. In some embodiments, the nanolaminate layer includes a first sublayer of silicon oxide and a second sublayer of titanium oxide.
[0005] In various embodiments, the nanolaminate layer is silicon oxide or titanium oxide. In certain embodiments, the nanolaminate layer is deposited using a plasma-based process such as plasma-enhanced atomic layer deposition (PEALD) by exposing the substrate to a titanium-containing precursor or a silicon-containing precursor; exposing the substrate to an oxidant; and initiating a plasma while the substrate is exposed to the oxidant. In certain embodiments, the nanolaminate layer is deposited at a temperature between about 50° C. and about 150° C. and the plasma is initiated with a high frequency radio frequency (HFRF) power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2. In certain embodiments, the nanolaminate layer is deposited at a temperature less than about 100° C. An example of a titanium-containing precursor that may be used with the methods disclosed herein is tetrakis(dimethylamino)titanium (TDMAT). An example of a silicon-containing precursor is bis(tertiarybutylamino)silane (SiH2(NHC(CH3)3)2 (BTBAS).
[0006] In various embodiments, the titanium oxide layer is deposited by PEALD by exposing the substrate to a titanium-containing precursor; exposing the substrate to an oxidant; and initiating a plasma while the substrate is exposed to the oxidant at a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2. Examples of oxidants include nitrous oxide, oxygen, carbon dioxide or a combination thereof. The titanium oxide layer may be deposited at a temperature between about 50° C. and about 400° C. in some embodiments.
[0007] Another aspect involves a method of processing a semiconductor substrate by depositing a core layer; depositing a nanolaminate layer on the core layer; and depositing a metal nitride or metal oxide layer on the nanolaminate layer. In some embodiments, the core layer is patterned. In certain embodiments, the core layer may be amorphous carbon or a photoresist. In various embodiments, the nanolaminate layer may be silicon oxide or titanium oxide. In some embodiments, the thickness of the deposited nanolaminate layer is between about 15 Å and about 200 Å.
[0008] In certain embodiments, the nanolaminate layer is deposited using PEALD by exposing the substrate to a titanium-containing precursor or a silicon-containing precursor; exposing the substrate to an oxidant; and initiating a plasma while the substrate is exposed to the oxidant. In various embodiments, the nanolaminate layer is deposited at a temperature between about 50° C. and about 150° C. and the plasma is initiated with HFRF power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2. In some embodiments, the nanolaminate layer is deposited at a temperature less than about 100° C.
[0009] In various embodiments, the metal nitride or metal oxide layer includes titanium oxide or silicon oxide. The metal nitride or metal oxide layer may have etch selectivity to the core. In certain embodiments, the metal nitride or metal oxide layer is deposited using PEALD by exposing the substrate to a metal-containing precursor; exposing the substrate to an oxidant; and initiating a plasma while the substrate is exposed to the oxidant at a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2. Examples of oxidants include nitrous oxide, oxygen, carbon dioxide or combinations thereof. In some embodiments, the metal nitride or metal oxide layer is deposited at a temperature between about 50° C. and about 400° C.
[0010] Another aspect involves a method of processing a semiconductor substrate by (a) exposing the substrate to a first titanium-containing precursor or a silicon-containing precursor; (b) exposing the substrate to a first oxidant; (c) initiating a first plasma while the substrate is exposed to the first oxidant with a HFRF power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2; (d) exposing the substrate to a second titanium-containing precursor; (e) exposing the substrate to a second oxidant; and (f) initiating a second plasma while the substrate is exposed to the second oxidant with a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2.
[0011] In some embodiments, (a) through (c) are processed at temperature between about 50° C. and 150° C. In some embodiments, (d) through (f) are processed at temperature between about 50° C. and 400° C. In some embodiments, (d) through (f) are processed at a higher temperature than (a) through (c) such that transitioning from (c) to (d) includes raising the substrate temperature by at least about 50° C., at least about 100° C., at least about 150° C., or at least about 200° C.
[0012] The first titanium-containing precursor and the second titanium-containing precursor may be the same precursor, e.g., TDMAT. In some embodiments, the first oxidant may be the same as the second oxidant (e.g., nitrous oxide, oxygen, carbon dioxide or combinations thereof). In some embodiments, it may be advantageous to use a different oxidant or mixture. In some embodiments, the substrate includes amorphous carbon. In some embodiments, the amorphous carbon is patterned.
[0013] In various embodiments, the method also includes after initiating the second plasma, planarizing the substrate to expose the amorphous carbon, and selectively etching the amorphous carbon to form a mask.
[0014] Another aspect involves a method of patterning a semiconductor substrate by, prior to depositing a conformal film on a core layer, depositing a nanolaminate protective layer on a patterned core layer; depositing a conformal film on the nanolaminate protective layer; planarizing the conformal film to expose the core; and selectively etching the core to form a mask.
[0015] In certain embodiments, the core layer includes amorphous carbon. In various embodiments, the nanolaminate protective layer includes silicon oxide or titanium oxide. In certain embodiments, the thickness of the nanolaminate protective layer is between about 15 Å and about 200 Å. In many embodiments, the nanolaminate protective layer is deposited using PEALD by exposing the substrate to a titanium-containing precursor or a silicon-containing precursor; exposing the substrate to an oxidant; and initiating a first plasma while the substrate is exposed to the oxidant.
[0016] In some embodiments, the nanolaminate protective layer is deposited at a temperature less than about 100° C. In various embodiments, the nanolaminate protective layer is deposited at a temperature between about 50° C. and about 150° C. and the first plasma is initiated at a HFRF power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2.
[0017] In some embodiments, the titanium oxide layer is deposited using PEALD by exposing the substrate to a titanium-containing precursor; exposing the substrate to an oxidant; and initiating a second plasma while the substrate is exposed to the oxidant at a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2.
[0018] Another aspect involves an apparatus for processing a semiconductor substrate including one or more process chambers; one or more gas inlets into the process chambers and associated flow-control hardware; a HFRF generator; and a controller having at least one processor and a memory, such that the at least one processer and the memory are communicatively connected with one another, the at least one processor is at least operatively connected with the flow-control hardware and HFRF generator, and the memory stores computer-executable instructions for: exposing the substrate to a metal-containing precursor; exposing the substrate to a first oxidant; initiating a first plasma while the substrate is exposed to the first oxidant with a HFRF power of between about 12.5 W and 125 W; exposing the substrate to a titanium-containing precursor; exposing the substrate to a second oxidant; and initiating a second plasma while the substrate is exposed to the second oxidant with HFRF power of at least about 125 W.
[0019] These and other aspects are described further below with reference to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIGS. 1-11 are schematic depictions of an integration scheme in accordance with disclosed embodiments.
[0021] FIGS. 12-18 are schematic depictions of an integration scheme in accordance with disclosed embodiments.
[0022] FIG. 19 is a process flow diagram of a method in accordance with disclosed embodiments.
[0023] FIGS. 20A and 20B are process flow diagrams of methods in accordance with disclosed embodiments.
[0024] FIG. 21 is an illustration of a reaction chamber for practicing methods in accordance with disclosed embodiments.
[0025] FIG. 22 is an illustration of a multi-station apparatus that may be used for performing operations in accordance with disclosed embodiments.
[0026] FIGS. 23A-23C are images of deposited films from experiments in performing methods in accordance with disclosed embodiments.
DETAILED DESCRIPTION
[0027] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.
[0028] Fabrication of semiconductor devices typically involves depositing one or more thin films in an integrated manufacturing process and may include patterning steps. Multiple patterning techniques are used to fabricate advanced integrated circuits, such as those with smaller features or higher aspect ratios, or down to 2× or 1×nm nodes. The term “1×” node means a process node between 10 nm and 19 nm and the term “2×” node means a process node between 20 nm and 29 nm. An example of multiple patterning is self-aligned double patterning, which produces double the number of features of a pattern formed by conventional lithography. As the devices become smaller, narrower half-pitch features may be attained using advanced multiple patterning techniques, such as quadruple patterning, or “quad patterning.”
[0029] An example of a quad patterning scheme is provided in FIGS. 1-11 . FIG. 1 provides a schematic illustration of an example of various layers that may be included in a multi-layer stack, such as on a wafer suitable for semiconductor processing. The multi-layer stack in FIG. 1 includes a first core layer formed into first cores (also referred to as first mandrels) 103, which may be lithographically defined in a previous process, on top of a hardmask 104. Hardmask 104 may be on top of a second core layer 105, which is itself deposited on layer 107. Layer 107 may include a hardmask layer 107a, a cap layer 107b, and a mask layer 107c, which may be used as a mask to pattern a subsequent target layer 150. Barrier layers, cap layers, or etch stop layers may be between the mask layer 107c and target layer 150. One of ordinary skill in the art will appreciate that there may be one or more layers deposited between any of the above described layers, and the target layer 150 may include one or more additional layers.
[0030] The first core layer (and thus first cores 103) may be highly etch selective to other materials in the stack, such as silicon and/or silicon-based oxides or nitrides, for example, and may be transparent. The first core layer may be a photoresist or may be made of amorphous carbon material or amorphous silicon material. In some embodiments, the first core layer may be deposited on top of hardmask 104 by a deposition technique, such as plasma-enhanced chemical vapor deposition (PECVD), and the deposition technique may involve generating a plasma in the deposition chamber from deposition gases including a hydrocarbon precursor. The hydrocarbon precursor may be defined by the formula CxHy, where x is an integer between 2 and 10, and y is an integer between 2 and 24. Examples include methane (CH4), acetylene (C2H2), ethylene (C2H4), propylene (C3H6), butane (C4H10), cyclohexane (C6H12), benzene (C6H6), and toluene (C7H8). A dual radio frequency (RF) plasma source including a high frequency (HF) power and a low frequency (LF) power may be used. Alternatively a single RF plasma source may be used. Typically such a source will be a HFRF source.
[0031] Under the first core layer formed into first cores 103 is a second core layer 105. Between the first core layer and the second core layer 105 may be a hardmask 104. The hardmask 104 may have high etch selectivity relative to first core layer and second core layer 105 so as not to etch second core layer 105 while first core layer is patterned. The second core layer 105 may be made of amorphous carbon material or amorphous silicon material. Methods of deposition and deposition precursors may be any of those described above with respect to first core layer. Once patterned, the second core layer 105 is formed into second cores (also referred to as second mandrels) 105′ (shown in FIG. 5 ) and may be used to etch a mask in a subsequent layer, such as mask layer 107c, which may then be used to pattern the target layer 150. In certain embodiments, the mask layer 107c may be made of amorphous carbon material or amorphous silicon material. In quadruple patterning schemes, such as that depicted in FIGS. 1-11 , the mask layer 107c may be the quadruple pattern of a photoresist pattern such that one feature in a photoresist is patterned and transferred to form four features in the target layer 150.
[0032] Between the second core layer 105 and target layer 150 may be other layers, such as a hardmask layer 107a, or cap layer 107b, or a mask layer 107c to be used to pattern the target layer 150. The target layer 150 may be the layer ultimately to be patterned. The target layer 150 may be a semiconductor, dielectric or other layer and may be made of silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), or titanium nitride (TiN), for example. The target layer 150 may be deposited by atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), chemical vapor deposition (CVD), or other suitable deposition techniques.
[0033] In one example, the compositions and thicknesses of a quad patterning stack such as the one shown in FIG. 1 may be the following: 400 Å amorphous carbon first cores 103, 150 Å tetraethylorthosilicate (TEOS) hardmask layer 104, 350 Å amorphous carbon second core layer 105, 150 Å TEOS hardmask layer 107a, 100 Å amorphous silicon cap layer 107b, 300 Å amorphous carbon mask layer 107c, 200 Å titanium nitride barrier layer (not shown) 108a, and 300 Å TEOS hardmask layer (not shown), all on a silicon target layer or substrate 150. In one example, the following may be deposited on top of the 400 Å amorphous carbon first core layer in order prior to lithographic patterning to define the first core layer as depicted in the example of FIG. 1 : 100 Å-150 Å SiON etch stop layer, 300 Å bottom anti-reflective coating (BARC) layer, and 1000 Å photoresist first core layer.
[0034] In FIG. 2 , a conformal film 109 is deposited over the first cores 103. The conformal film 109 may also be referred to as a “spacer” and may be deposited to conform to the shape of the pattern on the multi-layer stack to make an evenly distributed layer over the pattern. As described further below, the conformal film 109 may be formed into multiple individual spacers, each of which abuts a sidewall of the first cores 103. The conformal film 109 has a high etch selectivity to the core. For example, the conformal film 109 may have an etch selectivity greater than 3:1 relative to an amorphous carbon layer. In some embodiments, conformal film 109 has an etch selectivity greater than 15:1 relative to poly-silicon in halide etch chemistry.
[0035] The conformal film 109 may be made of dielectric material, such as SiO2. The conformal film 109 may also be an oxide, such as titanium oxide (TiO2), or may be silicon nitride (SiN). In some embodiments, the conformal film 109 is made of denser material to withstand more “passes” of patterning and may be deposited by ALD, PEALD, or conformal film deposition (CFD) methods as described briefly below.
[0036] ALD processes use surface-mediated deposition reactions to deposit films on a layer-by-layer basis. In one example ALD process, a substrate surface, including a population of surface active sites, is exposed to a gas phase distribution of a first film precursor (P1). Some molecules of P1 may form a condensed phase atop the substrate surface, including chemisorbed species and physisorbed molecules of P1. The reactor is then evacuated to remove gas phase and physisorbed P1 so that only chemisorbed species remain. A second film precursor (P2) is then introduced to the reactor so that some molecules of P2 adsorb to the substrate surface. The reactor may again be evacuated, this time to remove unbound P2. Subsequently, thermal energy provided to the substrate activates surface reactions between adsorbed molecules of P1 and P2, forming a film layer. Finally, the reactor is evacuated to remove reaction by-products and possibly unreacted P1 and P2, ending the ALD cycle. Additional ALD cycles may be included to build film thickness. In an example of a PEALD process, a plasma is initiated while the second film precursor P2 is introduced to the reactor to activate the reaction between P1 and P2.
[0037] CFD may be used to deposit the conformal film 109. Generally, CFD does not rely on complete purges of one or more reactants prior to reaction to form the film. For example, there may be one or more reactants present in the vapor phase when a plasma (or other activation energy) is struck. Accordingly, one or more of the process steps described in an ALD process may be shortened or eliminated in an example CFD process. Further, in some embodiments, plasma activation of deposition reactions may result in lower deposition temperatures than thermally-activated reactions, potentially reducing the thermal budget of an integrated process. For context, a short description of CFD is provided. The concept of a CFD cycle is relevant to the discussion of various embodiments herein. As with ALD processes, generally a cycle is the minimum set of operations required to perform a surface deposition reaction one time. The result of one cycle is production of at least a partial film layer on a substrate surface. Typically, a CFD cycle will include only those steps necessary to deliver and adsorb each reactant to the substrate surface, and then react those adsorbed reactants to form the partial layer of film. The cycle may include certain ancillary steps such as sweeping one or more of the reactants or byproducts and/or treating the partial film as deposited. Generally, a cycle contains only one instance of a unique sequence of operations. As an example, a cycle may include the following operations: (i) delivery/adsorption of reactant A, (ii) delivery/adsorption of reactant B, (iii) sweep B out of the reaction chamber, and (iv) apply plasma to drive a surface reaction of A and B to form the partial film layer on the surface. As used herein, the term PEALD includes CFD processes.
[0038] The following conditions are examples of conditions suitable depositing a silicon oxide conformal film 109 by a CFD process. Deposition may occur at a temperature between about 50° C. and about 400° C., at a pressure between about 0.5 Torr and about 10 Torr, and an RF power for four stations between about 100 W and 10 kW. RF activation frequency can vary from about 13.56 MHz to 40 MHz for various embodiments. For a silicon oxide conformal film 109, process gases that may be used include, as a silicon source, a silicon amide (e.g., BTBAS, BDEAS (bis-di-ethyl aminosilane) or DIPAS (di-isopropyl aminosilane), and, as an oxygen source, oxygen or nitrous oxide or carbon dioxide, separately or together, diluted with an inert carrier gas, for example argon or nitrogen. Process gas flow rates may be as follows: for (liquid) silicon precursor (e.g., BTBAS, BDEAS, and DIPAS), between about 1 sccm and 3 sccm, for example BTBAS at about 2.5 sccm; for oxygen precursor (O2, N2O), between about 5000 sccm and 10,000 sccm, for example N2O at 5000 sccm; and for the carrier gas (Ar or N2), between about 0 sccm and 10,000 sccm, for example about 5000 sccm Ar.
[0039] In FIG. 3 , the conformal film 109 is etched back or planarized to expose the first cores 103. In various embodiments, the conformal film 109 may be planarized through a multi-step process. In one example, the conformal film 109 may be etched back by first flowing about 10 sccm to about 100 sccm of chlorine (Cl2), then about 10 sccm to about 100 sccm of methane (CH4), then about 10 sccm to about 100 sccm of nitrogen (N2) for about 30 seconds. In some embodiments, the conformal film 109 may be etched at a temperature between about 10° C. and about 20° C. and at a pressure between about 2 mTorr and about 20 mTorr for a time of about 30 seconds. In some embodiments, the substrate may be etched at a temperature between about 40° C. and about 60° C. and at a pressure between about 5 mTorr and about 100 mTorr. In many embodiments, an anisotropic plasma etch is performed to expose the core and define the structure of the spacers 109′ from the conformal film 109.
[0040] In FIG. 4 , the first cores 103 are stripped or etched, leaving free-standing spacers 109′ on the substrate. If the first core layer is a photoresist, the first cores 103 may be etched by flowing oxygen (O2) at a flow rate between about 100 sccm and about 200 sccm at a temperature between about 40° C. and about 60° C. in a pressure between about 5 mTorr and about 20 mTorr.
[0041] If the first core layer is made of amorphous carbon material, the first cores 103 may be stripped or etched using an ashing method. An ashing method may be dependent on chemical reactions for material removal, rather than directional movement of energetic ions. For example, any surface that is exposed to the process gas used in an ashing operation may experience material removal due to the exposure, so the amorphous carbon material used in the first cores 103 may have high etch selectivity to the spacers 109′ such that the spacers 109′ are not etched while the first cores 103 are ashed. Additionally, in contrast to some chemical etching processes, ashing operations may produce a reaction product that is completely in the gas phase. Ashing operations for carbon films may, for example, utilize dissociated hydrogen (H2) or oxygen (O2) as a process gas, which may react with carbon films to form such gas-phase reaction byproducts. In some embodiments, the remaining spacers 109′ may be shaped for subsequent processing using various etch conditions.
[0042] In FIG. 5 , the second core layer 105 is etched down using the spacers 109′ as a mask, thereby transferring the pattern to form second cores 105′. The second core layer 105 may be etched at a temperature between about 50° C. and about 70° C. in a pressure between about 5 mTorr and about 100 mTorr using chemistry suitable for etching the second core layer 105 but not the spacers 109′. The second core layer 105 is thus highly etch selective to the spacers 109′. The second core layer 105 may be an amorphous carbon layer, or amorphous silicon layer. Above the second core layer 105 may be a cap layer 104, which may be a silicon anti-reflective coating, or PECVD dielectric layer, or spin-on glass.
[0043] In FIG. 6 , the spacers 109′ and the cap layer 104 are etched or otherwise removed, leaving the patterned second cores 105′. In some embodiments, the spacers 109′ may be removed at a temperature between about 10° C. and about 20° C. and at a pressure between about 2 mTorr and about 20 mTorr for a time of about 30 seconds. In some embodiments, the substrate may be etched at a temperature between about 40° C. and about 60° C. and at a pressure between about 5 mTorr and about 100 mTorr. In many embodiments, an anisotropic plasma etch is performed. In one example, the spacers 109′ are etched by first flowing about 10 sccm to about 100 sccm of chlorine (Cl2), then about 10 sccm to about 100 sccm of methane (CH4), then about 10 sccm to about 100 sccm of nitrogen (N2) for about 30 seconds.
[0044] In FIG. 7 , a second conformal film 119 is deposited over the patterned second cores 105′. In many embodiments, the second conformal film 119 may be a layer of titanium oxide, which may be deposited by PEALD methods.
[0045] In FIG. 8 , the second conformal film 119 is etched or planarized to expose the second cores 105′. Conditions and methods may be any of those discussed above with respect to FIG. 3 .
[0046] In FIG. 9 , the second cores 105′ is etched or removed, leaving free-standing second spacers 119′. Conditions and methods may be any of those discussed above with respect to FIG. 4 .
[0047] In FIG. 10 , the mask layer 107c is etched down using the second spacers 119′ as a mask, thereby transferring the pattern from the second spacers 119′ to form a patterned mask 107c′. Mask layer 107c may be highly etch selective to the second conformal film 119, and may be etched by any method discussed above with respect to FIG. 5 , depending on the chemistry of the mask layer 107c.
[0048] In FIG. 11 , the second spacers 119′ are removed, along with etch stop layer 107a and cap layer 107b, leaving the patterned mask 107c′. Conditions and methods for removing the second spacers 119′ may be any of those discussed above with respect to FIG. 6 . The mask 107c′ may then be used to pattern subsequent layers, such as target layer 150. The result of process steps depicted in FIGS. 1 through 11 is a quad-patterning scheme such that a single lithographically defined feature (such as a first core 103 in FIG. 1 ) results in four smaller features on the substrate. Quad patterning schemes may be used to form features with a half-pitch as small as 10 nm, or between 10 nm and 20 nm half-pitch, which cannot be achieved by current double patterning schemes.
[0049] Due to the nature of forming the smaller features, the material used for the second conformal film 119 may be of higher quality relative to conformal films used in spacers of wider cores so as to maintain robustness and prevent buckling when it is exposed to harsh conditions in subsequent patterning steps. Higher quality conformal film material may have near-ideal stoichiometry, such as if the conformal film is titanium oxide, the higher quality titanium oxide conformal film may have near ideal Ti:O stoichiometry, for example 1:2, and low carbon content. Higher quality conformal films may be deposited by ALD, which may perform a complete conversion from the oxidation half-reaction, thereby forming near ideal stoichiometry. Thus, higher quality conformal film material may then have a low etch rate and high etch selectivity, and also being infinitely selective against oxides and nitrides. These films may also have higher modulus, such as greater than about 150 MPa, which contributes to improved mechanical stability of the conformal film as a spacer, thereby improving critical dimension uniformity (CDU). The higher quality conformal film material disclosed herein may also be dense to withstand subsequent integration steps.
[0050] Provided herein are methods of depositing thin, conformal nanolaminate protective layers. Also provided are methods of forming high quality films that may be used as spacers, with the methods including deposition of a nanolaminate layer. The nanolaminate layers can improve spacer robustness while protecting the underlying core layer from degradation during deposition of the conformal film.
[0051] Deposition of high quality films, such as high quality titanium oxide, directly on a core layer may result in degradation or consumption of the core due to harsh conditions during deposition of the spacer, thereby harming the underlying patterned core. For example, during deposition of the high quality conformal film, a patterned core layer may be exposed to oxygen radicals, such as those produced from a N2O/O2 sequential plasma with a high HFRF power of at least about 1000 W. Due to the higher power, more oxygen radicals are formed, which increases radical bombardment on the core layer and subsequent degradation the pattern of the core. Nitrides may be able to withstand such bombardment if used as a cap over the core layer, but since nitrides are not selective to certain core materials, nitrides are not suitable. After a conformal film is deposited, the substrate may then be planarized to expose the core and remove the core, but since the core has been consumed or degraded, the resulting width between spacers may be diminished, which results in an irregular pattern in the semiconductor substrate. Rather than using lower quality conformal films to prevent degradation of the core, the methods disclosed herein enable high quality spacer materials.
[0052] Nanolaminate protective layers may be less dense than conformal film due to the lower HFRF power used during deposition. As such nanolaminate protective layers may be deposited at a minimum thickness that adequately protects the core. Minimizing the nanolaminate protective layer may facilitate subsequent integration. Nanolaminate protective layers may protect an underlying layer to the extent that a higher quality conformal film may be deposited over it. Core consumption and degradation thereby decreases and the core can withstand harsher conditions during deposition of the high quality conformal film. In subsequent patterning steps, the high quality conformal film can withstand other harsh conditions and still maintain its strong robustness as a free-standing structure. The nanolaminate protective layers may also prevent spacer leaning and enable critical dimension variability, by maintaining the integrity of the core geometry and providing mechanical support to the free-standing spacer structures, thereby enhancing the ability to form finer features at lower half-pitch in semiconductor processing.
[0053] An example of a method of using a nanolaminate protective layer may begin by providing a multi-stack semiconductor substrate with a lithographically defined or patterned first core layer, such as the one discussed above with respect to FIG. 1 . In some embodiments, a nanolaminate protective layer may be deposited on the first cores 103 prior to depositing a conformal film 109 as described in embodiments below with respect to FIG. 13 . In various embodiments, a conformal film 109 may be deposited over the first cores 103, such as in FIG. 2 . After the conformal film 109 is planarized, such as shown in FIG. 3 , the first cores 103 may be etched or removed to reveal the remaining spacers 109′, such as shown in FIG. 4 . A second core layer 105 may be etched down using the spacers 109′ as a mask to thereby transfer the pattern to form the second cores 105′ such as shown in FIG. 5 . The spacers 109′ may be removed to reveal patterned second cores 105′ such as shown in FIG. 12 . The second core layer 105 may be an amorphous carbon layer, or an amorphous silicon layer.
[0054] In FIG. 13 , a nanolaminate protective layer 111 may be deposited conformally over the second cores 105′. Examples of thicknesses of the nanolaminate layer 111 are between about 15 Å and about 200 Å thick, between about 15 Å and about 100 Å thick, or between about 15 Å and about 50 Å thick. Note that the thickness depicted in FIG. 13 is exaggerated for the purposes of the illustration and as an example only.
[0055] In some embodiments, the nanolaminate layer 111 may include a stack, which may have two or more sublayers (not shown). For example, the stack may be a bilayer. In some embodiments the sublayers have the same composition, and in some embodiments, the sublayers have different compositions. In some embodiments, the nanolaminate layer 111 is one layer. In one example, the nanolaminate layer 111 is one layer of silicon oxide. In another example, the nanolaminate layer 111 is one layer of titanium oxide. In one example of a bilayer nanolaminate layer 111, the upper layer is silicon oxide, and the lower layer is titanium oxide. In another example of a bilayer nanolaminate layer 111, the upper layer is titanium oxide and the lower layer is silicon oxide.
[0056] The nanolaminate layer 111 may also be less dense than the material deposited in a conformal film due to the lower HFRF power which may be used to deposit the nanolaminate layer 111. In some embodiments, the nanolaminate layer 111 may be an ALD oxide, such as silicon oxide (SiO2) or titanium oxide (TiO2) and referred to as “soft” ALD oxide. The thickness of the nanolaminate layer 111 may be taken into account when configuring processing conditions for the patterning scheme and deciding the pattern to be etched. In various embodiments, the nanolaminate layer 111 is deposited by conformal film deposition (CFD) or PEALD.
[0057] In FIG. 14 , the second conformal film 129 is deposited over the nanolaminate layer 111. In certain embodiments, the second conformal film 129 is a high quality titanium oxide film, such as a titanium oxide layer with a low wet etch rate and high dry etch selectivity with infinite selectivity against oxides such as silicon oxide (SiO2) and nitrides such as silicon nitride (SiN). For example, the second conformal film 129 may have an etch selectivity greater than 3:1 relative to an amorphous carbon layer. In some embodiments, second conformal film 129 has an etch selectivity greater than 15:1 relative to a poly silicon layer in halide etch chemistry. In one example, a nanolaminate layer 111 deposited to a thickness of about 15 Å may be sufficient to protect second cores 105′ from deposition of about 110 Å of the second conformal film 129. In various embodiments, the second conformal film 129 is deposited by CFD or PEALD. In some embodiments the second conformal film 129 is denser than the nanolaminate layer 111.
[0058] In FIG. 15 , the substrate is planarized to expose the second cores 105′ with nanolaminate layer 111 sidewalls and yield sidewall second spacers 129′. The conditions for the planarization may be any of those described above with respect to FIG. 3 .
[0059] In FIG. 16 , the second cores 105′ are etched and removed. Conditions and methods may be any of those discussed above with respect to FIG. 9 . In some embodiments, a small portion of the nanolaminate layer 111 may be etched due to the nature of the etching step. In some embodiments, the nanolaminate layer 111 is sufficiently etch selective and is not etched while the second cores 105′ are removed. Note the second spacers 129′ are sitting on a thin layer of nanolaminate layer 111 with a thin nanolaminate layer 111 on its sidewall, which may thereby reinforce its stability and prevent leaning. Still further, in some embodiments, the nanolaminate material may be completely removed with the second cores 105′. As noted above, in some embodiments, the thickness of the nanolaminate layer 111 and how much of it will be removed may be taken into account when planning the patterning scheme to arrive at the desired dimension. However, in some embodiments, the thickness of the nanolaminate layer 111 may be within the tolerance of the patterned dimensions, and may not need to be accounted for.
[0060] In FIG. 17 , the mask layer 107c is etched down using the second spacers 129′ as a mask. Due to the increased stability and robustness of the higher quality second spacers 129′, this operation may be more easily and more efficiently completed to form fine, stable features with high aspect ratios.
[0061] In FIG. 18 , the nanolaminate layer 111 and second spacers 129′ are etched or removed to reveal the resulting patterned mask 107c′. Conditions and methods may be any of those described above with respect to FIG. 5 . The patterned mask 107c′ may then be used to pattern a subsequent layer, which can be used to pattern the target layer 150. In some embodiments, the patterned mask 107c′ may be used to pattern the target layer 150.
[0062] FIG. 19 is a process flow diagram of steps of a method in accordance with various embodiments. Cycle and exposure times described herein may depend on the apparatus and platform used and one of ordinary skill in the art may adjust cycle and exposure times accordingly. In operation 1901, a substrate may be exposed to a first precursor, such as a titanium-containing precursor or silicon-containing precursor. In some embodiments, the substrate includes a core layer. In various embodiments, the core layer is amorphous carbon, amorphous silicon, or a photoresist. In some embodiments, the core layer is lithographically defined or patterned. In a certain embodiment, the substrate includes a patterned amorphous carbon layer.
[0063] Examples of a titanium-containing precursor include tetrakis(dimethylamino)titanium (TDMAT), tetraethoxytitanium, tetrakis-dimethyl-amido titanium, titanium isopropoxide, titanium tetraisopropoxide, and titanium tetrachloride. A silicon-containing precursor may be, for example, a silane, a halosilane or an aminosilane. A silane contains hydrogen and/or carbon groups, but does not contain a halogen. Examples of silanes are silane (SiH4), disilane (Si2H6), and organo silanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, tetra-ethyl-ortho-silicate (also known as tetra-ethoxy-silane or TEOS) and the like. A halosilane contains at least one halogen group and may or may not contain hydrogens and/or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Although halosilanes, particularly fluorosilanes, may form reactive halide species that can etch silicon materials, in certain embodiments described herein, the silicon-containing reactant is not present when a plasma is struck. Specific chlorosilanes are tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens and carbons. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilane (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3 and Si(NH2)4, respectively), as well as substituted mono-, di-, tri- and tetra-aminosilanes, for example, t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tertiarybutylamino)silane (SiH2(NHC(CH3)3)2 (BTBAS), tert-butyl silylcarbamate, SiH(CH3)—(N(CH3)2)2, SiHCl—(N(CH3)2)2, (Si(CH3)2NH)3 and the like. A further example of an aminosilane is trisilylamine (N(SiH3)3).
[0064] After operation 1901, the deposition chamber may be purged in a sweep phase with an injector purge or a pump away step. Generally, a sweep phase removes or purges one of the vapor phase reactant from a reaction chamber and typically occurs only after delivery of such reactant is completed. In other words, that reactant is no longer delivered to the reaction chamber during the sweep phase. However, the reactant remains adsorbed on the substrate surface during the sweep phase. Typically, the sweep serves to remove any residual vapor phase reactant in the chamber after the reactant is adsorbed on the substrate surface to the desired level. A sweep phase may also remove weakly adsorbed species (e.g., certain precursor ligands or reaction by-products) from the substrate surface. In ALD, the sweep phase has been viewed as necessary to prevent gas phase interaction of two reactants or interaction of one reactant with a thermal, plasma or other driving force for the surface reaction. In general, and unless otherwise specified herein, a sweep/purge phase may be accomplished by (i) evacuating a reaction chamber, and/or (ii) flowing gas not containing the species to be swept out through the reaction chamber. In the case of (ii), such gas may be, for example, an inert gas.
[0065] In operation 1903, the substrate may be exposed to a second precursor or an oxidant. In some embodiments, the oxidant is nitrous oxide (N2O) or oxygen (O2) or carbon dioxide (CO2) or a mixture or combinations thereof. In some embodiments, the oxidizer may be a mixture of oxygen (O2) and a weak oxidizer such as N2O, CO, CO2, NO, NO2, SO, SO2, CxHyOz and/or H2O. In other implementations, the oxidation reactant may be entirely a weak oxidizer. Alternatively, the oxidation reactant may include O3. In some embodiments, the oxidation reactant is about 0-50% O2 and about 50-100% weak oxidizer.
[0066] In some cases, one of the reactants may be delivered continuously (e.g., even during delivery of other reactants and/or during plasma exposure). For example, an oxidizing reactant may be delivered continuously. The continuously flowing reactant may be delivered to the reaction chamber in conjunction with a carrier gas such as argon. In some cases, the delivery of the continuously flowing reactants to reaction chamber is controlled by using divert valve/inlet valve toggling. Gas flow changes may be diverted or co-flowed. In one example, a continuously flowing reactant is periodically diverted from the reaction chamber such that it is only delivered to the reaction chamber at certain periods. The continuously flowing gas may be diverted to an outlet/dump using appropriate valves. For instance, an oxidizing reactant may flow continuously, but only be delivered to the reaction chamber periodically. When the oxidizing reactant is not being delivered to the reaction chamber, it may be diverted to an outlet, recycle system, etc.
[0067] In operation 1905, a plasma may be initiated with a low HFRF power while the substrate is exposed to the oxidant. In some embodiments, the low HFRF power per area of the wafer may be between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2 where mm2 represents the unit for surface area of the wafer. Plasma power may be scaled linearly with wafer surface area. For example, a low HFRF power may be between about 12.5 W to about 125 W per station for a 300 mm wafer, or between about 28 W and about 280 W for a 450 mm wafer. The deposition temperature may be between about 50° C. and about 150° C. After operation 1905, the deposition chamber may be purged again. These steps may be repeated until the desired thickness of the film is deposited.
[0068] In some embodiments, operation 1905 may occur at a low temperature, such as a temperature less than about 100° C. with an HFRF power while exposing a 300 mm substrate to the oxidant between about 50 W and about 500 W in a four-station tool, the power being the total power applied to the four-station tool.
[0069] In operation 1907, the substrate may be exposed to a titanium-containing precursor. Examples of titanium-containing precursors may be any of those described with respect to operation 1901. As an example, the substrate may be exposed to TDMAT for about 2 seconds, which may be described as a “dose.” After operation 1907, the deposition chamber may be purged with an injector purge or pump away step. As an example, the purge may last about 10 seconds.
[0070] In operation 1909, the substrate may be exposed to another precursor or an oxidant. In many embodiments, the oxidant is nitrous oxide (N2O) or oxygen (O2) or carbon dioxide (CO2) or a mixture thereof. As an example, operation 1909 may be about 30 seconds, such that for the first 25 seconds, no oxidant is flowed and only a carrier gas or inert gas is flowed, and an oxidant is flowed starting after the 25 seconds and is kept on through the next operation. Examples of carrier gases include argon (Ar) and nitrogen (N2). The flow rate of these carrier gases may be between about 0 sccm and about 10,000 sccm.
[0071] In operation 1911, a plasma may be initiated with high HFRF power while the substrate is exposed to the oxidant. In many embodiments, the HFRF power may be between about 125 W and about 1500 W per station for 300 mm wafers. As an example, HFRF power may be about 625 W per station. The plasma may be initiated for a time between about 0.25 seconds and about 3 seconds, or about 0.5 seconds. Operations 1907 through 1911 may occur at a temperature between about 50° C. and about 400° C., or between about 50° C. and 200° C., or about 150° C. and at a pressure between about 3 Torr and about 3.5 Torr. After operation 1911, the plasma may be turned off and the chamber may be purged or pumped to base. Example purge gases for use after operations 1901, 1903, 1905, 1907, 1909, and 1911 may be argon (Ar) or nitrogen (N2) or any other suitable purge gas. In some embodiments, the density of the film deposited in operations 1901 through 1905 may be less dense than the film deposited in operations 1907 through 1911.
[0072] According to various embodiments, operations 1901 through 1905 may be performed at a lower temperature, and/or lower RF power, and/or shorter RF time, and/or lower pressure, and/or with a weaker oxidant than operations 1907 through 1911. These deposition conditions may help prevent damage to the underlying substrate while producing an operable device.
[0073] FIG. 20A provides a process flow diagram of a method of using nanolaminate layers in accordance with various embodiments. In operation 2001, a core layer may be deposited, such as those described with respect to FIG. 1 . The core layer may be an amorphous carbon layer, or amorphous silicon layer, or may be a photoresist. In some embodiments, the core layer is patterned. In operation 2003, a nanolaminate layer is deposited on the core layer. The nanolaminate layer may be deposited by CFD or PEALD methods. The nanolaminate layer may be deposited using operations 1901-1905 with respect to FIG. 19 above. In some embodiments the nanolaminate layer may be silicon oxide (SiO2) or titanium oxide (TiO2). The thickness of the deposited nanolaminate layer may be between about 15 Å and about 200 Å, or between about 15 Å and about 100 Å. In operation 2005, a metal nitride or metal oxide layer may be deposited on the nanolaminate layer. The metal nitride or metal oxide layer may be deposited using operations 1907 through operation 1911 with respect to FIG. 19 above. In some embodiments, the metal nitride or metal oxide layer is a silicon oxide or titanium oxide layer. In some embodiments, the metal nitride or metal oxide layer is a high quality titanium oxide layer. In various embodiments, the metal nitride or metal oxide layer has a high etch selectivity to the core. In many embodiments, the metal nitride or metal oxide layer is denser than the nanolaminate layer.
[0074] FIG. 20B is a process flow diagram of an example of a method of using a nanolaminate layer in accordance with various embodiments. In operation 2011, a thin nanolaminate layer is deposited on a substrate. A nanolaminate layer may be any of those discussed above with respect to FIGS. 13 and 20A . The nanolaminate layer may be deposited using operations 1901-1905 with respect to FIG. 19 above. In operation 2013, a titanium oxide layer may be deposited on the nanolaminate layer. An example of a titanium oxide layer deposited on a nanolaminate layer is described above with respect to FIG. 14 . The titanium oxide layer may be deposited using operations 1907 through operation 1911 with respect to FIG. 19 above.
[0075] Apparatus
[0076] Deposition techniques provided herein may be implemented in a plasma enhanced chemical vapor deposition (PECVD) reactor or a conformal film deposition (CFD) reactor. Such a reactor may take many forms, and may be part of an apparatus that includes one or more chambers or “reactors” (sometimes including multiple stations) that may each house one or more wafers and may be configured to perform various wafer processing operations. The one or more chambers may maintain the wafer in a defined position or positions (with or without motion within that position, e.g., rotation, vibration, or other agitation). In one implementation, a wafer undergoing film deposition may be transferred from one station to another within a reactor chamber during the process. In other implementations, the wafer may be transferred from chamber to chamber within the apparatus to perform different operations, such as etching operations or lithography operations. The full film deposition may occur entirely at a single station or any fraction of the total film thickness for any deposition step. While in process, each wafer may be held in place by a pedestal, wafer chuck, and/or other wafer-holding apparatus. For certain operations in which the wafer is to be heated, the apparatus may include a heater, such as a heating plate. A Vector™ (e.g., C3 Vector) or Sequel™ (e.g., C2 Sequel) reactor, produced by Lam Research Corp. of Fremont, Calif., are both examples of suitable reactors that may be used to implement the techniques described herein.
[0077] FIG. 21 provides a simple block diagram depicting various reactor components arranged for implementing methods described herein. As shown, a reactor 2100 includes a process chamber 2124 that encloses other components of the reactor and serves to contain a plasma generated by a capacitive-discharge type system including a showerhead 2114 working in conjunction with a grounded heater block 2120. A high frequency (HF) radio frequency (RF) generator 2104 and a low frequency (LF) RF generator 2102 may be connected to a matching network 2106 and to the showerhead 2114. The power and frequency supplied by matching network 2106 may be sufficient to generate a plasma from process gases supplied to the process chamber 2124. For example, the matching network 2106 may provide 50 W to 500 W of HFRF power. In some examples, the matching network 2106 may provide 100 W to 5000 W of HFRF power and 100 W to 5000 W of LFRF power total energy. In a typical process, the HFRF component may generally be between 5 MHz to 60 MHz, e.g., 13.56 MHz. In operations where there is an LF component, the LF component may be from about 100 kHz to 2 MHz, e.g., 430 kHz.
[0078] Within the reactor, a wafer pedestal 2118 may support a substrate 2116. The wafer pedestal 2118 may include a chuck, a fork, or lift pins (not shown) to hold and transfer the substrate during and between the deposition and/or plasma treatment reactions. The chuck may be an electrostatic chuck, a mechanical chuck, or various other types of chuck as are available for use in the industry and/or for research.
[0079] Various process gases may be introduced via inlet 2112. Multiple source gas lines 2110 are connected to manifold 2108. The gases may be premixed or not. Appropriate valving and mass flow control mechanisms may be employed to ensure that the correct process gases are delivered during the deposition and plasma treatment phases of the process. In the case where a chemical precursor(s) is delivered in liquid form, liquid flow control mechanisms may be employed. Such liquids may then be vaporized and mixed with process gases during transportation in a manifold heated above the vaporization point of the chemical precursor supplied in liquid form before reaching the deposition chamber.
[0080] Process gases may exit chamber 2124 via an outlet 2122. A vacuum pump, e.g., a one or two stage mechanical dry pump and/or turbomolecular pump 2140, may be used to draw process gases out of the process chamber 2124 and to maintain a suitably low pressure within the process chamber 2124 by using a closed-loop-controlled flow restriction device, such as a throttle valve or a pendulum valve.
[0081] As discussed above, the techniques for deposition discussed herein may be implemented on a multi-station or single station tool. In specific implementations, a 300 mm Lam Vector™ tool having a 4-station deposition scheme or a 200 mm Sequel™ tool having a 6-station deposition scheme may be used. In some implementations, tools for processing 450 mm wafers may be used. In various implementations, the wafers may be indexed after every deposition and/or post-deposition plasma treatment, or may be indexed after etching steps if the etching chambers or stations are also part of the same tool, or multiple depositions and treatments may be conducted at a single station before indexing the wafer.
[0082] In some embodiments, an apparatus may be provided that is configured to perform the techniques described herein. A suitable apparatus may include hardware for performing various process operations as well as a system controller 2130 having instructions for controlling process operations in accordance with the disclosed embodiments. The system controller 2130 will typically include one or more memory devices and one or more processors communicatively connected with various process control equipment, e.g., valves, RF generators, wafer handling systems, etc., and configured to execute the instructions so that the apparatus will perform a technique in accordance with the disclosed embodiments, e.g., a technique such as that provided in the deposition steps of FIG. 19 . Machine-readable media containing instructions for controlling process operations in accordance with the present disclosure may be coupled to the system controller 2130. The controller 2130 may be communicatively connected with various hardware devices, e.g., mass flow controllers, valves, RF generators, vacuum pumps, etc. to facilitate control of the various process parameters that are associated with the deposition operations as described herein.
[0083] In some embodiments, a system controller 2130 may control all of the activities of the reactor 2100. The system controller 2130 may execute system control software stored in a mass storage device, loaded into a memory device, and executed on a processor. The system control software may include instructions for controlling the timing of gas flows, wafer movement, RF generator activation, etc., as well as instructions for controlling the mixture of gases, the chamber and/or station pressure, the chamber and/or station temperature, the wafer temperature, the target power levels, the RF power levels, the substrate pedestal, chuck, and/or susceptor position, and other parameters of a particular process performed by the reactor apparatus 2100. The system control software may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components necessary to carry out various process tool processes. The system control software may be coded in any suitable computer readable programming language.
[0084] The system controller 2130 may typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a technique in accordance with the present disclosure. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller 2130.
[0085] The method and apparatus described herein may be used in conjunction with lithographic patterning tools or processes such as those described below for fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following steps, each step performed with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate or multi-layer stack as provided in disclosed embodiments, using a spin-on or spray-on tool; (2) curing a photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferred the resist pattern into an underlying film or workpiece, such as an amorphous carbon layer, by using a dry or plasma-assisted etching tool such as those described below; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In one implementation, one or more gap features on a wafer are filled with a carbon film using a technique as described herein. The carbon film may then be used, for example, for one of the purposes described herein. Further the implementation may include one or more of steps (1) through (6) described above.
[0086] One or more process stations may be included in a multi-station processing tool. FIG. 22 shows a schematic view of an embodiment of a multi-station processing tool 2200 with an inbound load lock 2202 and an outbound load lock 2204, either or both of which may include a remote plasma source. A robot 2206, at atmospheric pressure, is configured to move wafers from a cassette loaded through a pod 2208 into inbound load lock 2202 via an atmospheric port 2210. A wafer is placed by the robot 2206 on a pedestal 2212 in the inbound load lock 2202, the atmospheric port 2210 is closed, and the load lock is pumped down. Where the inbound load lock 2202 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment in the load lock prior to being introduced into a processing chamber 2214. Further, the wafer also may be heated in the inbound load lock 2202 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 2216 to processing chamber 2214 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted includes load locks, it will be appreciated that, in some embodiments, direct entry of a wafer into a process station may be provided.
[0087] The depicted processing chamber 2214 includes four process stations, numbered from 1 to 4 in the embodiment shown in FIG. 22 . Each station has a heated pedestal (shown at 2218 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between a CFD and PECVD process mode. Additionally or alternatively, in some embodiments, processing chamber 2214 may include one or more matched pairs of CFD and PECVD process stations. While the depicted processing chamber 2214 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.
[0088] FIG. 22 also depicts an embodiment of a wafer handling system 2290 for transferring wafers within processing chamber 2214. In some embodiments, wafer handling system 2290 may transfer wafers between various process stations and/or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 22 also depicts an embodiment of a system controller 2250 employed to control process conditions and hardware states of process tool 2200. System controller 2250 may include one or more memory devices 2256, one or more mass storage devices 2254, and one or more processors 2252. Processor 2252 may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.
[0089] In some embodiments, system controller 2250 controls all of the activities of process tool 2200. System controller 2250 executes system control software 2258 stored in mass storage device 2254, loaded into memory device 2256, and executed on processor 2252. Alternatively, the control logic may be hard coded in the controller 2250. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. System control software 2258 may include instructions for controlling the timing, mixture of gases, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power levels, RF power levels, RF exposure time, substrate pedestal, chuck and/or susceptor position, and other parameters of a particular process performed by process tool 2200. System control software 2258 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components necessary to carry out various process tool processes. System control software 2258 may be coded in any suitable computer readable programming language.
[0090] In some embodiments, system control software 2258 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a CFD process may include one or more instructions for execution by system controller 2250. The instructions for setting process conditions for a CFD process phase may be included in a corresponding CFD recipe phase. In some embodiments, the CFD recipe phases may be sequentially arranged, so that all instructions for a CFD process phase are executed concurrently with that process phase.
[0091] Other computer software and/or programs stored on mass storage device 2254 and/or memory device 2256 associated with system controller 2250 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.
[0092] A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 2218 and to control the spacing between the substrate and other parts of process tool 2200.
[0093] A process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. In some embodiments, the controller includes instructions for depositing a nanolaminate protective layer on a core layer, and depositing a conformal layer over the protective layer.
[0094] A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc. In some embodiments, the controller includes instructions for depositing a nanolaminate protective layer on a core layer, and depositing a conformal layer over the protective layer.
[0095] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate. In certain implementations, the controller includes instructions for depositing a nanolaminate protective layer at a first temperature, and a conformal layer over the protective layer at a second temperature, where the second temperature is higher than the first temperature.
[0096] A plasma control program may include code for setting RF power levels and exposure times in one or more process stations in accordance with the embodiments herein. In some embodiments, the controller includes instructions for depositing a nanolaminate protective layer at a first RF power level and RF duration, and depositing a conformal layer over the protective layer at a second RF power level and RF duration. The second RF power level and/or the second RF duration may be higher/longer than the first RF power level/duration.
[0097] In some embodiments, there may be a user interface associated with system controller 2250. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
[0098] In some embodiments, parameters adjusted by system controller 2250 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels and exposure times), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.
[0099] Signals for monitoring the process may be provided by analog and/or digital input connections of system controller 2250 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of process tool 2200. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.
[0100] System controller 2250 may provide program instructions for implementing the above-described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.
[0101] The system controller will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with the disclosed embodiments. Machine-readable, non-transitory media containing instructions for controlling process operations in accordance with the disclosed embodiments may be coupled to the system controller.
EXPERIMENTAL
Experiment 1
[0102] Experiments were conducted to compare deposited spacer or conformal films on unprotected cores and those deposited on cores protected by a nanolaminate protective layer. In the first trial, a substrate with a patterned core layer made of amorphous carbon was provided. High quality titanium oxide was deposited directly on the core layer by a plasma enhanced atomic layer deposition (PEALD) or conformal film deposition (CFD) method. The chamber pressure was about 3 Torr and at a temperature about 150° C. The substrate was exposed to the first precursor, TDMAT, for 2 seconds, followed by a 10 second purge. The substrate was then exposed to a mixture of oxidants N2O/O2 in a 30 second exposure where the first 25 seconds involved flowing only the carrier gas N2 (at a flow rate of up to 9500 sccm) and in the last five seconds, the N2O/O2 flow was turned on and stayed on until the plasma was initiated for 0.5 seconds. The plasma was initiated with a high frequency radio frequency (HFRF) power of 625 W per station, or 2500 W for four stations. The N2O/O2 flow and plasma were turned off at the same time after the 0.5 second plasma exposure, and lastly the chamber was pumped to base to purge the chamber. An image of the deposited conformal film and the underlying core layer is shown in FIG. 23A . The degraded core layer 2304a is shown underneath the titanium oxide (TiO2) conformal film layer 2302a.
[0103] In the second trial, a substrate with a patterned core layer made of amorphous carbon was also provided. A silicon oxide (SiO2) nanolaminate protective layer was deposited on the core layer by PEALD. Deposition chamber temperature was 50° C. and pressure of the chamber was 1.8 Torr. The substrate was exposed to a silicon-containing precursor 0.2 seconds, followed by a 0.2 second purge. The substrate was then exposed to a mixture of oxidants N2O/O2 in a 0.3 second exposure. A plasma was initiated for the four-station chamber at 1000 W, or about 500 W per station. The N2O/O2 flow and plasma were turned off and the chamber was purged. Subsequently, the substrate was exposed to TDMAT for 2 seconds, followed by a 10 second purge. Following the purge, the substrate was exposed to oxidants N2O/O2 in a 30 second exposure such that the mixture flowed only in the last 5 seconds and after the 30 seconds, continued to flow for 0.5 seconds while plasma was initiated for the 0.5 seconds at 625 W per station, or 2500 W for four stations. After both the plasma and the oxidants N2O/O2 flow were turned off, the chamber was again purged. An image of the deposited conformal film, nanolaminate layer, and underlying core layer is shown in FIG. 23B . As shown, the deposited conformal film 2302b was deposited on top of a nanolaminate layer 2306 which is so thin that it is indistinguishable from the conformal film and core layer it is adjacent to. Note that compared to FIG. 23A , the core mandrels 2304b have very little degradation or consumption.
[0104] In the third trial, a substrate with a patterned core layer made of amorphous carbon was also provided. A titanium oxide (TiO2) nanolaminate protective layer was deposited on the core layer by PEALD. Deposition chamber temperature was 150° C. and pressure of the chamber was 3.0 Torr. The substrate was exposed to TDMAT for 2 seconds, followed by a 10 second purge. The substrate was then exposed to a mixture of oxidants N2O/O2 in a 30 second exposure such that the mixture flowed only in the last 5 seconds and after the 30 seconds, continued to flow for 0.5 seconds while a plasma was initiated for the four-station chamber at 1000 W, or about 500 W per station. The N2O/O2 flow and plasma were turned off and the chamber was purged. Subsequently, the substrate was exposed to TDMAT for 2 seconds, followed by a 10 second purge. Following the purge, the substrate was exposed to oxidants N2O/O2 in a 30 second exposure such that the mixture flowed only in the last 5 seconds and after the 30 seconds, continued to flow for 0.5 seconds while plasma was initiated for the 0.5 seconds at 625 W per station, or 2500 W for four stations. After both the plasma and the oxidants N2O/O2 flow were turned off, the chamber was again purged. An image of the deposited conformal film, nanolaminate layer, and underlying core layer is shown in FIG. 23C . As shown, the deposited conformal film 2302c was deposited on top of a nanolaminate layer 2308 which is so also thin that it is indistinguishable from the conformal film and core layer it is adjacent to. Note that the core mandrels 2304c have very little degradation or consumption.
Experiment 2
[0105] Another series of experiments were conducted using the same conditions as those described with respect to the three trials above, but for blanket substrates with no features. In each trial, the thickness of the amorphous carbon layer was measured, then the spacer was deposited and the spacer thickness was measured, and lastly the thickness of the remaining amorphous carbon layer after spacer deposition was measured. The carbon consumption was calculated by subtracting the thickness after spacer deposition from the thickness before spacer deposition. The results of this series of experiments are shown in Table 1.
[0106]
| TABLE 1 | |||||||
|---|---|---|---|---|---|---|---|
| Carbon Consumption and Nanolaminate Layers | |||||||
| Trial 1 | Trial 2 | Trial 3 | |||||
| Nanolam- | Composition | None | SiO2 | TiO2 | |||
| inate | Deposition Power | 500 | W | 500 | W | ||
| Deposition | 50° | C. | 150° | C. | |||
| Temperature | |||||||
| Thickness Deposited | 1.44 | nm | |||||
| (TEM) | |||||||
| Spacer | Thickness Deposited | 5.9 | nm | 4.7 | nm | ||
| (TEM) | |||||||
| Amorphous | Thickness Before | 43.886 | nm | 44.1 | nm | 45.0 | nm |
| Carbon | Spacer Deposition | ||||||
| Thickness After | 28.36 | nm | 35.3 | nm | 36.4 | nm | |
| Spacer Deposition | |||||||
| Carbon | 15.4 | nm | 8 | nm | 8.6 | nm | |
| Consumption | |||||||
[0107] As shown in the table, presence of the nanolaminate layer reduced carbon consumption substantially. Without the nanolaminate layer, carbon consumption was 15.4 nm, whereas for both the SiO2 and TiO2 nanolaminate layers, carbon consumption was only about 8 nm. Thus, depositing a nanolaminate layer over an amorphous carbon layer, particularly patterned amorphous carbon layer, protects the amorphous carbon layer when the spacer is deposited and higher quality films may be deposited for spacer deposition as a result.
CONCLUSION
[0108] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.
Claims
What is claimed is:
1. A method of processing a semiconductor substrate, the method comprising:
depositing a nanolaminate layer on the substrate; and
depositing a titanium oxide layer on the nanolaminate layer, the nanolaminate layer having a thickness of between about 15 Å and about 200 Å and a density lower than the density of the titanium oxide layer.
2. The method of claim 1, further comprising depositing an amorphous carbon layer, wherein the nanolaminate layer is deposited on the amorphous carbon layer.
3. The method of claim 2, wherein the amorphous carbon layer is a patterned layer.
4. The method of claim 1, wherein the nanolaminate layer comprises a stack comprising two or more sublayers.
5. The method of claim 4, wherein the two or more sublayers each comprise silicon oxide, or titanium oxide, or combinations thereof.
6. The method of claim 4, wherein the stack comprises no more than two sublayers.
7. The method of claim 6, wherein the nanolaminate layer comprises a first sublayer of silicon oxide and a second sublayer of titanium oxide.
8. The method of claim 1, wherein the nanolaminate layer comprises silicon oxide or titanium oxide.
9. The method of claim 1, wherein the nanolaminate layer is deposited using plasma-enhanced atomic layer deposition (PEALD) by:
exposing the substrate to a titanium-containing precursor or a silicon-containing precursor;
exposing the substrate to an oxidant; and
initiating a plasma while the substrate is exposed to the oxidant.
10. The method of claim 9, wherein the nanolaminate layer is deposited at a temperature between about 50° C. and about 150° C. and the plasma is initiated at a high frequency radio frequency (HFRF) power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2.
11. The method of claim 9, wherein the nanolaminate layer is deposited at a temperature less than about 100° C.
12. The method of claim 9, wherein the titanium-containing precursor comprises TDMAT.
13. The method of claim 1, wherein the titanium oxide layer is deposited by PEALD by:
exposing the substrate to a titanium-containing precursor;
exposing the substrate to an oxidant; and
initiating a plasma while the substrate is exposed to the oxidant at a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2.
14. The method of claim 13, wherein the oxidant comprises nitrous oxide or oxygen or carbon dioxide or a mixture thereof.
15. The method of claim 13, wherein the titanium-containing precursor comprises TDMAT.
16. The method of claim 13, wherein the titanium oxide layer is deposited at a pressure between about 3 Torr and about 3.5 Torr.
17. The method of claim 13, wherein the titanium oxide layer is deposited at a temperature between about 50° C. and about 400° C.
18. A method of processing a semiconductor substrate, the method comprising:
(a) exposing the substrate to a first titanium-containing precursor or a silicon-containing precursor;
(b) exposing the substrate to a first oxidant;
(c) initiating a first plasma while the substrate is exposed to the first oxidant with a HFRF power per square millimeter of substrate area between about 1.768×10−4 W per mm2 and about 1.768×10−3 W per mm2;
(d) exposing the substrate to a second titanium-containing precursor;
(e) exposing the substrate to a second oxidant; and
(f) initiating a second plasma while the substrate is exposed to the second oxidant with a HFRF power per square millimeter of substrate area of at least about 1.768×10−3 W per mm2.
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