Disk drive estimating repeatable runout of reference pattern based on repeatable runout of phase error

[0001] When manufacturing a disk drive, concentric servo sectors 2₀-2_N are written to a disk 4 which define a plurality of radially-spaced, concentric data tracks 6 as shown in the prior art disk format of FIG. 1. Each data track 6 is partitioned into a plurality of data sectors wherein the concentric servo sectors 2₀-2_N are considered “embedded” in the data sectors. Each servo sector (e.g., servo sector 2₄) comprises a preamble 8 for synchronizing gain control and timing recovery, a sync mark 10 for synchronizing to a data field 12 comprising coarse head positioning information such as a track number, and servo bursts 14 which provide fine head positioning information. The coarse head position information is processed to position a head over a target track during a seek operation, and the servo bursts 14 are processed to maintain the head over a centerline of the target track while writing or reading data during a tracking operation.

[0002] In the past, external servo writers have been used to write the concentric servo sectors 2₀-2_N to the disk surface during manufacturing. External servo writers employ extremely accurate head positioning mechanics, such as a laser interferometer, to ensure the concentric servo sectors 2₀-2_N are written at the proper radial location from the outer diameter of the disk to the inner diameter of the disk. However, external servo writers are expensive and require a clean room environment so that a head positioning pin can be inserted into the head disk assembly (HDA) without contaminating the disk. Thus, external servo writers have become an expensive bottleneck in the disk drive manufacturing process.

[0003] The prior art has suggested various “self-servo” writing methods wherein the internal electronics of the disk drive are used to write the concentric servo sectors independent of an external servo writer. For example, U.S. Pat. No. 5,668,679 teaches a disk drive which performs a self-servo writing operation by writing a plurality of spiral servo tracks to the disk which are then processed to write the concentric servo sectors along a circular path. Each spiral servo track is written to the disk as a high frequency signal (with missing bits), wherein the position error signal (PES) for tracking is generated relative to time shifts in the detected location of the spiral servo tracks. The read signal is rectified and low pass filtered to generate a triangular envelope signal representing a spiral servo track crossing, wherein the location of the spiral servo track is detected by detecting a peak in the triangular envelope signal relative to a clock synchronized to the rotation of the disk.

[0011] FIG. 2A shows a disk drive according to an embodiment of the present invention comprising a head 16 actuated over a disk 18 comprising a reference pattern (a plurality of spiral tracks 20₀-20_N in the embodiment shown). The disk drive further comprises control circuitry 22 operable to execute the flow diagram of FIG. 2B, wherein the head 16 is positioned at a first radial location R1 (block 24), a first phase error (PE₁) is measured in response to the reference pattern at the first radial location R1 (bock 26), and a first repeatable runout (RRO) of the first phase error is measured (block 28). The head is positioned at a second radial location R2 (block 30), a second phase error (PE₂) is measured in response to the reference pattern at the second radial location (block 32), and a second repeatable runout (RRO) of the second phase error is measured (block 34). The first and second RROs are processed to estimate an offset r₀ representing a difference between an axial rotation of the disk and an axial rotation of the reference pattern (block 36).

[0012] In the embodiment of FIG. 2A, the control circuitry 22 processes a read signal 40 emanating from the head 16 to demodulate servo sectors 38₀-38_N on the disk 18 and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 22 filters the PES using suitable compensation filters to generate a control signal 42 applied to a voice coil motor (VCM) 44 which rotates an actuator arm 46 about a pivot, thereby actuating the head 16 radially over the disk 18 in a direction that reduces the PES. The actual position of the head is measured by reading position information derived from the servo sectors 38₀-38_N, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern as shown in FIG. 1, or a suitable phase based servo pattern.

[0013] In one embodiment, the control circuitry 22 internal to the disk drive performs a self-servo write operation in order to write the servo sectors 38₀-38_N on the disk 18. During the self-servo write operation, the control circuitry 22 reads a reference pattern on the disk 18 in order to servo the head 16 while writing the servo sectors 38₀-38_N. In the embodiment of FIG. 2A, the reference pattern comprises a plurality of spiral tracks 20₀-20_N, wherein each spiral track comprises a high frequency signal periodically interrupted by a sync mark. When the head 16 moves in the radial direction, an eye pattern generated by reading a spiral track will shift (left or right) while the sync marks remain fixed (ideally). The shift in the eye pattern (detected from the high frequency signal) relative to the sync marks provides the off-track information (spiral position error signal (PES)) for servoing the head 16. Each spiral track may span a partial disk revolution as in the embodiment of FIG. 2A, or more than one disk revolution as illustrated in the embodiment of FIG. 3.

[0014] In on embodiment, the spiral track crossings are also used to synchronize a servo write clock used to write the servo sectors 38₀-38_N to the disk 18. The servo write clock is generated using a phase locked loop (PLL) where the phase error is measured based on when the sync marks are detected in each spiral track crossing. In an embodiment described below, the servo write clock is used to clock a modulo-N counter, and as each sync mark in a spiral track crossing is detected, the value of the modulo-N counter represents the phase error for adjusting the PLL.

[0015] The axis of rotation of the reference pattern recorded on the disk 18 may be offset from an axis of rotation of the disk 18. This is illustrated in FIG. 4A which shows an offset r₀ between Cspin (axis of disk) and Cseed (axis of reference pattern), wherein Cseed will rotate in a circle around Cspin (illustrated by a dashed line) as the disk 18 rotates. In one embodiment, the offset r₀ may be caused by an offset when clamping the disk 18 to a spindle motor after recording the reference pattern on the disk 18. In another embodiment, the control circuitry 22 may write the reference pattern on the disk 18, wherein the offset r₀ may be caused by errors in the writing process (written-in error).

[0016] As the disk 18 rotates and Cseed rotates around Cspin as shown in FIG. 4A, a repeatable runout (RRO) is induced in the phase error of the PLL that generates the servo write clock. The instantaneous RRO in the phase error relative to the rotation angle of the disk is represented by the angle Ψ₁ in FIG. 4A. In addition, the angle Ψ₁ representing the RRO in the phase error will reach a peak when the distance R1 of the head 16 from Cseed forms a right angle with the offset r₀. Although the location of the head 16 can be determined relative to the reference pattern, the distance R1 of the head 16 from Cseed is unknown (because r₀ is unknown).

[0017] In one embodiment in order to estimate the offset r₀, the head 16 is positioned at a first radial location R1 as shown in FIG. 4A and a first peak Ψ₁ in a first RRO of the phase error is measured. The head 16 is then positioned at a second radial location R2 as shown in FIG. 4B and a second peak Ψ₂ in a second RRO of the phase error is measured. The offset r₀ may then be estimated in one embodiment as follows:
R2−R1=r₀/tan Ψ₂−r₀/tan Ψ₁
then

[0018] $\begin{array}{cc}{r}_0=\frac{\left(R2-R1\right)}{\left(1/\tan {\psi }_2-1/\tan {\psi }_1\right)}& \left(\mathrm{FIG}.5\right)\end{array}$
The phase of the offset r₀ relative to the rotation angle of the disk 18 may be determined relative to the angle of the disk 18 when the RRO in the phase error reaches its peak. In the example shown in FIGS. 4A and 4B, the rotation angle of the disk 18 is slightly different between the first peak Ψ₁ and the second peak Ψ₂. In one embodiment, the phase of the offset r₀ may be computed as the average of the rotation phase of the disk measured at the first peak Ψ₁ and the second peak Ψ₂.

[0019] Estimating the offset r₀ using the above equation assumes the head 16 follows the RRO in the position error while servoing on the reference pattern (e.g., using feed-forward compensation). In this manner, the distance between R1 and R2 can be measured based on the corresponding tracks defined by the reference pattern when Ψ₁ and Ψ₂ reach their peak. In another embodiment, the RRO may be canceled from the position error while servoing on the reference pattern. In this embodiment, R1 and R2 may be measured along the axis aligned with Cspin based on the corresponding tracks defined by the reference pattern when Ψ₁ and Ψ₂ reach their peak. Accordingly, the above equation in this embodiment is modified to derive the estimate for the offset r₀ based on the measured hypotenuse of the right triangles shown in FIGS. 4A and 4B.

[0020] FIG. 6A shows a timing control loop according to an embodiment of the present invention wherein an oscillator 48 generates the servo write clock 50 that clocks a modulo-N counter 52. The output 54 of the modulo-N counter represents a measured phase of the servo write clock 50 which is subtracted from a target phase 56 to generate a phase error 58. The phase error 58 is filtered with a suitable compensator 60 to generate a control signal 62. The phase error 58 comprises a RRO due to the offset r₀ between Cspin and Cseed as described above. In this embodiment, the RRO in the phase error 58 may be learned by adapting coefficients a1,b1 (block 64) of a sinusoid 66 that generates feed-forward timing compensation values 68. The sinusoid is generated according to:

[0021] $a1\cos \left(\left(2\pi ·\left(\frac{k}{N}\right)\right)+\left(2\pi ·\frac{r}{r_1}\right)\right)+b1\sin \left(\left(2\pi ·\left(\frac{k}{N}\right)\right)+\left(2\pi ·\frac{r}{r_1}\right)\right)$
where a1 and b1 are the first coefficients, k is the kth spiral track out of N spiral tracks, r is the radial location of the head, and r₁ represents a part of the radius of the disk spanned by a complete revolution of the spiral tracks (as illustrated in FIG. 3).

[0022] The feed-forward timing compensation values 68 adjust the control signal 62 to generate an adjusted control signal 70 used to adjust the frequency of the oscillator 48. The coefficients a1,b1 are adapted 64 in order to drive the RRO in the phase error 58 toward zero. Once the coefficients a1,b1 have adapted, the resulting sinusoid 66 represents the RRO in the phase error 58, and the peak in the sinusoid 66 represents the peak in the RRO (Ψ₁ or Ψ₂ described above).

[0023] FIG. 6B shows an alternative embodiment of the present invention wherein coefficients a1,b1 of a sinusoid 72 may be adapted 74 in response to the phase error 58 to generate timing compensation values 76 that are subtracted from the phase error 58 in order to generate an adjusted phase error 78. The coefficients a1,b1 are adapted until the RRO is substantially canceled from the adjusted phase error 78, thereby generating a servo write clock 50 that is synchronized to the rotation of the disk 18 rather than to the rotation of the reference pattern as in the embodiment of FIG. 6A. Similar to the embodiment of FIG. 6A, after the coefficients a1,b1 have adapted, the resulting sinusoid 72 represents the RRO in the phase error 58, and the peak in the sinusoid 72 represents the peak in the RRO (Ψ₁ or Ψ₂ described above).

[0024] The estimated offset r₀ (amplitude and/or phase) may be used in any suitable manner. For example, the estimated offset r₀ may be used to generate compensation values for a position control loop and/or a timing control loop when writing the product servo sectors 38₀-38_N to the disk while servoing the head 16 off of the reference pattern (e.g., the spiral tracks 20₀-20_N shown in FIG. 2A). The compensation values may be used to follow an RRO in a position error or phase error, or the compensation values may be used to cancel the RRO.

[0025] Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.

[0026] In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.