Inductor current measurement for DC to DC converters

[0001] The present application is related to U.S. patent application Ser. No. 12/622,478 filed Nov. 20, 2009. The disclosure of the above application is incorporated herein by reference in its entirety.

[0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] Many analog and digital power supplies, including average current mode power supplies, include DC to DC converters. DC to DC converters can be of different types (e.g., Buck, boost, Buck-boost, fly-back, etc.). Buck type DC to DC converters include an inductor in an output stage. An output voltage of the DC to DC converter may be regulated in many ways. For example, in average current mode power supplies, current through the inductor (inductor current) may be used to regulate the output voltage. Accordingly, sensing the inductor current is an important function of a controller for high-efficiency DC to DC converters.

[0004] The sensed inductor current can be used in a variety of applications. For example, the applications may include over-current protection, adaptive voltage positioning, and loop control for current-mode power supplies. Additionally, the sensed inductor current can be used to determine when to switch from Continuous Conduction Mode (CCM) to Discontinuous Conduction Mode (DCM). Further, the sensed inductor current can be used to calculate load current in a state space based controller, where estimated capacitor current is available.

[0005] Methods for sensing the inductor current need to be accurate, low cost, and have minimum impact on the overall efficiency of a DC to DC converter. Several methods are currently used to sense the inductor current. Each of these methods, however, has some shortcomings that make these methods undesirable for a leading-edge, high-precision, and fast-transient DC to DC converter. Some of these methods are described below.

[0006] Referring now to FIG. 1, a converter 10 uses a high-precision resistance connected in series with the inductor to sense the inductor current. The converter 10 comprises a pulse-width modulation (PWM) controller 12, a pair of series-connected switches 14 and 16, an inductor L, a high-precision sensing resistor R_sense, a capacitor C_out, and an amplifier 20. R_dc is a parasitic resistance of the inductor L.

[0007] The PWM controller 12 generates pulse-width modulated pulses that control on-off times of the switches 14 and 16. Current i flows through the inductor L and generates a voltage drop across the sensing resistor R_sense. The amplifier 20 has a gain of A_v and amplifies the voltage drop across the sensing resistor R_sense. The output of the amplifier 20 is given by i*R_sense*A_v. The inductor current i can be determined from the output of the amplifier 20.

[0008] This method suffers from losses in the sensing resistor R_sense, which reduces the overall efficiency of the converter 10. Additionally, this method suffers from effects of noise since the voltage drop across the sensing resistor R_sense used to sense the inductor current i is small. Further, the measurement circuits used to measure the inductor current i add a delay.

[0009] Instead of using the sensing resistor R_sense, an on-resistance (R_DSon) of the switches 14 and 16, can be used to sense the inductor current i. R_DSon is a resistance between a drain and a source of a switch when the switch is on. When the switch is on, R_DSon of the switch is in series with the inductor L, and the inductor current i generates a voltage drop across R_DSon (i.e., V_DS), which can be measured to sense the inductor current i.

[0010] While this method does not affect the efficiency of the converter, this method is not very accurate since the value of R_DSon varies based on temperature. Further, small signal levels of V_DS pose noise problems. Additionally, measurement circuits used to measure the inductor current i add a delay.

[0011] Referring now to FIG. 2, a converter 30 uses a resistor and a capacitor connected in parallel to the inductor to sense the inductor current. The converter 30 comprises the PWM controller 12, the switches 14 and 16, the inductor L, and the capacitor C_out. Additionally, a resistor R and a capacitor C are connected across the inductor L as shown. R_DC, the parasitic resistance of the inductor L, serves as the sensing resistor.

[0012] The values of R and C are chosen so that the impedance of the RC circuit formed by the resistor R and the capacitor C matches the impedance of the inductor L. In other words, the values of R and C are chosen so that the time constant of the RC circuit matches the time constant of the LR circuit formed by the inductor L and the parasitic resistance R_DC. That is, the values of R and C are chosen so that R*C≈L/R_DC.

[0013] When R*C≈L/R_DC, the voltage across the capacitor C is linearly proportional to the inductor current i. The amplifier 40 amplifies the voltage across the capacitor C and generates an output equal to i*R_DC*A_v. The inductor current i can be determined from the output of the amplifier 40.

[0014] The accuracy of this approach depends on how closely the impedance of the RC circuit matches the impedance of the inductor L. Further, small voltage levels across the capacitor C pose noise problems. Particularly, the sensed inductor current may include high-frequency noise. Additionally, measurement circuits used to measure the inductor current i add a delay.

[0015] A system comprises an averaging module, a high pass filter module, a first estimation module, a sensing module, and a combining module. The averaging module receives an output voltage of a power supply and that generates an average output voltage. The high pass filter module receives an average switching voltage used to control switches in an output stage of the power supply and filters a difference between the average output voltage and the average switching voltage. The estimation module estimates a first filtered current through an inductor in the output stage based on an output of the high pass filter module. The sensing module senses voltage across the inductor and estimates a second current through the inductor. The low pass filter module filters the second current. The combining module combines the first filtered current and the second filtered current to generate an estimated current through the inductor.

[0016] In other features, the high pass filter module includes a high pass filter having a first corner frequency. The low pass filter module includes a low pass filter having a second corner frequency. The first corner frequency is equal to the second corner frequency.

[0017] In other features, the high pass filter module includes a high pass filter having a first gain. The low pass filter module includes a low pass filter having a second gain. The first gain is equal to the second gain.

[0018] In other features, the high pass filter module includes a high pass filter having a first pole. The low pass filter module includes a low pass filter having a second pole. The first pole is equal to the second pole.

[0019] In another feature, the sensing module comprises a circuit connected across the inductor. An impedance of the circuit matches an impedance of the inductor.

[0020] In another feature, the estimation module estimates the first current through the inductor by using a model of the inductor.

[0021] In other features, the high pass filter module, the estimation module, the low pass filter module, and the combining module are implemented using at least one of passive and active analog components including resistances, capacitances, and operational amplifiers.

[0022] In other features, the high pass filter module, the estimation module, the low pass filter module, and the combining module are implemented using digital logic including adders, multipliers, and a delay stage.

[0023] In other features, the high pass filter module, the estimation module, the low pass filter module, and the combining module are implemented using firmware including instructions executable by a digital signal processor (DSP) controlling the converter.

[0024] In still other features, a method comprises generating an average output voltage by averaging an output voltage of a power supply. The method further comprises filtering using a high pass filter a difference between the average output voltage and an average switching voltage used to control switches in an output stage of the power supply. The method further comprises estimating a first filtered current through an inductor in the output stage based on an output of the high pass filter and estimating a second current through the inductor by sensing voltage across the inductor. The method further comprises filtering the second current using a low pass filter and combining the first filtered current and the second filtered current to generate an estimated current through the inductor.

[0025] In other features, the method further comprises configuring the high pass filter to have a first corner frequency and configuring the low pass filter to have a low pass filter having a second corner frequency, where the first corner frequency is equal to the second corner frequency.

[0026] In other features, the method further comprises configuring the high pass filter to have a first gain and configuring the low pass filter to have a low pass filter having a second gain, where the first gain is equal to the second gain.

[0027] In other features, the method further comprises configuring the high pass filter to have a first pole and configuring the low pass filter to have a low pass filter having a second pole, where the first pole is equal to the second pole.

[0028] In another feature, the method further comprises sensing the voltage across the inductor by using a circuit connected across the inductor, where an impedance of the circuit matches an impedance of the inductor.

[0029] In other features, the method further comprises generating a model of the inductor and estimating the first current through the inductor by using the model.

[0030] Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

[0043] The following description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure.

[0044] As used herein, the term module may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); an electronic circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor (shared, dedicated, or group) that executes code; other suitable components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip. The term module may include memory (shared, dedicated, or group) that stores code executed by the processor.

[0045] The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, and/or objects. The term shared, as used above, means that some or all code from multiple modules may be executed using a single (shared) processor. In addition, some or all code from multiple modules may be stored by a single (shared) memory. The term group, as used above, means that some or all code from a single module may be executed using a group of processors. In addition, some or all code from a single module may be stored using a group of memories.

[0046] The apparatuses and methods described herein may be implemented by one or more computer programs executed by one or more processors. The computer programs include processor-executable instructions that are stored on a non-transitory tangible computer readable medium. The computer programs may also include stored data. Non-limiting examples of the non-transitory tangible computer readable medium are nonvolatile memory, magnetic storage, and optical storage.

[0047] Referring now to FIGS. 3A and 3B, a system 100 uses a mathematical model to estimate an average inductor current. A detailed description of the mathematical model can be found in U.S. patent application Ser. No. 12/622,478 filed Nov. 20, 2009, which is incorporated herein by reference in its entirety. A brief description of the system 100 follows.

[0048] In FIG. 3A, the system 100 comprises the PWM controller 12, the switches 14 and 16, the inductor L, and the capacitor C_out. Additionally, the system 100 comprises an ADC/Averaging module 102, an estimation module 104, an ADC 106, and a divider 108. The ADC/Averaging module 102 digitizes an output voltage across the capacitor C_out and generates average values of the output voltage (V_outavg). The ADC 106 digitizes an input voltage V_dd. The divider 108 divides an average switching voltage V_avgsw by the input voltage V_dd. The average switching voltage V_avgsw is the average voltage of the signal used to control duty cycle of the switches 14 and 16. The PWM controller 12 determines a duty cycle of the pulses that drive the switches 14 and 16 based on the ratio V_avgsw/V_dd.

[0049] The average switching voltage V_avgsw and the average values of the output voltage are input to the estimation module 104. The estimation module 104 combines the average switching voltage V_avgsw and the average values of the output voltage to estimate an average inductor current. The estimation module 104 uses the mathematical model summarized below to estimate the average inductor current i_est.

[0050] In FIG. 3B, the estimation module 104 is shown in detail. The estimation module comprises a subtractor 150, a multiplier 152, an adder 154, a delay stage 156, and a multiplier 158. The subtractor 150 generates a difference between the average switching voltage V_avgsw and the average values of the output voltage. The multiplier 152 multiples the output of the subtractor 150. The adder 154 adds the output of the multiplier 152 and an output of the multiplier 158. The delay stage 156 delays an output of the adder 154. The multiplier 158 multiplies the output of the delay stage 156. The output of the delay stage 156 is the estimated inductor current I_est.

[0051] Mathematically, an instantaneous inductor current is given by the following equation:

[0052] $L\frac{di\left(t\right)}{dt}=\mathrm{Vsw}\left(t\right)-R*i\left(t\right)-\mathrm{vout}\left(t\right)$

[0053] When averaged over a PWM cycle, the equation reduces to:

[0054] $L\frac{1}{T}\frac{d}{dt}{\int }_0^{T}i\left(t\right)dt=\frac{1}{T}{\int }_0^T\mathrm{Vsw}\left(t\right)dt-R\frac{1}{T}{\int }_0^{T}i\left(t\right)dt-\frac{1}{T}{\int }_0^T\mathrm{vout}\left(t\right)dt$

[0055] Using the definition of averaging over one period, the equation simplifies to:

[0056] $L\frac{d\mathrm{avgi}\left(t\right)}{dt}=\mathrm{Vavgsw}\left(t\right)-R*\mathrm{avgi}\left(t\right)-\mathrm{vout}\left(t\right)$
where V_avgsw is the average switching voltage, avgi is the average inductor current, vout is the measured or estimated output voltage, L is the inductance of the inductor L, and R is the DC resistance of the power stage.

[0057] These differential equations may be simplified to a discrete time equation of the form:
avgi(n+1)=A_est*avgi(n)+B_est*(V_avgsw(n)−vest(n)),
where A_est and B_est are multipliers, n denotes a current sampling time, and (n+1) denotes a subsequent sampling time. Typically, since the time constant of the inductor L (L/R) is much larger than a sampling time T_s, A_est and B_est can be approximated as B_est=T_s/L, and A_est=1−R*T_s/L.

[0058] The above method estimates the average inductor current using the mathematical model of the inductor and the DC resistance of the power stage. This method does not have noise problems since this method uses the mathematical model instead of relying on noise sensitive measurements. This method, however, estimates the average inductor current based on the duty cycle (since V_avgsw is proportional to the duty cycle) and the output voltage. Accordingly, this method has problems with DC offset due to errors in the duty cycle.

[0059] The present disclosure relates to generating a composite estimate of inductor current using a combination of two methods: the method that uses impedance matched circuit to sense the inductor current, and the method that uses the mathematical model to estimate the inductor current. The DC offset problem associated with the method that uses the mathematical model is eliminated by filtering the input to the estimation module with a high-pass filter. The high-frequency noise problem associated with the method that uses the impedance matched circuit is eliminated by filtering the sensed inductor current with a low-pass filter. The outputs of the estimation module and the low-pass filter are combined to generate a composite estimate inductor current that is free of the DC offset and the high-frequency noise.

[0060] Thus, the present disclosure provides a method for sensing the inductor current without noise problems and with no impact on the overall efficiency of the converter. The method of generating the composite estimate of inductor current disclosed herein blends the advantages of no loss and low cost of the impedance matching method with the noise-free current estimate generated by the mathematical modeling method. Accordingly, the method disclosed herein produces a high bandwidth, low noise, and accurate estimate of the inductor current at low cost. The method disclosed herein can be implemented using analog hardware, digital hardware, firmware, or a combination thereof.

[0061] Referring now to FIG. 4, a functional block diagram of a system 200 for sensing the inductor current according to the present disclosure is shown. The system 200 comprises a high pass filter module 202, an estimation module 204, a low pass filter module 206, and a combining module 208. The high pass filter module 202 includes a high pass filter. The low pass filter module 206 includes a low pass filter. The high pass filter and the low pass filter have the same corner frequency (i.e., 3 dB cutoff frequency) and the same gain.

[0062] The corner frequency and the gain of the high pass filter and the low pass filter can be selected by a user. For example, the user may communicate with the controller using power management bus (PMbus) commands or graphical user interface (GUI) commands to select the corner frequency and the gain.

[0063] The high pass filter module 202 receives the average output voltage of the converter (V_outavg) and the average switching voltage V_avgsw, which is available from the controller that controls the converter. The average switching voltage V_avgsw is proportional to the duty cycle. Accordingly, the average switching voltage V_avgsw can also be referred to as V_duty (i.e., the duty cycle voltage). The high pass filter module 202 filters V_avgsw and V_outavg. The output of the high pass filter module 202, V_indhp, is free of the DC offset. V_indhp is input to the estimation module 204. The estimation module 204 uses the mathematical model described above to estimate the inductor current and generates the estimated inductor current i_esthp that is free of DC offset.

[0064] The low pass filter module 206 filters the inductor current i_est sensed using the impedance matching method described above (see description of FIG. 2). The low pass filter module 206 removes the high-frequency noise from the sensed inductor current i_est and outputs i_estlp, which is free of the high-frequency noise. The combining module 208 combines the output of the estimation module 204, i_esthp, and the output of the low pass filter module 206, i_estlp, to generate a blended inductor current i_blend that is free of the DC offset and the high-frequency noise.

[0065] Referring now to FIG. 5, a system 200-1 is shown. The system 200-1 comprises the converter 30 shown in FIG. 2, the system 100 shown in FIGS. 3A and 3B, and the system 200 shown in FIG. 4. The operation of the converter 30, the system 100, and the system 200 is described above and is not repeated.

[0066] Referring now to FIGS. 6A-8D, different implementations (e.g., analog, digital, and firmware implementations) of each module of the system 200 are shown. In FIGS. 6A-6D, different implementations of the high pass filter module 202 are shown. In FIG. 7, a digital implementation of the estimation module 204 is shown. In FIGS. 8A-8D, different implementations of the low pass filter module 206 are shown.

[0067] In FIG. 6A, a discrete high pass filter (e.g., a first order high pass digital filter) is shown, where a is the pole of the high pass filter in Z domain. In FIG. 6B, a digital implementation of the discrete high pass filter comprising adders, a delay stage, and a gain stage is shown. Adders 220, 222, and 224 represent summing junctions. A delay stage 226 adds a delay denoted by 1/z. A gain stage 228 is implemented using a multiplier, where blend (i.e., gain)=1/(1−α).

[0068] The high pass filter module 202 can be implemented by firmware in a digital signal processor (DSP) based power controller. The firmware may include code for the following equations:
V_ind=V_duty(n)−V_out(n), and
V_indhp=V_ind(n)+V_indhp*(1−1/blend)−V_ind(n−1),
where n denotes a current sampling time, and (n−1) denotes a previous sampling time. Substituting blend=1/(1−α), the equation for V_indhp becomes
V_indhp=V_ind(n)+V_indhp*α−V_ind(n−1).

[0069] In FIGS. 6C and 6D, analog implementations of the high pass filter are shown. In FIG. 6C, an analog high pass filter implemented using passive components (an RC circuit) is shown. The corner frequency of the high pass filter is given by f_c=½πRC. In FIG. 6D, an analog high pass filter implemented using active components is shown. The corner frequency of the high pass filter is given by f_c=½πR₁C. The high-frequency signals are inverted and amplified by R₂/R₁. Accordingly, the gain of the high pass filter is (−R₂/R₁).

[0070] In FIG. 7, the estimation module 204 comprises a multiplier 250, an adder 252, a delay stage 254, and a multiplier 256. The input to the estimation module is the output V_indhp of the high pass filter module 202, which is free of the DC offset. The multiplier 250 multiples V_indhp. The adder 252 adds the output of the multiplier 250 and an output of the multiplier 256. The delay stage 254 delays an output of the adder 252. The multiplier 256 multiplies the output of the delay stage 254. The output of the delay stage 254 is the estimated inductor current i_esthp, which is free of the DC offset. Typically, since the time constant of the inductor L (L/R) is much larger than the sampling time T_s, A_est and B_est can be approximated as B_est=T_s/L, and A_est=1−R_dc*T_s/L.

[0071] The estimation module 204 can be implemented by firmware in a DSP based power controller. The firmware may include code for the following equation:
i_est(n+1)=A_est*i_est(n)+B_est*V_indhp(n),
where n denotes a current sampling time, and (n+1) denotes a subsequent sampling time.

[0072] In FIG. 8A, a discrete low pass filter (e.g., a first order high pass digital filter) is shown, where β is the pole of the low pass filter in Z domain. In FIG. 8B, a digital implementation of the discrete low pass filter comprising adders, a delay stage, and a gain stage is shown. Adders 270 and 272 represent summing junctions. A delay stage 274 adds a delay denoted by 1/z. A gain stage 276 is implemented using a multiplier, where β=1/(1−blend).

[0073] The low pass filter module 206 can be implemented by firmware in a DSP based power controller. The firmware may include code for the following equation:
i_estlp(n)=blend*i_est(n−1)+(1−1/blend)*i_estlp(n−1).
where n denotes a current sampling time, and (n−1) denotes a previous sampling time. Alternatively,
i_estlp(n)=β*i_est(n−1)+(1−1/β)*i_estlp(n−1).

[0074] In FIGS. 8C and 8D, analog implementations of the low pass filter are shown. In FIG. 6C, an analog low pass filter implemented using passive components (an RC circuit) is shown. The corner frequency of the low pass filter is given by f_c=½πRC. In FIG. 8D, an analog low pass filter implemented using active components is shown. The corner frequency of the low pass filter is given by f_c=½πR₂C. The gain of the low pass filter is (−R₂/R₁).

[0075] The combining module 208 combines the output of the estimation module 204, i_esthp, and the output of the low pass filter module 206, i_estlp, to generate the composite estimate of inductor current, i_blend, which is given by the following equation:
i_blend=i_esthp+i_estlp.
The pole of the low pass filter module 206 is the same as the pole of the high pass filter module 202. Accordingly, the composite estimate of inductor current i_blend has no DC offset and high frequency noise and has high bandwidth, high precision, and low noise.

[0076] Referring now to FIG. 9A, an analog implementation of the system 200 is shown. In FIG. 9A, the subscript ‘h’ in a component symbol indicates that the component is part of a high pass filter, and the subscript ‘l’ in a component symbol indicates that the component is part of a low pass filter. V_e represents an estimated current input to a high pass filter. V_m represents a measured current input to a low pass filter. Output i_blend a blend of the estimated current V_e and the measured current V_m and is given by the following equation:
i_blend=(R/R1)*(R_fh*C_h*s)/(R_fh*C_h*s+1)+(R/R2)*(R_l/R_l*C_l*s+1),
is a Laplace transform variable. Values of resistances and capacitances shown in FIG. 9a are selected so that the above equation is satisfied.

[0077] Referring now to FIG. 9B, a simulated representation of the analog implantation is shown. K1=R/R1, and K2=R/R2.

[0078] Referring now to FIG. 10, a method 300 for estimating inductor current according to the present disclosure is shown. Control begins at 302. At 304, control digitizes and averages the output voltage of the converter. At 306, control filters the difference between the average output voltage and the average switching voltage using high pass filter and removes DC offset. At 308, control generates a first estimated inductor current using a mathematical model of the inductor and the DC resistance of the output stage of the converter.

[0079] At 310, control generates a second estimated inductor current from the inductor voltage sensed using an impedance-matched RC circuit connected across the inductor. At 312, control filters the second estimated inductor current using a low pass filter and removes high-frequency noise. At 314, control combines the first estimated inductor current and the filtered second estimated inductor current to produce the composite estimate of inductor current, which has no DC offset and high-frequency noise. Control returns to 304.

[0080] The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification, and the following claims.