US 8,040,703 B2Grant

Power factor correction controller with feedback reduction

Issue Date:2011-10-18

•22 Claims

•15 Drawing Sheets

Abstract

A power control system includes a feedback loop having a power factor correction (PFC) and output voltage controller and a switching power converter. The switching power converter includes an inductor to supply charge to an output capacitor and a switch to control inductor current ramp-up times. The PFC and output voltage controller provides a control signal to the switch to control PFC and regulate output voltage of the switching power converter. During a single period of the control signal, the PFC and output voltage controller obtains the line input voltage and output voltage of the switching power converter using a single feedback signal received from the switching power converter.

Metadata

Assignee

Cirrus Logic, Inc.

Inventor

John L. Melanson

Application Information

Application Number:US 11/967,271

Filing Date:2007-12-31

Priority Date:2007-05-02

Art Unit:2838

Classifications

IPC:

H02M1/42G05F1/70

Patent Drawings (15 sheets)

Description

Cross-Reference to Related Application

[0001] This application claims the benefit under 35 U.S.C. §119(e) and 37 C.F.R. §1.78 of U.S. Provisional Application No. 60/915,547, filed May 2, 2007, and entitled “Power Factor Correction (PFC) Controller Apparatuses and Methods,” and is incorporated by reference in its entirety.

Background of the Invention

[0002] 1. Field of the Invention

[0003] The present invention relates in general to the field of signal processing, and more specifically, to power factor correction and a power factor correction controller with feedback reduction.

[0004] 2. Description of the Related Art

[0005] Power control systems provide power factor corrected and regulated output voltages to many applications that utilize a regulated output voltage. FIG. 1 depicts a power control system 100, which includes a switching power converter 102. The switching power converter 102 performs power factor correction and provides constant voltage power to load 112. Voltage source 101 supplies an alternating current (AC) input voltage V_in(t) to a full, diode bridge rectifier 103. The voltage source 101 is, for example, a public utility, and the AC voltage V_in(t) is, for example, a 60 Hz/110 V line voltage or a 50 Hz/220 V line voltage in Europe. The rectifier 103 rectifies the input voltage V_in(t) and supplies a rectified, time-varying, line input voltage V_x(t) to the switching power converter.

[0006] The switch 108 of switching power converter 102 regulates the transfer of energy from the line input voltage V_x(t), through inductor 110, to capacitor 106. The inductor current i_Lramps ‘up’ when the switch 108 conducts, i.e. is “ON”. The inductor current i_Lramps down when switch 108 is nonconductive, i.e. is “OFF”, and supplies current i_Lto recharge capacitor 106. The time period during which inductor current i_Lramps down is commonly referred to as the “inductor flyback time”. In at least one embodiment, the switching power converter 102 operates in discontinuous current mode, i.e. the inductor current i_Lramp up time plus the inductor flyback time is less than the period of switch 108. Capacitor 106 supplies stored energy to load 112 while the switch 108 conducts. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage V_c(t), as established by a power factor correction (PFC) and output voltage controller 114 (as discussed in more detail below). The output voltage V_c(t) remains substantially constant during constant load conditions. However, as load conditions change, the output voltage V_c(t) changes. The PFC and output voltage controller 114 responds to the changes in V_c(t) and adjusts the control signal CS₀to maintain a substantially constant output voltage as quickly as possible. The output voltage controller 114 includes a small capacitor 115 to filter any high frequency signals from the line input voltage V_x(t).

[0007] The power control system 100 also includes a PFC and output voltage controller 114 to control the switch 108 and, thus control power factor correction and regulate output power of the switching power converter 102. The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, the PFC and output voltage controller 114 attempts to control the inductor current i_Lso that the average inductor current i_Lis linearly and directly related to the line input voltage V_x(t). Prodić, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of PFC and output voltage controller 114. The PFC and output voltage controller 114 supplies a pulse width modified (PWM) control signal CS₀to control the conductivity of switch 108. In at least one embodiment, switch 108 is a field effect transistor (FET), and control signal CS₀is the gate voltage of switch 108. The values of the pulse width and duty cycle of control signal CS₀depend on two feedback signals, namely, the line input voltage V_x(t) and the capacitor voltage/output voltage V_c(t).

[0008] Switching power converter 114 receives two feedback signals, the line input voltage V_x(t) and the output voltage V_c(t), via a wide bandwidth current loop 116 and a slower voltage loop 118. The current loop 116 operates at a frequency f_cthat is sufficient to allow the PFC and output controller 114 to respond to changes in the line input voltage V_x(t) and cause the inductor current i_Lto track the line input voltage to provide power factor correction. The current loop frequency is generally set to a value between 20 kHz and 150 kHz. The voltage loop 118 operates at a much slower frequency f_v, typically 10-20 Hz. The capacitor voltage V_c(t) includes a ripple component having a frequency equal to twice the frequency of input voltage V_in(t), e.g. 120 Hz. Thus, by operating at 10-20 Hz, the voltage loop 118 functions as a low pass filter to filter the ripple component.

[0009] PFC and output voltage controller 114 is often implemented as an integrated circuit (IC). Thus, the PFC and output voltage controller 114 includes two respective pins to connect to the current feedback loop 118. Pins can be relatively expensive components of the IC. Additionally, high voltage components, such as high voltage resistors, in the voltage loop 118 also increase the cost of PFC and output voltage controller 114.

Summary of the Invention

[0010] In one embodiment of the present invention, a power factor correction (PFC) controller is configured to control power factor correction and regulate output voltage of a switching power converter. The switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor. The PFC controller includes an input to receive a feedback signal from the switching power converter. The PFC controller is configured to:

- [0011] (a) determine at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;
- [0012] (b) provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;
- [0013] (c1) wherein, if the line input voltage is determined in (a), the PFC controller is further configured to determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval; and
- [0014] (c2) wherein, if the output voltage of the switching power converter is determined in (a), the PFC controller is further configured to determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

[0015] In another embodiment of the present invention, a power factor correction (PFC) controller is configured to control power factor correction and regulate output voltage of a switching power converter. The switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor. The PFC controller includes an input to receive a feedback signal from the switching power converter. The PFC controller is configured to determine a line input voltage and provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive. the PFC controller is further configured to determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval.

[0016] In another embodiment of the present invention, a power factor correction (PFC) controller is configured to control power factor correction and regulate output voltage of a switching power converter. The switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor. The PFC controller includes an input to receive a feedback signal from the switching power converter. The PFC controller is configured to determine an output voltage of the switching power converter from the feedback signal and provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive. The PFC controller is further configured to determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

[0017] In a further embodiment of the present invention, a method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, includes receiving a feedback signal from the switching power converter. The method further includes:

- [0018] (a) determining at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;
- [0019] (b) providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;
- [0020] (c1) wherein, if the line input voltage is determined in (a), determining the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval; and
- [0021] (c2) wherein, if the output voltage of the switching power converter is determined in (a), determining the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

[0022] In a further embodiment of the present invention, a method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, includes receiving a feedback signal from the switching power converter and determining a line input voltage. The method further includes providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive. The method further includes determining an output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval.

[0023] In another embodiment of the present invention, a method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, includes receiving a feedback signal from the switching power converter and determining an output voltage of the switching power converter from the feedback signal. The method further includes providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive. The method also includes determining a line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

Brief Description of the Drawings

[0024] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

[0025] FIG. 1 (labeled prior art) depicts a power control system with power factor correction and output voltage regulation.

[0026] FIG. 1A depicts a power control system with a single feedback signal to determine a line input voltage and an output voltage.

[0027] FIG. 2 depicts an embodiment of the power control system of FIG. 1A.

[0028] FIG. 3 depicts a power factor correction and output voltage regulation process.

[0029] FIGS. 4 and 5 depict sensor/converters.

[0030] FIG. 6 depicts a time domain graph of a voltage feedback signal, an inductor current i_L, and corresponding states of a switching power converter switch.

[0031] FIG. 7 depicts an inductor flyback time interval determination module.

[0032] FIG. 8 depicts a PFC and output voltage controller.

[0033] FIG. 9 depicts an embodiment of the power control system of FIG. 1A.

[0034] FIG. 10 depicts a graph of a feedback signal and corresponding ideal and actual gate voltages and actual currents of a switching power converter switch.

[0035] FIG. 11 depicts an inductor flyback time interval determination module.

[0036] FIG. 12 depicts an embodiment of the power control system of FIG. 1A.

[0037] FIG. 13 depicts an inductor flyback time interval determination module.

[0038] FIG. 14 depicts an embodiment of the power control system of FIG. 1A that includes a redundancy and reliability module.

Detailed Description

[0039] A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The switching power converter includes an inductor to supply charge to an output capacitor and a switch to control inductor current ramp-up times and energy transfer to the output capacitor. In at least one embodiment, the PFC and output voltage controller provides a control signal to the switch to control power factor correction and regulate output voltage of the switching power converter. In at least one embodiment, during a single period of the control signal, the PFC and output voltage controller determines the line input voltage and output voltage of the switching power converter using a single feedback signal received from the switching power converter. In at least one embodiment, the PFC and output voltage controller determines an inductor flyback time from the feedback signal. The PFC and output voltage controller determines either the line input voltage or the output voltage, whichever was not determined from the feedback signal, using the determined voltage, the inductor flyback time, and a conducting (“ON”) time of the switch as controlled by the control signal. Using the line input voltage and the output voltage, the PFC and output voltage controller generates the control signal to provide power factor correction and output voltage regulation.

[0040] In at least one embodiment, the overall number of input terminals of the PFC and output voltage controller is reduced or an additional pin is available for other uses. For example, by using only one feedback signal to obtain both the line input voltage and the output voltage of the switching power converter, the number of pins of an integrated circuit (IC) switching power converter can be reduced by one. Additionally, in at least one embodiment, by reducing the number of feedback signals received by the PFC and output voltage controller, in at least one embodiment, the number of peripheral components, such as voltage and/or current step-down circuits, can be reduced. Reducing the number of pins and associated peripheral components can lower costs. In at least one embodiment, rather than reducing the number of pins, the PFC and output voltage controller receives one or more additional feedback signals that can be used for reliability and redundancy purposes.

[0041] FIG. 1A depicts one embodiment of a power control system 150 with one feedback signal V_S(t). The power control system 150 includes a switching power converter 154 to provide a power factor corrected and regulated output voltage V_c(t) to load 112. A PFC and output voltage controller 156 provides a control signal CS₁to the switching power converter 154 to control switch 108 and, thus, control power factor correction and voltage regulation. To determine the control signal CS₁, the PFC and output voltage controller 156 receives feedback signal V_S(t) from the switching power converter 154. The PFC and output voltage controller 154 can determine control signal CS₁using the single feedback signal V_S(t). Accordingly, in at least one embodiment, the PFC and output voltage controller can be implemented using fewer input terminals, such as integrated circuit pins, and fewer peripheral components. The power control system 150 can be implemented using digital and/or analog hardware or a combination of hardware and software. In at least one embodiment, PFC and output voltage controller 156 is a programmable PFC and output voltage controller as illustratively described in U.S. Patent Application entitled “Programmable Power Control System”, inventor John L. Melanson, assignee Cirrus Logic, Inc., U.S. patent application Ser. No. 11/967,275, now U.S. Pat. No. 7,969,125, which is incorporated herein by reference in its entirety.

[0042] FIG. 2 depicts power control system 200 having a PFC and output voltage controller 202 that, during operation, includes a feedback signal V_S(t) from SWITCH NODE from which the line input voltage V_x(t) and the output voltage V_c(t) can be determined. The power control system 200 and PFC and output voltage controller 202 represent one embodiment of respective power control system 150 and PFC and output voltage controller 156. The switching power converter 201 provides a power factor corrected and regulated output voltage V_c(t) to load 112. The output voltage V_c(t) across output capacitor 106 equals the load voltage V_L(t). The power control system 200 includes a feedback path 203 to provide the feedback signal V_S(t) from the SWITCH NODE to PFC and output voltage controller 202. In at least one embodiment, the feedback signal V_S(t) provided to PFC and output voltage controller 202 is a voltage V_S(t) or a current, both sensed at the SWITCH NODE. The feedback path 203 includes the SWITCH NODE, the PFC and output voltage controller 202, and switch 108. The PFC and output voltage controller 202 determines the line input voltage V_x(t) and the output voltage V_c(t) from the single feedback signal V_S(t). The PFC and output voltage controller 202 uses the determined line input voltage V_x(t) and the output voltage V_c(t) of switching power converter 201 to generate the control signal CS₁.

[0043] FIG. 3 depicts an exemplary PFC and output voltage regulation process 300. In at least one embodiment, PFC and output voltage controller 202 operates in accordance with PFC and output voltage regulation process 300 to determine the line input voltage V_x(t) and the output voltage V_c(t) of switching power converter 102, to control power factor correction, and to regulate the output voltage V_c(t) of switching power converter 102. In operation 302, the PFC and output voltage controller 202 receives feedback signal V_S(t) from switching power converter 201. In at least one embodiment, the feedback signal V_S(t) is a signal from which the PFC and output voltage controller 202 can obtain the line input voltage V_x(t) or the output voltage V_c(t) and determine an inductor current flyback time interval T2. In at least one embodiment, the feedback signal V_S(t), as depicted in FIG. 2, is the voltage V_S(t) at the SWITCH NODE of switching power converter 201. The PFC and output voltage regulation process 300 can be implemented in hardware or in software and executed by a processor of PFC and output voltage controller 202.

[0044] In at least one embodiment, the maximum, nominal voltage of feedback signal V_S(t) depends upon the voltage demand of load 112. For example, if load 112 is a 12 V motor, the feedback signal V_S(t) will have a maximum nominal value of 12 V; if load 112 is a light emitting diode based fixture, the feedback signal V_S(t) may have a nominal value of 400 V, and so on. The exact maximum, nominal voltage of feedback signal V_S(t) at SWITCH NODE typically varies slightly from the output voltage V_c(t) due to system impedances, such as a voltage drop across diode 111.

[0045] In at least one embodiment of the PFC and output voltage controller 202, analog circuitry is used to generate the control signal CS₁, and the feedback signal V_S(t) can be fed directly into the analog circuitry. In at least one embodiment, PFC and output voltage controller 202 is implemented as an integrated circuit (IC), and input signals to PFC and output voltage controller 202 are voltage or current limited to prevent damaging PFC and output voltage controller 202. Thus, in at least one embodiment, power control system 200 includes a sensor/converter 206 to convert the feedback signal V_S(t) to a maximum value, such as +1 V, that can be received directly by an integrated circuit implemented PFC and output voltage controller 202. The sensor/converter 206 can be implemented separately from PFC and output voltage controller 202 or as a wholly or partially integrated component of PFC and output voltage controller 202.

[0046] FIGS. 4 and 5 depict respective, exemplary sensor/converters. Sensor/converter 402 represents one embodiment of sensor/converter 206. Sensor/converter 402 represents a voltage divider/analog-to-digital system. Sensor/converter 402 includes a resistive voltage divider R0/R1 to step down feedback signal V_S(t) to levels useable by PFC and output voltage controller 202. The resistance values of R0 and R1 depend upon the voltage coupled across R0 and R1 and the input voltage and current levels to be received by PFC and output voltage controller 202. In one embodiment, resistor R0 is 399 kohms, and resistor R1 is 1 kohm. Sensor/converter circuit 402 also includes an analog-to-digital (A/D) converter 404 to convert the analog output voltage across resistor R1 into a representative digital feedback signal V(n) useable by digital system 406, and “n” indicates a particular sample. In at least one embodiment, digital system 406 represents processing, driver, and other functions of PFC and output voltage controller 202.

[0047] FIG. 5 depicts a current-source and A/D sensor/converter 502. Sensor/converter 502 represents another embodiment of sensor/converter 206. Sensor/converter 502 includes a current-source 504 that provides a current-output signal i(t) to A/D converter 404. The value of current-output signal i(t) corresponds to the feedback signal V_S(t). Sensor/converter 502 also includes A/D 404 to convert the output signal i(t) into a representative digital feedback signal V(n) useable by digital system 406.

[0048] FIG. 6 depicts time domain graphs 600 of (i) the voltage feedback signal V_S(t) from the SWITCH NODE (graph 602), (ii) inductor current i_L(graph 604), and (iii) corresponding states of switch 108 (graph 606). Referring to FIGS. 2 and 6, the state of switch 108 is controlled by control signal CS₁. Control signal CS₁has a frequency equal to 1/TT_x, where TT_xis the period of control signal CS₁for the x^thframe, and “x” is an integer marker. The frequency f_CS1of control signal CS₁can be controlled by PFC and output voltage controller 202. In at least one embodiment, PFC and output voltage controller 202 varies the frequency f_CS1to provide a regulated output voltage V_c(t) and in accordance with a predetermined spread spectrum strategy to, for example, reduce electromagnetic interference emissions. The frequency of control signal CS₁is preferably between 20 kHz and 150 kHz, which respectively avoids audio frequencies and inefficient switching frequencies.

[0049] During an inductor current i_Lramp-up time interval T1, i.e. when switch 108 is “ON” (i.e. conducts), the inductor current i_Lramps up and the voltage V_S(t) at the SWITCH NODE decreases to approximately 0. The voltage V_S(t) decreases to “approximately” 0 because small, non-ideal voltage drops can occur, such as a voltage drop across switch 108 when switch 108 is conducting or a voltage drop across diode 111, so that the voltage of feedback signal V_S(t) differs from, for example, line input voltage V_x(t) or output voltage V_c(t) by such non-ideal voltage drops. However, unless otherwise indicated, for purposes of this application determining or obtaining a line input voltage V_x(t) and/or an output voltage V_S(t) of switching power converter 201 includes determining or obtaining an approximate or scaled line input voltage and/or an approximate or scaled output voltage of switching power converter 201.

[0050] During inductor flyback time interval T2 when switch 108 is “OFF” (i.e. nonconductive), diode 111 conducts, the inductor current i_Lramps down to zero (0) amps, and the voltage V_S(t) increases to V_c(t). After the inductor current i_Lramps down to zero (0) amps, diode 111 stops conducting, the voltage drop across inductor 110 is approximately zero, and the voltage of feedback signal V_S(t) equals V_x(t). When the inductor current i_Lreaches zero, parasitic impedances, such as the parasitic capacitance across inductor 110, cause a decaying ripple 608 at the SWITCH NODE.

[0051] Referring to FIGS. 2, 3, and 6, PFC and output voltage controller 202 processes the feedback signal V_S(t) in accordance with PFC and output voltage regulation process 300. Operation 304 determines the line input voltage V_x(t) or the output voltage V_c(t) from the feedback signal V_S(t). Whether operation 304 determines the line input voltage V_x(t) or the output voltage V_c(t) is a design choice. Generally, the output voltage V_c(t) can be obtained for all power output settings of switching power converter 201, i.e. for minimum and maximum pulse widths of control signal CS₁. However, the ripple 608 can cause difficulties in determining the line input voltage V_x(t) during maximum output power settings, i.e. maximum pulse width of control signal CS₁, because the ripple 608 may not subside prior to the next cycle of control signal CS₁. If the line input voltage V_x(t) is determined by operation 304, the PFC and output voltage controller 202 is configured to determine the output voltage V_c(t) in operation 308. If the output voltage V_c(t) is determined by operation 304, the PFC and output voltage controller 202 is configured to determine the line input voltage in operation 308. The switch 108 ON time is set by PFC and output voltage controller 202 during each period of control signal CS₁, and, thus, the inductor current i_Lramp-up time interval T1 is known.

[0052] The PFC and output voltage controller 202 determines the output voltage V_c(t) from the feedback signal V_S(t) by sensing the feedback signal V_S(t) during inductor flyback time interval T2. In at least one embodiment, the duration of inductor flyback time interval T2 is unknown. Accordingly, switching power converter 201 waits a sufficient amount of time after the end of time interval T1 to allow any transient signals to dissipate and then determines the output voltage V_c(t) from the feedback signal V_S(t). As previously described, the feedback signal V_S(t) may represent a scaled version of the output voltage V_c(t). However, in at least one embodiment, when using the output voltage V(t) to determine the line input voltage V_x(t) in operation 308, the scaling can be accounted for by switching power converter 201. Accordingly, unless otherwise indicated, determining the output voltage V_c(t) includes determining a scaled or approximate version of the output voltage V_c(t).

[0053] The PFC and output voltage controller 202 determines the line input voltage V_x(t) from the feedback signal V_S(t) by sensing the feedback signal V_S(t) after the inductor flyback time interval T2. Accordingly, in at least one embodiment, when determining the line input voltage V_x(t) from the feedback signal V_S(t) (as subsequently described), operation 306 determines the inductor flyback time interval T2 prior to operation 304. To determine the line input voltage V_x(t) directly from the feedback signal V_S(t), the feedback signal V_S(t) can be sensed during a period of control signal CS₁any time after inductor flyback time interval T2 and prior to the beginning of the time interval T1 for the next period of control signal CS₁to determine line input voltage V_x(t). In at least one embodiment, the feedback signal V_S(t) is sensed after the ripple signal 608 dissipates so as to obtain a more accurate value of line input voltage V_x(t) and sufficiently prior the beginning of the next period of control signal CS₁to allow the switching power converter 201 to perform operations 308, 310, and 312. In at least one embodiment, the switching power converter 201 determines the line input voltage V_x(t) immediately after the inductor flyback time interval T2 by averaging the feedback signal V_S(t). As with the output voltage V_c(t), in at least one embodiment, when using the input voltage V_x(t) to determine the output voltage V_c(t), the scaling can be accounted for by switching power converter 201. Accordingly, unless otherwise indicated, determining the line input voltage V_x(t) includes determining a scaled or approximate version of the line input voltage V_x(t).

[0054] Operation 306 determines the inductor flyback time interval T2. FIG. 7 depicts one embodiment of an inductor flyback time interval determination module (referred to herein as a “flyback time module”) 702. The inductor flyback time interval T2 can be determined by the flyback time module 702 by, for example, sensing the feedback signal V_S(t) at the beginning of time interval T2, detecting the transition at time t_xof voltage V_S(t) to V_x(t), and determining the time between the end of the inductor current i_Lramp-up time interval T1 and the transition of voltage V_S(t) to V_x(t) at time t_x, where “x” is a marker representing a particular period of control signal CS₁. Flyback time module 702 can be implemented separately from PFC and output voltage controller 202 or as a wholly or partially integrated component of PFC and output voltage controller 202.

[0055] Flyback time module 702 includes a comparator 704 to compare the feedback signal V_S(t) with a predetermined reference voltage V_REF0and provide an output signal V_SENSE_—₀. The output signal V_SENSE_—₀transitions from one logical state to another (in this embodiment from HIGH to LOW) when voltage V_S(t) decreases below the reference voltage V_REF0. Thus, the comparison of feedback signal V_S(t) and V_REF0allows the flyback time module 702 to sense a transition of the feedback signal V_S(t) from the output voltage V_c(t) level towards the line input voltage V_x(t) level. The reference voltage V_REF0is set between V_c(t) and V_x(t). In at least one embodiment, the reference voltage V_REF0is set below any expected transients in the feedback signal V_S(t) during inductor flyback time interval T2 and high enough so that the value of comparator output signal V_SENSE_—₀transitions quickly at the end of inductor flyback time interval T2. In at least one embodiment, the comparator 704 is implemented separately from the integrated PFC and output voltage controller 202. In another embodiment, comparator 704 is integrated with PFC and output voltage controller 202 (i.e. “on-chip”), and sensor/converter 206 modifies feedback signal V_S(t) into a level useable by PFC and output voltage controller 202. In this embodiment, the reference voltage V_REF0is also scaled to the same degree as feedback signal V_S(t).

[0056] The transition of the comparator output signal V_SENSE_—₀of comparator 704 from logical HIGH to logical LOW indicates an end of the inductor flyback time interval T2. The flyback time module 702 includes a counter/processor 706 that begins counting at the beginning of inductor flyback time interval T2. The beginning of inductor flyback time interval T2 is known because the beginning coincides with the end of time interval T1. The PFC and output voltage controller 202 determines the end of time interval T1, which occurs when control signal CS₁causes switch 108 to turn OFF. In at least one embodiment, PFC and output voltage controller 202 generates a START signal at the beginning of inductor flyback time interval T2 to reset and start the counter/processor 706. The counter/processor 706 operates at a clock frequency f_CLK. The frequency f_CLKis a matter of design choice. Higher values of frequency f_CLKincrease the accuracy of a determined inductor flyback time interval T2. In at least one embodiment, the frequency f_CLKis 10 MHz. The counter/processor 706 begins counting at the end of time interval T1 at the frequency f_CLKand stops counting when signal V_SENSE_—₀transitions from HIGH to LOW. The number of counts divided by the clock frequency f_CLKrepresents the flyback time interval T2.

[0057] Operation 308 determines whichever voltage, i.e. the line input voltage V_x(t) or the output voltage V_c(t), that was not determined in operation 304 using the determined voltage, inductor current i_Lramp-up time interval T1, and the determined inductor flyback time interval T2. If operation 304 determines the line input voltage V_x(t), in at least one embodiment, operation 308 determines the output voltage V_c(t) in accordance with Equation [1]:

[0058]

\begin{matrix} V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2} . & Equation [1] \end{matrix}

T1 is the inductor current i_Lramp-up time interval, and T2 is the inductor flyback time interval. The voltage V_xand the voltage V_cof Equation [1] represent the respective actual, approximate, scaled, or sampled versions of line input voltage V_x(t) and output voltage V_c(t).

[0059] If operation 304 determines the output voltage V_c(t), in at least one embodiment, operation 308 determines the line input voltage V_x(t) in accordance with Equation [2]:

[0060]

\begin{matrix} V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)} . & Equation [2] \end{matrix}

T1 is the inductor current i_Lramp-up time interval, and T2 is the inductor flyback time interval. The voltage V_xand the voltage V_cof Equation [2] represent the respective actual, approximate, scaled, or sampled versions of line input voltage V_x(t) and output voltage V_c(t).

[0061] Operation 310 determines the pulse width PW and duty cycle D of switch control signal CS₁. The PFC and output voltage controller 202 controls the pulse width PW and period T of control signal C_S1Power and control system 200 represents a nonlinear process because the power delivered by the switching power converter 201 is related to a square of the line input voltage V_x(t). PFC and output voltage controller 202 controls the nonlinear process of switching power converter 201 so that a desired amount of energy is transferred to capacitor 106. The desired amount of energy depends upon the voltage and current requirements of load 112. The duty cycle of control signal CS₁is set to maintain the desired output voltage V_C(t) and load voltage V_L(t), and, in at least one embodiment, the duty cycle D of control signal CS₁equals [V_L(t)/(V_C(t)+V_L(t))]. Energy transfer increases during a period of time as the line input voltage V_x(t) increases.

[0062] To regulate the amount of energy transferred and maintain a power factor correction close to one, PFC and output voltage controller 202 varies the period of control signal CS₁so that the inductor current i_Ltracks the changes in line input voltage V_x(t) and holds the output voltage V_C(t) constant. Thus, as the line input voltage V_x(t) increases, PFC and output voltage controller 202 increases the period TT (FIG. 6) of control signal CS₁, and as the line input voltage V_x(t) decreases, PFC and output voltage controller 202 decreases the period TT (FIG. 6) of control signal CS₁. At the same time, the pulse width PW of control signal CS₁is adjusted to maintain a constant duty cycle D, and, thus, hold the output voltage V_C(t) constant. In at least one embodiment, the PFC and output voltage controller 202 updates the control signal CS₁at a frequency much greater than the frequency of line input voltage V_x(t). The frequency of line input voltage V_x(t) is generally 50-60 Hz. The frequency 1/T of control signal CS₁is, for example, between 20 kHz and 150 kHz. Frequencies at or above 20 kHz avoids audio frequencies, and frequencies at or below 150 kHz avoids significant switching inefficiencies while still maintaining good power factor correction, e.g. between 0.9 and 1, and an approximately constant output voltage V_C(t).

[0063] FIG. 8 depicts PFC and output voltage controller 800, which represents one embodiment of PFC and output voltage controller 202. The PFC and output voltage controller 800 generates the control signal CS₁to control the nonlinear energy transfer process of switching power converter 201. A nonlinear delta-sigma modulator 802 receives an energy input signal E(n) indicating a desired amount of energy transfer during the next cycle of control signal CS₁to maintain a desired output voltage V_c(t). The nonlinear delta-sigma modulator 802 processes the energy input signal E(n) and generates a quantizer output signal Q_PW. A nonlinear feedback model 803 of nonlinear delta-sigma modulator 802 models the nonlinear energy transfer process of switching power converter 201 so that the quantizer output signal Q_PWrepresents a pulse width for control signal CS₁that matches the energy transfer needed by capacitor 106 to maintain an approximately constant output voltage V_c(t). Exemplary embodiments of PFC and output voltage controller 800 and nonlinear feedback model 803 are described in more detail in U.S. patent application Ser. No. 11/865,032, entitled “Control System Using A Nonlinear Delta-Sigma Modulator With Nonlinear Process Modeling”, inventor John L. Melanson, and filing date Sep. 30, 2007 (“Melanson I”)m now U.S. Pat. No. 7,554,473 and in U.S. Patent Application entitled “Power Control System Using a Nonlinear Delta-Sigma Modulator With Nonlinear Power Conversion Process Modeling”, inventor John L. Melanson, assignee Cirrus Logic, Inc., U.S. patent application Ser. No. 11/967,277, now U.S. Pat. No. 7.719,246. Melanson I and Melanson II are incorporated herein by reference in their entireties.

[0064] In at least one embodiment, line input signal V_x(t) is a rectified voltage and, thus, rises and falls over time. The PFC and output voltage controller 800 is configured to track the changes in line input signal V_x(t) and adjust the period of control signal CS₁to increase as line input signal V_x(t) increases and to decrease as line input signal V_x(t) decreases. To determine each period of control signal CS₁, PFC and output voltage controller 800 includes an input signal estimator 805 to estimate the instantaneous values of line input voltage V_x(t) for each cycle of control signal CS₁and generate an estimated voltage value EV(n). In at least one embodiment, the input signal estimator 805 performs operation 304 to determine the line input voltage V_x(t) from the feedback signal V_S(t). The PFC and output voltage controller 800 includes a conventional delta-sigma modulator 804 to process the estimated voltage value EV(n) and convert the estimated voltage value EV(n) into a quantizer output signal Q_T. The quantizer output signal Q_Trepresents a period of control signal CS₁for the estimated value of line input voltage V_x(t). Exemplary conventional delta-sigma modulator design and operation is described in the book Understanding Delta-Sigma Data Converters by Schreier and Temes, IEEE Press, 2005, ISBN 0-471-46585-2.

[0065] The PFC and output voltage controller 800 includes a pulse width modulator 806 to convert the quantizer output signal Q_PW(n) into a pulse width and quantizer output signal Q_T(n) into a period for control signal CS₁, where n can be a number representing a particular instance of the associated variable. To perform the conversions, in at least one embodiment, pulse with modulator 806 includes a counter. The quantizer output signal Q_PW(n) indicates that number of counts for the pulse width of control signal CS₁, and the quantizer output signal Q_T(n) indicates the number of counts for the period of control signal CS₁. The pulse width modulator 806 translates the number of counts for the quantizer output signal Q_PW(n) and the quantizer output signal Q_T(n) into the respective pulse width and period of control signal CS₁. In at least one embodiment, PFC and output voltage controller 800 is implemented using digital technology. In other embodiments, PFC and output voltage controller 800 can be implemented using analog or mixed digital and analog technology.

[0066] Referring to FIGS. 2 and 8, when nonlinear delta-sigma modulator 802 is used as part of a PFC and output voltage controller, such as PFC and output voltage controller 800 (FIG. 8), for maintaining power factor correction, the energy input signal E(n) is proportional to (1−(V_x(t)/V_C(t))·K. “K” is a constant representing power demand by load 112 as determined by a proportional integral compensator (not shown) that compares the output voltage V_c(t) to a reference voltage and determines a feedback signal that is a combination of an integral and proportionate function of the output voltage error. An example of a proportional integral compensator is described in Alexander Prodić, “Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers”, IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007 and Erickson and Maksomovic, “Fundamentals of Power Electronics”, 2^nded., Boston, Mass.: Kluwer, 2000, which is incorporated herein by reference in its entirety. In at least one embodiment, the energy input signal E(n) is constrained to ensure that switching power converter 201 operates in discontinuous current mode.

[0067] Operation 312 provides the switch control signal CS₁to switching power converter 201. After operation 312, PFC and output voltage regulation process 300 returns to operation 302 for the next period of control signal CS₁.

[0068] Operations 304 and 306 can be determined using a variety of systems and processes. FIG. 9 depicts a power control system 900, which is one embodiment of power control system 150. Power control system includes PFC and output voltage controller 904, and PFC and output voltage controller 904 operates in accordance with PFC and output voltage regulation process 300. However, the particular implementation of operations 304 and 306 differ from the application of PFC and output voltage regulation process 300 in conjunction with power control system 200. Switch 908 is a FET, and the control signal CS₁is applied to a gate of switch 908. The gate voltage V_gof the switch 108 can be monitored and used to determine the inductor flyback time interval T2.

[0069] In at least one embodiment, operation 306 determines the end of inductor flyback time interval T2 by monitoring the gate charge characteristics of switch 908 to detect the end of inductor flyback time interval T2. FIG. 10 depicts a graph 1000 of feedback signal V_S(t) and corresponding ideal and actual gate voltages V_gand actual gate currents i_g. Referring to FIGS. 9 and 10, ideally during each period of control signal CS₁, the gate voltage V_ghas a logical HIGH pulse 1002 corresponding to the switch 908 ON time and is otherwise a logical LOW. Likewise, ideally during each period of control signal CS₁, the gate current i_ghas a brief pulse 1004 to charge the gate of switch 908 and has a brief pulse 1006 to discharge the gate of switch 908. Ideally, pulses 1004 and 1006 are the only pulses of the gate current i_g. However, the switch 108 has a parasitic gate-to-drain Miller capacitance 914. The parasitic capacitance causes transient voltage signals 1008 and transient current signals 1010 at the gate of switch 108 when the feedback signal V_S(t) at the SWITCH NODE transitions from voltage V_c(t) to voltage V_x(t) at the end of the inductor flyback time interval T2. (The transient signals are not necessarily drawn to scale in FIG. 10, and the magnitudes of the transient signals will vary depending upon the components used to implement switching power converter 906.) In at least one embodiment, the transient current signals, transient voltage signals, or both can be detected by respective embodiments of the PFC and output voltage controller 904. Thus, PFC and output voltage controller 904 in operation 306 can determine the inductor flyback time interval T2 by determining the beginning of inductor flyback time interval T2 and determining the elapsed time until the transient signal(s) are detected.

[0070] In at least one embodiment, to perform operation 304 in conjunction with power control system 900, the line input voltage V_x(t) can be determined by directly detecting the line input voltage V_x(t) from a feedback signal at node 916 or, as previously described, determined from the feedback signal V_S(t). In another embodiment, to perform operation 304 in conjunction with power control system 900, the output voltage V_c(t) can be determined by directly detecting the output voltage V_c(t) from a feedback signal at node 918 or, as previously described, determined from the feedback signal V_S(t). The dashed lines from the SWITCH NODE and nodes 916 and 918 indicate that operation 304 can be performed using any one of the feedback signals, i.e. V_x(t), V_c(t), or V_S(t). The output voltage V_c(t) can be detected in any of a variety of ways including as described in the exemplary embodiments of U.S. patent application Ser. No. 11/967,276, entitled “Power Factor Correction Controller With Digital FIR Filter Output Voltage Sampling”, inventor John L. Melanson, assignee Cirrus Logic, Inc., and (“Melanson III”) and U.S. patent application Ser. No. 11/967,277, entitled “Power Supply Dc Voltage Offset Detector”, inventor John L. Melanson, assignee Cirrus Logic, Inc., and (“Melanson IV”), now U.S. Pat. No. 7,863,828. Melanson III and Melanson IV are incorporated herein by reference in their entireties.

[0071] Operations 308-312 are performed by PFC and output voltage controller 904 as described in conjunction with PFC and output voltage controller 202.

[0072] FIG. 11 depicts an exemplary inductor flyback time interval determination module (“flyback time module”) 1100 to determine the inductor flyback time interval T2 using the transient voltage signal 1008. In at least one embodiment, the PFC and output voltage controller 906 includes flyback time module 1100. The flyback time module 1100 detects the gate voltage V_g, and comparator 1102 compares the gate voltage with a reference voltage V_REF1. The reference voltage V_REF1is predetermined and set between the steady state gate voltage V_gduring the inductor flyback time interval T2 and the minimum voltage of the transient 1008. In at least one embodiment, V_REF1is set at −0.5 V. When the feedback signal V_S(t) transitions from voltage V_c(t) to voltage V_x(t), the gate voltage V_gtransient 1008 decreases below the reference voltage V_REF1, and the output signal V_SENSE_—₁of comparator 1102 changes from a logical HIGH to a logical LOW.

[0073] The transition of the comparator output signal V_SENSE_—₁of comparator 1102 from logical HIGH to logical LOW indicates an end of the inductor flyback time interval T2. The flyback time module 1100 includes counter/processor 706 that begins counting at the beginning of inductor flyback time interval T2. As previously discussed, the beginning of inductor flyback time interval T2 is known because the beginning coincides with the end of inductor current i_Lramp-up time interval T1. The PFC and output voltage controller 904 determines the end of time interval T1, which occurs when control signal CS₁causes switch 908 to turn OFF. In at least one embodiment, PFC and output voltage controller 906 generates a START signal at the beginning of inductor flyback time interval T2 to reset the counter/processor 706. Using the input signal V_SENSE_—₁, the counter/processor 706 determines inductor flyback time interval T2 as previously described.

[0074] FIG. 12 depicts a power control system 1200, which is one embodiment of power control system 150. Power control system 1200 includes PFC and output voltage controller 1204, and PFC and output voltage controller 1204 operates in accordance with PFC and output voltage regulation process 300. However, the particular implementation of operations 304 and 306 differ from the application of PFC and output voltage regulation process 300 in conjunction with power control system 200.

[0075] Referring to FIGS. 3 and 12, operation 306 senses the inductor voltage V_L(t) using a secondary winding 1206 magnetically coupled to inductor 110. The inductor 110 represents a primary winding, and the inductor voltage V_P(t) is directly proportional to the inductor current i_L. Thus, the inductor flyback time interval T2 can be determined directly by sensing changes in the inductor voltage V_P(t) corresponding to the ramping down of the inductor current i_L. In at least one embodiment, the PFC and output voltage controller 1204 includes two terminals to receive the feedback signal V_S(t) generated by the secondary winding 1206.

[0076] Inductor 110 induces a secondary voltage V_S(t) in the secondary winding 1206 that is directly proportional to the inverse of the inductor voltage V_P(t). The secondary voltage V_S(t) represents a feedback signal to PFC and output voltage controller 1204. The feedback signal V_S(t) relates to the inductor voltage in accordance with Equation [3]:

[0077]

\begin{matrix} V_{P} (t) = - V_{S} (t) \cdot \frac{n_{S}}{n_{P}} = - V_{S} (t) \cdot k . & Equation [3] \end{matrix}

“n_S” is the number of windings in the second winding 1206, “n_Pp” is the number of windings in the inductor 110, and k=n_S/n_P. The value of “n_P” is set by the choice of inductor 110. The value of “n_S” can be set so that PFC and output voltage controller 1204 can receive feedback signal V_S(t) directly without any conversion.

[0078] Referring to FIGS. 3, 6, 11, 12, and 13, during time interval T1, switch 108 conducts, and the feedback signal V_S(t) equals −V_x(t)·k. Thus, operation 304 can determine the line input voltage V_x(t) by sensing the feedback signal V_S(t) during time interval T1 and dividing the feedback signal by −k. During inductor flyback time interval T2, the feedback signal V_S(t) relates to the output voltage V_c(t) and line input voltage in accordance with Equation [4]:
V_S(t)=(V_c(t)−V_x(t))·k Equation [4].

[0079] FIG. 13 depicts an inductor flyback time interval determination module to perform operation 306. The flyback time module 1300 receives the feedback signal V_S(t), and comparator 1302 compares the feedback signal to V_REF2, and determines the time interval between the end of time interval T1 and when the feedback signal V_S(t) transitions below V_REF2, with V_REF2set between (V_c(t)−V_x(t))·k and −V_x(t).

[0080] Operations 308-312 are performed by PFC and output voltage controller 1204 as described in conjunction with PFC and output voltage controller 202.

[0081] FIG. 14 depicts power control system 1400, which is one embodiment of the power control system of FIG. 1A. Power control system 1400 that includes a redundancy and reliability module 1406 in the PFC and output voltage controller 1404 to provide reliability and/redundancy to power control system 1400. In at least one embodiment, power control system 1400 can function and be implemented identically to power control system 200, power control system 900, and power control system 1100 except that power control system 1400 includes extra feedback signals to provide redundancy and reliability. In at least one embodiment, power control system 1400 provides a high output voltage V_c(t) such as 400 V. High voltages pose particular safety concerns and hardware failure concerns. Thus, in addition to determining the output voltage V_c(t) and line input voltage V_x(t) in accordance with any embodiment previously described, additional feedback signals can be used, such as directly sensing the line input voltage V_x(t) from node 1408, the output voltage V_c(t) from node 1410, the line input voltage V_x(t) and/or the output voltage V_c(t) from the SWITCH NODE, and/or the inductor voltage across the inductor 110 using a secondary winding as previously described (not shown).

[0082] The additionally sensed, redundant parameters can be converted using sensor/converters 206 as desired, and reliability and redundancy module 1406 can compare the values of line input voltage V_x(t) and output voltage V_c(t) to the corresponding values determined by PFC and output voltage regulation process 300. The reliability and redundancy module 1406 includes logic to, for example, shut down the power control system 1400 if the values disagree by a predetermined margin. In at least one embodiment, if PFC and output voltage regulation process 300 is unable to determine the output voltage V_C(t) or the line input voltage V_x(t), the reliability and redundancy module 1406 can use one of the additionally sensed values as a substitute, thus providing redundancy.

[0083] Thus, during a single period of the control signal, embodiments of the PFC and output voltage controller obtain the line input voltage and output voltage of the switching power converter using a single feedback signal received from the switching power converter.

[0084] Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

What is claimed is:

1. A power factor correction (PFC) controller to control power factor correction and regulate output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the PFC controller comprising:

an input to receive a feedback signal from the switching power converter;

wherein the PFC controller is configured to cause the switching power converter to operate in discontinuous conduction mode and is further configured to:

(a) determine at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;

(b) provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;

(d1) wherein, if the line input voltage is determined in (a), the PFC controller is further configured to determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval;

(d2) wherein, if the output voltage of the switching power converter is determined in (a), the PFC controller is further configured to determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

2. The PFC controller of claim 1 wherein the PFC controller is configured to determine the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

3. The PFC controller of claim 1 wherein the PFC controller is configured to determine the line input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

4. The PFC controller of claim 1 wherein the switch comprises a field effect transistor and the PFC controller is configured to sense voltage transients on the gate of the switch to determine the inductor flyback time interval.

5. The PFC controller of claim 1 wherein, during operation of the PFC controller and the switching power converter, a sensor senses the line input voltage across the inductor.

6. The PFC controller of claim 5 wherein the sensor further comprises a secondary winding magnetically coupled to the inductor to sense the voltage across the inductor.

7. The PFC controller of claim 1 wherein the PFC controller is further configured to determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval and determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

8. The PFC controller of claim 1 wherein the PFC controller comprises an integrated circuit having a number of contacts to provide external connections, wherein the contacts of the PFC controller include a contact for only one member of a group consisting of: (i) the line input voltage and (ii) the output voltage of the switching power converter from the feedback signal.

9. The PFC controller of claim 1 wherein:

if the input voltage of the switching power converter is determined in (a), the PFC controller is configured to determine the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

if the output voltage of the switching power converter is determined in (a), the PFC controller is configured to determine the line input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}

T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage; and

TT is a period of the control signal, and TT is greater than T1+T2.

10. A power factor correction (PFC) controller to control power factor correction and regulate output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the PFC controller comprising:

an input to receive a feedback signal from the switching power converter;

wherein the PFC controller is configured to cause the switching power converter to operate in discontinuous conduction mode and is further configured to:

determine a line input voltage;

provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;

sense one or more voltage transients on a gate of the switch to determine the inductor flyback time interval; and

determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval.

11. A power factor correction (PFC) controller to control power factor correction and regulate output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the PFC controller comprising:

an input to receive a feedback signal from the switching power converter;

wherein the PFC controller is configured to cause the switching power converter to operate in discontinuous conduction mode and is further configured to:

determine an output voltage of the switching power converter from the feedback signal;

sense one or more voltage transients on a gate of the switch to determine the inductor flyback time interval; and

determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

12. A method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the method comprising:

receiving a feedback signal from the switching power converter;

(a) determining at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;

(b) providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;

(d1) wherein, if the line input voltage is determined in (a), determining the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval;

(d2) wherein, if the output voltage of the switching power converter is determined in (a), determining the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval; and

causing the switching power converter to operate in discontinuous conduction mode.

13. The method of claim 12 further comprising:

determining the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

14. The method of claim 12 further comprising:

determining the input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

15. The method of claim 12 wherein the switch comprises a field effect transistor, the method further comprising:

sensing voltage transients on a gate of the switch to determine the inductor flyback time interval.

16. The method of claim 12 further comprising:

generating the feedback signal via a secondary winding magnetically coupled to the inductor.

17. The method of claim 12 further comprising:

sensing the line input voltage across the inductor.

18. The method of claim 17 wherein sensing the line input voltage across the inductor comprises:

inducing a current in a secondary winding from current in the inductor;

sensing the induced current;

converting the sensed induced current into a voltage corresponding to the line input voltage; and

sensing the voltage corresponding to the line input voltage.

19. The method of claim 12 wherein the switching power converter further includes a capacitor coupled to the inductor, the switch, and an output voltage node, the method further comprising:

sensing the switching power converter output voltage across the capacitor.

20. The method of claim 12 further comprising:

if the input voltage of the switching power converter is determined in (a),determining the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

if the output voltage of the switching power converter is determined in (a),determining the input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage; and

TT is a period of the control signal, and TT is greater than T1+T2.

21. A method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the method comprising:

receiving a feedback signal from the switching power converter;

determining a line input voltage;

providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;

sensing one or more voltage transients on a gate of the switch to determine the inductor flyback time interval;

determining an output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval; and

causing the switching power converter to operate in discontinuous conduction mode.

22. A method of controlling power factor correction and regulating output voltage of a switching power converter, wherein the switching power converter includes an inductor to couple to a line input voltage node and a switch coupled to the inductor, the method comprising:

receiving a feedback signal from the switching power converter;

determining an output voltage of the switching power converter from the feedback signal;

sensing one or more voltage transients on a gate of the switch to determine the inductor flyback time interval;

determining a line input voltage using the output voltage, the inductor flyback time interval, and the first time interval; and

causing the switching power converter to operate in discontinuous conduction mode.

Patent Citations (265)

Patent	Date	Inventor	Cited By
US3790878(A)	1974-02-01	Brokaw	Applicant
US3881167(A)	1975-04-01	Pelton et al.	Applicant
US4075701(A)	1978-02-01	Hofmann	Applicant
US4334250(A)	1982-06-01	Theus	Applicant
US4409476(A)	1983-10-01	Lofgren et al.	Applicant
US4414493(A)	1983-11-01	Henrich	Applicant
US4476706(A)	1984-10-01	Hadden et al.	Applicant
US4523128(A)	1985-06-01	Stamm	Applicant
US4677366(A)	1987-06-01	Wilkinson et al.	Applicant
US4683529(A)	1987-07-01	Bucher	Applicant
US4700188(A)	1987-10-01	James	Applicant
US4737658(A)	1988-04-01	Kronmuller et al.	Applicant
US4797633(A)	1989-01-01	Humphrey	Applicant
US4937728(A)	1990-06-01	Leonardi	Applicant
US4940929(A)	1990-07-01	Williams	Applicant
US4973919(A)	1990-11-01	Allfather	Applicant
US4979087(A)	1990-12-01	Sellwood et al.	Applicant
US4980898(A)	1990-12-01	Silvian	Applicant
US4992919(A)	1991-02-01	Lee et al.	Applicant
US4994952(A)	1991-02-01	Silva et al.	Applicant
US5001620(A)	1991-03-01	Smith	Applicant
US5055746(A)	1991-10-01	Hu et al.	Applicant
US5109185(A)	1992-04-01	Ball	Applicant
US5121079(A)	1992-06-01	Dargatz	Applicant
US5206540(A)	1993-04-01	de Sa e Silva et al.	Applicant
US5264780(A)	1993-11-01	Bruer et al.	Applicant
US5278490(A)	1994-01-01	Smedley	Applicant
US5323157(A)	1994-06-01	Ledzius et al.	Applicant
US5359180(A)	1994-10-01	Park et al.	Applicant
US5383109(A)	1995-01-01	Maksimovic et al.	Applicant
US5424932(A)	1995-06-01	Inou et al.	Applicant
US5477481(A)	1995-12-01	Kerth	Applicant
US5479333(A)	1995-12-01	McCambridge et al.	Applicant
US5481178(A)	1996-01-01	Wilcox et al.	Applicant
US5565761(A)	1996-10-01	Hwang	Applicant
US5589759(A)	1996-12-01	Borgato et al.	Applicant
US5638265(A)	1997-06-01	Gabor	Applicant
US5691890(A)	1997-11-01	Hyde	Applicant
US5747977(A)	1998-05-01	Hwang	Applicant
US5757635(A)	1998-05-01	Seong	Examiner
US5768111(A)	1998-06-01	Zaitsu	Applicant
US5781040(A)	1998-07-01	Myers	Applicant
US5783909(A)	1998-07-01	Hochstein	Applicant
US5798635(A)	1998-08-01	Hwang et al.	Applicant
US5867379(A)	1999-02-01	Maksimovic et al.	Examiner
US5900683(A)	1999-05-01	Rinehart et al.	Applicant
US5912812(A)	1999-06-01	Moriarty, Jr.	Applicant
US5929400(A)	1999-07-01	Colby et al.	Applicant
US5946202(A)	1999-08-01	Balogh	Applicant
US5946206(A)	1999-08-01	Shimizu et al.	Applicant
US5952849(A)	1999-09-01	Haigh et al.	Applicant
US5962989(A)	1999-10-01	Baker	Applicant
US5963086(A)	1999-10-01	Hall	Applicant
US5966297(A)	1999-10-01	Minegishi	Applicant
US5994885(A)	1999-11-01	Wilcox et al.	Applicant
US6016038(A)	2000-01-01	Mueller et al.	Applicant
US6043633(A)	2000-03-01	Lev et al.	Applicant
US6072969(A)	2000-06-01	Yokomori et al.	Applicant
US6083276(A)	2000-07-01	Davidson et al.	Applicant
US6084450(A)	2000-07-01	Smith et al.	Applicant
US6091233(A)	2000-07-01	Hwang	Applicant
US6125046(A)	2000-09-01	Jang et al.	Applicant
US6150774(A)	2000-11-01	Mueller et al.	Applicant
US6175218(B1)	2001-01-01	Choi et al.	Examiner
US6178104(B1)	2001-01-01	Choi	Examiner
US6181114(B1)	2001-01-01	Hemena et al.	Applicant
US6211626(B1)	2001-04-01	Lys et al.	Applicant
US6211627(B1)	2001-04-01	Callahan	Applicant
US6229271(B1)	2001-05-01	Liu	Applicant
US6229292(B1)	2001-05-01	Redl et al.	Applicant
US6246183(B1)	2001-06-01	Buonavita	Applicant
US6259614(B1)	2001-07-01	Ribarich et al.	Applicant
US6300723(B1)	2001-10-01	Wang et al.	Applicant
US6304066(B1)	2001-10-01	Wilcox et al.	Applicant
US6304473(B1)	2001-10-01	Telefus et al.	Applicant
US6343026(B1)	2002-01-01	Perry	Applicant
US6344811(B1)	2002-02-01	Melanson	Applicant
US6344986(B1)	2002-02-01	Jain et al.	Examiner
US6369525(B1)	2002-04-01	Chang et al.	Applicant
US6385063(B1)	2002-05-01	Sadek et al.	Applicant
US6407514(B1)	2002-06-01	Glaser et al.	Applicant
US6407515(B1)	2002-06-01	Hesler	Applicant
US6407691(B1)	2002-06-01	Yu	Applicant
US6441558(B1)	2002-08-01	Muthu et al.	Applicant
US6445600(B2)	2002-09-01	Ben-Yaakov	Applicant
US6452521(B1)	2002-09-01	Wang	Applicant
US6469484(B2)	2002-10-01	L'Hermite et al.	Examiner
US6495964(B1)	2002-12-01	Muthu et al.	Applicant
US6509913(B2)	2003-01-01	Martin, Jr. et al.	Applicant
US6531854(B2)	2003-03-01	Hwang	Applicant
US6580258(B2)	2003-06-01	Wilcox et al.	Applicant
US6583550(B2)	2003-06-01	Iwasa et al.	Applicant
US6628106(B1)	2003-09-01	Batarseh et al.	Applicant
US6636003(B2)	2003-10-01	Rahm et al.	Applicant
US6646848(B2)	2003-11-01	Yoshida et al.	Applicant
US6657417(B1)	2003-12-01	Hwang	Applicant
US6713974(B2)	2004-03-01	Patchornik et al.	Applicant
US6724174(B1)	2004-04-01	Esteves et al.	Applicant
US6727832(B1)	2004-04-01	Melanson	Applicant
US6737845(B2)	2004-05-01	Hwang	Applicant
US6741123(B1)	2004-05-01	Andersen et al.	Applicant
US6753661(B2)	2004-06-01	Muthu et al.	Applicant
US6756772(B2)	2004-06-01	McGinnis	Applicant
US6768655(B1)	2004-07-01	Yang et al.	Applicant
US6781351(B2)	2004-08-01	Mednik et al.	Applicant
US6788011(B2)	2004-09-01	Mueller et al.	Applicant
US6806659(B1)	2004-10-01	Mueller et al.	Applicant
US6839247(B1)	2005-01-01	Yang	Applicant
US6860628(B2)	2005-03-01	Robertson et al.	Applicant
US6870325(B2)	2005-03-01	Bushell et al.	Applicant
US6873065(B2)	2005-03-01	Haigh et al.	Applicant
US6882552(B2)	2005-04-01	Telefus et al.	Applicant
US6888322(B2)	2005-05-01	Dowling et al.	Applicant
US6894471(B2)	2005-05-01	Corva et al.	Applicant
US6933706(B2)	2005-08-01	Shih	Applicant
US6940733(B2)	2005-09-01	Schie et al.	Applicant
US6944034(B1)	2005-09-01	Shteynberg et al.	Applicant
US6956750(B1)	2005-10-01	Eason et al.	Applicant
US6958920(B2)	2005-10-01	Mednik et al.	Applicant
US6963496(B2)	2005-11-01	Bimbaud	Applicant
US6967448(B2)	2005-11-01	Morgan et al.	Applicant
US6970503(B1)	2005-11-01	Kalb	Applicant
US6975079(B2)	2005-12-01	Lys et al.	Applicant
US6975523(B2)	2005-12-01	Kim et al.	Applicant
US6980446(B2)	2005-12-01	Simada et al.	Applicant
US7003023(B2)	2006-02-01	Krone et al.	Applicant
US7034611(B2)	2006-04-01	Oswal et al.	Applicant
US7050509(B2)	2006-05-01	Krone et al.	Applicant
US7064498(B2)	2006-06-01	Dowling et al.	Applicant
US7064531(B1)	2006-06-01	Zinn	Applicant
US7072191(B2)	2006-07-01	Nakao et al.	Applicant
US7075329(B2)	2006-07-01	Chen et al.	Applicant
US7078963(B1)	2006-07-01	Andersen et al.	Applicant
US7088059(B2)	2006-08-01	McKinney et al.	Applicant
US7099163(B1)	2006-08-01	Ying	Applicant
US7102902(B1)	2006-09-01	Brown et al.	Applicant
US7106603(B1)	2006-09-01	Lin et al.	Applicant
US7109791(B1)	2006-09-01	Epperson et al.	Applicant
US7135824(B2)	2006-11-01	Lys et al.	Applicant
US7145295(B1)	2006-12-01	Lee et al.	Applicant
US7158633(B1)	2007-01-01	Hein	Applicant
US7161816(B2)	2007-01-01	Shteynberg et al.	Applicant
US7180250(B1)	2007-02-01	Gannon	Applicant
US7183957(B1)	2007-02-01	Melanson	Applicant
US7221130(B2)	2007-05-01	Ribeiro et al.	Applicant
US7233135(B2)	2007-06-01	Noma et al.	Applicant
US7255457(B2)	2007-08-01	Ducharme et al.	Applicant
US7266001(B1)	2007-09-01	Notohamiprodjo et al.	Applicant
US7276861(B1)	2007-10-01	Shteynberg et al.	Applicant
US7288902(B1)	2007-10-01	Melanson	Applicant
US7292013(B1)	2007-11-01	Chen et al.	Applicant
US7310244(B2)	2007-12-01	Yang et al.	Applicant
US7345458(B2)	2008-03-01	Kanai et al.	Applicant
US7388764(B2)	2008-06-01	Huynh et al.	Applicant
US7394210(B2)	2008-07-01	Ashdown	Applicant
US7538499(B2)	2009-05-01	Ashdown	Applicant
US7545130(B2)	2009-06-01	Latham	Applicant
US7554473(B2)	2009-06-01	Melanson	Applicant
US7569996(B2)	2009-08-01	Holmes et al.	Applicant
US7583136(B2)	2009-09-01	Pelly	Applicant
US7656103(B2)	2010-02-01	Shteynberg et al.	Applicant
US7667986(B2)	2010-02-01	Artusi et al.	Applicant
US7710047(B2)	2010-05-01	Shteynberg et al.	Applicant
US7719246(B2)	2010-05-01	Melanson	Applicant
US7719248(B1)	2010-05-01	Melanson	Applicant
US7746043(B2)	2010-06-01	Melanson	Examiner
US7746671(B2)	2010-06-01	Radecker et al.	Applicant
US7750738(B2)	2010-07-01	Bach	Applicant
US7756896(B1)	2010-07-01	Feingold	Applicant
US7777563(B2)	2010-08-01	Midya et al.	Applicant
US7804256(B2)	2010-09-01	Melanson	Applicant
US7804480(B2)	2010-09-01	Jeon et al.	Applicant
US2002/0065583(A1)	2002-05-01	Okada	Applicant
US2002/0145041(A1)	2002-10-01	Muthu et al.	Applicant
US2002/0150151(A1)	2002-10-01	Krone et al.	Applicant
US2002/0166073(A1)	2002-11-01	Nguyen et al.	Applicant
US2003/0095013(A1)	2003-05-01	Melanson et al.	Applicant
US2003/0174520(A1)	2003-09-01	Bimbaud	Applicant
US2003/0223255(A1)	2003-12-01	Ben-Yaakov	Applicant
US2004/0004465(A1)	2004-01-01	McGinnis	Applicant
US2004/0046683(A1)	2004-03-01	Mitamura et al.	Applicant
US2004/0085030(A1)	2004-05-01	Laflamme et al.	Applicant
US2004/0085117(A1)	2004-05-01	Melbert et al.	Applicant
US2004/0169477(A1)	2004-09-01	Yanai et al.	Applicant
US2004/0227571(A1)	2004-11-01	Kuribayashi	Applicant
US2004/0228116(A1)	2004-11-01	Miller et al.	Applicant
US2004/0232971(A1)	2004-11-01	Kawasaki et al.	Applicant
US2004/0239262(A1)	2004-12-01	Ido et al.	Applicant
US2005/0057237(A1)	2005-03-01	Clavel	Applicant
US2005/0156770(A1)	2005-07-01	Melanson	Applicant
US2005/0168492(A1)	2005-08-01	Hekstra et al.	Applicant
US2005/0184895(A1)	2005-08-01	Petersen et al.	Applicant
US2005/0197952(A1)	2005-09-01	Shea et al.	Applicant
US2005/0207190(A1)	2005-09-01	Gritter	Applicant
US2005/0218838(A1)	2005-10-01	Lys	Applicant
US2005/0222881(A1)	2005-10-01	Booker	Applicant
US2005/0253533(A1)	2005-11-01	Lys et al.	Applicant
US2005/0270813(A1)	2005-12-01	Zhang et al.	Applicant
US2005/0275354(A1)	2005-12-01	Hausman, Jr. et al.	Applicant
US2005/0275386(A1)	2005-12-01	Jepsen et al.	Applicant
US2006/0002110(A1)	2006-01-01	Dowling	Applicant
US2006/0013026(A1)	2006-01-01	Frank et al.	Examiner
US2006/0022916(A1)	2006-02-01	Aiello	Applicant
US2006/0023002(A1)	2006-02-01	Hara et al.	Applicant
US2006/0116898(A1)	2006-06-01	Peterson	Applicant
US2006/0125420(A1)	2006-06-01	Boone et al.	Applicant
US2006/0184414(A1)	2006-08-01	Pappas et al.	Applicant
US2006/0214603(A1)	2006-09-01	Oh et al.	Applicant
US2006/0226795(A1)	2006-10-01	Walter et al.	Applicant
US2006/0261754(A1)	2006-11-01	Lee	Applicant
US2006/0285365(A1)	2006-12-01	Huynh et al.	Applicant
US2007/0024213(A1)	2007-02-01	Shteynberg et al.	Applicant
US2007/0029946(A1)	2007-02-01	Yu et al.	Applicant
US2007/0040512(A1)	2007-02-01	Jungwirth et al.	Applicant
US2007/0053182(A1)	2007-03-01	Robertson	Applicant
US2007/0055564(A1)	2007-03-01	Fourman	Applicant
US2007/0103949(A1)	2007-05-01	Tsuruya	Applicant
US2007/0126656(A1)	2007-06-01	Huang et al.	Applicant
US2007/0182699(A1)	2007-08-01	Ha et al.	Applicant
US2007/0285031(A1)	2007-12-01	Shteynberg et al.	Applicant
US2008/0012502(A1)	2008-01-01	Lys	Applicant
US2008/0027841(A1)	2008-01-01	Eder	Applicant
US2008/0043504(A1)	2008-02-01	Ye et al.	Applicant
US2008/0054815(A1)	2008-03-01	Kotikalapoodi et al.	Applicant
US2008/0116818(A1)	2008-05-01	Shteynberg et al.	Applicant
US2008/0130336(A1)	2008-06-01	Taguchi	Applicant
US2008/0150433(A1)	2008-06-01	Tsuchida et al.	Applicant
US2008/0154679(A1)	2008-06-01	Wade	Applicant
US2008/0174291(A1)	2008-07-01	Hansson et al.	Applicant
US2008/0174372(A1)	2008-07-01	Tucker et al.	Applicant
US2008/0175029(A1)	2008-07-01	Jung et al.	Applicant
US2008/0192509(A1)	2008-08-01	Dhuyvetter et al.	Applicant
US2008/0224635(A1)	2008-09-01	Hayes	Applicant
US2008/0239764(A1)	2008-10-01	Jacques et al.	Applicant
US2008/0259655(A1)	2008-10-01	Wei et al.	Applicant
US2008/0278132(A1)	2008-11-01	Kesterson et al.	Applicant
US2009/0067204(A1)	2009-03-01	Ye et al.	Applicant
US2009/0070188(A1)	2009-03-01	Scott et al.	Applicant
US2009/0147544(A1)	2009-06-01	Melanson	Applicant
US2009/0174479(A1)	2009-07-01	Yan et al.	Applicant
US2009/0218960(A1)	2009-09-01	Lyons et al.	Applicant
US2010/0141317(A1)	2010-06-01	Szajnowski	Applicant
DE19713814	1998-10-01		Applicant
EP585789(A1)	1994-03-01		Applicant
EP632679	1995-01-01		Applicant
EP838791	1998-04-01		Applicant
EP910168(A1)	1999-04-01		Applicant
EP1014563	2000-06-01		Applicant
EP1164819(A)	2001-12-01		Applicant
EP1213823(A2)	2002-06-01		Applicant
EP1460775	2004-09-01		Applicant
EP1528785(A)	2005-05-01		Applicant
EP2204905(A1)	2010-07-01		Applicant
WO9725836	1997-07-01		Applicant
WO1/97384(A)	2001-12-01		Applicant
WO227944	2002-04-01		Applicant
WO2/091805(A2)	2002-11-01		Applicant
WO2006013557	2006-02-01		Applicant
WO2006/022107(A2)	2006-03-01		Applicant
WO2006/067521(A)	2006-06-01		Applicant
WOW02006135584	2006-12-01		Applicant
WO2007/026170(A)	2007-03-01		Applicant
WO2007/079362(A)	2007-07-01		Applicant
WO2008072160	2008-06-01		Applicant
WO2008152838	2008-12-01		Applicant

Non-Patent Literature (174)

“HV9931 Unity Power Factor Led Lamp Driver, Initial Release” 2005, Supertex Inc., Sunnyvale, CA USA.Applicant
“AN-H52 Application Note: ”HV9931 Unity Power Factor LED Lamp Driver Mar. 7, 2007, Supertex Inc., Sunnyvale, CA, USA.Applicant
Dustin Rand et al: “Issues, Models and Solutions for Triac Modulated Phase Dimming of LED Lamps” Power Electronics Specialists Conference, 2007. PESC 2007, IEEE, IEEE, P1, Jun. 1, 2007, pp. 1398-1404.Applicant
Spiazzi G et al: “Analysis of a High-Power-Factor Electronic Ballast for High Brightness Light Emitting Diodes” Power Electronics Specialists, 2005 IEEE 36th Conference on Jun. 12, 2005, Piscatawa, NJ USA, IEEE, Jun. 12, 2005, pp. 1494-1499.Applicant
International Search Report PCT/US2008/062381 dated Feb. 5, 2008.Applicant
International Search Report PCT/US2008/056739 dated Dec. 3, 2008.Applicant
Written Opinion of the International Searching Authority PCT/US2008/062381 dated Feb. 5, 2008.Applicant
Ben-Yaakov et al, “The Dynamics of a PWM Boost Converter with Resistive Input” IEEE Transactions on Industrial Electronics, IEEE Service Center, Piscataway, NJ, USA, vol. 46, No. 3, Jun. 1, 1999.Applicant
International Search Report PCT/US2008/062398 dated Feb. 5, 2008.Applicant
Partial International Search PCT/US2008/062387 dated Feb. 5, 2008.Applicant
Noon, Jim “UC3855A/B High Performance Power Factor Preregulator”, Texas Instruments, SLUA146A, May 1996, Revised Apr. 2004.Applicant
“High Performance Power Factor Preregulator”, Unitrode Products from Texas Instruments, SLUS382B, Jun. 1998, Revised Oct. 2005.Applicant
International Search Report PCT/GB2006/003259 dated Jan. 12, 2007.Applicant
Written Opinion of the International Searching Authority PCT/US2008/056739.Applicant
International Search Report PCT/US2008/056606 dated Dec. 3, 2008.Applicant
Written Opinion of the International Searching Authority PCT/US2008/056606 dated Dec. 3, 2008.Applicant
International Search Report PCT/US2008/056608 dated Dec. 3, 2008.Applicant
Written Opinion of the International Searching Authority PCT/US2008/056608 dated Dec. 3, 2008.Applicant
International Search Report PCT/GB2005/050228 dated Mar. 14, 2006.Applicant
International Search PCT/US2008/062387 dated Jan. 10, 2008.Applicant
Data Sheet LT3496 Triple Output LED Driver, 2007, Linear Technology Corporation, Milpitas, CA.Applicant
News Release, Triple Output LED, LT3496.Applicant
Freescale Semiconductor, Inc., Dimmable Light Ballast with Power Factor Correction, Design Reference Manual, DRM067, Rev. 1, Dec. 2005.Applicant
J. Zhou et al., Novel Sampling Algorithm for DSP Controlled 2 kW PFC Converter, IEEE Transactions on Power Electronics, vol. 16, No. 2, Mar. 2001.Applicant
A. Prodic, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, vol. 22, No. 5, Sep. 2007.Applicant
M. Brkovic et al., “Automatic Current Shaper with Fast Output Regulation and Soft-Switching,” S.15.C Power Converters, Telecommunications Energy Conference, 1993.Applicant
Dallas Semiconductor, Maxim, “Charge-Pump and Step-Up DC-DC Converter Solutions for Powering White LEDs in Series or Parallel Connections,” Apr. 23, 2002.Applicant
Freescale Semiconductor, AN3052, Implementing PFC Average Current Mode Control Using the MC9S12E128, Nov. 2005.Applicant
D. Maksimovic et al., “Switching Converters with Wide DC Conversion Range,” Institute of Electrical and Electronic Engineer's (IEEE) Transactions on Power Electronics, Jan. 1991.Applicant
V. Nguyen et al., “Tracking Control of Buck Converter Using Sliding-Mode with Adaptive Hysteresis,” Power Electronics Specialists Conference, 1995. PESC apos; 95 Record., 26th Annual IEEE vol. 2, Issue, Jun. 18-22, 1995 pp. 1086-1093.Applicant
S. Zhou et al., “A High Efficiency, Soft Switching DC-DC Converter with Adaptive Current-Ripple Control for Portable Applications,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 53, No. 4, Apr. 2006.Applicant
K. Leung et al., “Use of State Trajectory Prediction in Hysteresis Control for Achieving Fast Transient Response of the Buck Converter,” Circuits and Systems, 2003. ISCAS apos;03. Proceedings of the 2003 International Symposium, vol. 3, Issue , May 25-28, 2003 pp. III-439-III-442 vol. 3.Applicant
K. Leung et al., “Dynamic Hysteresis Band Control of the Buck Converter with Fast Transient Response,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 52, No. 7, Jul. 2005.Applicant
Y. Ohno, Spectral Design Considerations for White LED Color Rendering, Final Manuscript, Optical Engineering, vol. 44, 111302 (2005).Applicant
S. Skogstad et al., A Proposed Stability Characterization and Verification Method for High-Order Single-Bit Delta-Sigma Modulators, Norchip Conference, Nov. 2006 http://folk.uio.no/sayskogs/pub/A—Proposed—Stability—Characterization.pdf.Applicant
J. Turchi, Four Key Steps to Design a Continuous Conduction Mode PFC Stage Using the NCP1653, on Semiconductor, Publication Order No. AND184/D, Nov. 2004.Applicant
Megaman, D or S Dimming ESL, Product News, Mar. 15, 2007.Applicant
J. Qian et al., New Charge Pump Power-Factor-Correction Electronic Ballast with a Wide Range of Line Input Voltage, IEEE Transactions on Power Electronics, vol. 14, No. 1, Jan. 1999.Applicant
P. Green, A Ballast that can be Dimmed from a Domestic (Phase-Cut) Dimmer, IRPLCFL3 rev. b, International Rectifier, http://www.irf.com/technical-info/refdesigns/cfl-3.pdf, printed Mar. 24, 2007.Applicant
J. Qian et al., Charge Pump Power-Factor-Correction Technologies Part II: Ballast Applications, IEEE Transactions on Power Electronics, vol. 15, No. 1, Jan. 2000.Applicant
Chromacity Shifts in High-Power White LED Systems due to Different Dimming Methods, Solid-State Lighting, http://www.Irc.rpi.edu/programs/solidstate/completedProjects.asp?ID=76, printed May 3, 2007.Applicant
S. Chan et al., Design and Implementation of Dimmable Electronic Ballast Based on Integrated Inductor, IEEE Transactions on Power Electronics, vol. 22, No. 1, Jan. 2007.Applicant
M. Madigan et al., Integrated High-Quality Rectifier-Regulators, IEEE Transactions on Industrial Electronics, vol. 46, No. 4, Aug. 1999.Applicant
T. Wu et al., Single-Stage Electronic Ballast with Dimming Feature and Unity Power Factor, IEEE Transactions on Power Electronics, vol. 13, No. 3, May 1998.Applicant
F. Tao et al., “Single-Stage Power-Factor-Correction Electronic Ballast with a Wide Continuous Dimming Control for Fluorescent Lamps,” IEEE Power Electronics Specialists Conference, vol. 2, 2001.Applicant
Azoteq, IQS17 Family, IQ Switch®—ProxSense™ Series, Touch Sensor, Load Control and User Interface, IQS17 Datasheet V2.00.doc, Jan. 2007.Applicant
C. Dilouie, Introducing the LED Driver, EC&M, Sep. 2004.Applicant
S. Lee et al., TRIAC Dimmable Ballast with Power Equalization, IEEE Transactions on Power Electronics, vol. 20, No. 6, Nov. 2005.Applicant
L. Gonthier et al., EN55015 Compliant 500W Dimmer with Low-Losses Symmetrical Switches, 2005 European Conference on Power Electronics and Applications, Sep. 2005.Applicant
Why Different Dimming Ranges? The Difference Between Measured and Perceived Light, http://www.lutron.com/ballast/pdf/LutronBallastpg3.pdf.Applicant
D. Hausman, Real-Time Illumination Stability Systems for Trailing-Edge (Reverse Phase Control) Dimmers, Technical White Paper, Lutron, version 1.0, Dec. 2004, http://www.lutron.com/technical—info/pdf/RTISS-TE.pdf.Applicant
Light Dimmer Circuits, www.epanorama.net/documents/lights/lightdimmer.html, printed Mar. 26, 2007.Applicant
Light Emitting Diode, http://en.wikipedia.org/wiki/Light-emitting—diode, printed Mar. 27, 2007.Applicant
Color Temperature, www.sizes.com/units/color—temperature.htm, printed Mar. 27, 2007.Applicant
S. Lee et al., A Novel Electrode Power Profiler for Dimmable Ballasts Using DC Link Voltage and Switching Frequency Controls, IEEE Transactions on Power Electronics, vol. 19, No. 3, May 2004.Applicant
Y. Ji et al., Compatibility Testing of Fluorescent Lamp and Ballast Systems, IEEE Transactions on Industry Applications, vol. 35, No. 6, Nov./Dec. 1999.Applicant
National Lighting Product Information Program, Specifier Reports, “Dimming Electronic Ballasts,” vol. 7, No. 3, Oct. 1999.Applicant
Supertex Inc., Buck-based LED Drivers Using the HV9910B, Application Note AN-H48, Dec. 28, 2007.Applicant
D. Rand et al., Issues, Models and Solutions for Triac Modulated Phase Dimming of LED Lamps, Power Electronics Specialists Conference, 2007.Applicant
Supertex Inc., HV9931 Unity Power Factor LED Lamp Driver, Application Note AN-H52, Mar. 7, 2007.Applicant
Supertex Inc., 56W Off-line LED Driver, 120VAC with PFC, 160V, 350mA Load, Dimmer Switch Compatible, DN-H05, Feb. 2007.Applicant
ST Microelectronics, Power Factor Corrector L6561, Jun. 2004.Applicant
Fairchild Semiconductor, Application Note 42047 Power Factor Correction (PFC) Basics, Rev. 0.9.0 Aug. 19, 2004.Applicant
M. Radecker et al., Application of Single-Transistor Smart-Power IC for Fluorescent Lamp Ballast, Thirty-Fourth Annual Industry Applications Conference IEEE, vol. 1, Oct. 3, 1999-Oct. 7, 1999.Applicant
M. Rico-Secades et al., Low Cost Electronic Ballast for a 36-W Fluorescent Lamp Based on a Current-Mode-Controlled Boost Inverter for a 120-V DC Bus Power Distribution, IEEE Transactions on Power Electronics, vol. 21, No. 4, Jul. 2006.Applicant
Fairchild Semiconductor, FAN4800, Low Start-up Current PFC/PWM Controller Combos, Nov. 2006.Applicant
Fairchild Semiconductor, FAN4810, Power Factor Correction Controller, Sep. 24, 2003.Applicant
Fairchild Semiconductor, FAN4822, ZVS Average Current PFC Controller, Aug, 10, 2001.Applicant
Fairchild Semiconductor, FAN7527B, Power Factor Correction Controller, 2003.Applicant
Fairchild Semiconductor, ML4821, Power Factor Controller, Jun. 19, 2001.Applicant
Freescale Semiconductor, AN1965, Design of Indirect Power Factor Correction Using 56F800/E, Jul. 2005.Applicant
International Search Report for PCT/US2008/051072, mailed Jun. 4, 2008.Applicant
Infineon, CCM-PFC Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM), Version 2.1, Feb. 6, 2007.Applicant
International Rectifier, IRAC1150-300W Demo Board, User's Guide, Rev 3.0, Aug. 2, 2005.Applicant
International Rectifier, Application Note AN-1077,PFC Converter Design with IR1150 One Cycle Control IC, rev. 2.3, Jun. 2005.Applicant
International Rectifier, Data Sheet PD60230 revC, Feb. 5, 2007.Applicant
Lu et al, International Rectifier, Bridgeless PFC Implementation Using One Cycle Control Technique, 2005.Applicant
Linear Technology, LT1248, Power Factor Controller, Apr. 20, 2007.Applicant
On Semiconductor, AND8123/D, Power Factor Correction Stages Operating in Critical Conduction Mode, Sep. 2003.Applicant
On Semiconductor, MC33260, GreenLine Compact Power Factor Controller: Innovative Circuit for Cost Effective Solutions, Sep. 2005.Applicant
On Semiconductor, NCP1605, Enhanced, High Voltage and Efficient Standby Mode, Power Factor Controller, Feb. 2007.Applicant
On Semconductor, NCP1606, Cost Effective Power Factor Controller, Mar. 2007.Applicant
On Semiconductor, NCP1654, Product Review, Power Factor Controller for Compact and Robust, Continuous Conduction Mode Pre-Converters, Mar. 2007.Applicant
Philips, Application Note, 90W Resonant SMPS with TEA1610 SwingChip, AN99011, 1999.Applicant
NXP, TEA1750, GreenChip III SMPS control IC Product Data Sheet, Apr. 6, 2007.Applicant
Renesas, HA16174P/FP, Power Factor Correction Controller IC, Jan. 6, 2006.Applicant
Renesas Technology Releases Industry's First Critical-Conduction-Mode Power Factor Correction Control IC Implementing Interleaved Operation, Dec. 18, 2006.Applicant
Renesas, Application Note R2A20111 EVB, PFC Control IC R2A20111 Evaluation Board, Feb. 2007.Applicant
STMicroelectronics, L6563, Advanced Transition-Mode PFC Controller, Mar. 2007.Applicant
Texas Instruments, Application Note SLUA321, Startup Current Transient of the Leading Edge Triggered PFC Controllers, Jul. 2004.Applicant
Texas Instruments, Application Report, SLUA309A, Avoiding Audible Noise at Light Loads when using Leading Edge Triggered PFC Converters, Sep. 2004.Applicant
Texas Instruments, Application Report SLUA369B, 350-W, Two-Phase Interleaved PFC Pre-Regulator Design Review, Mar. 2007.Applicant
Unitrode, High Power-Factor Preregulator, Oct. 1994.Applicant
Texas Instruments, Transition Mode PFC Controller, SLUS515D, Jul. 2005.Applicant
Unitrode Products From Texas Instruments, Programmable Output Power Factor Preregulator, Dec. 2004.Applicant
Unitrode Products From Texas Instruments, High Performance Power Factor Preregulator, Oct. 2005.Applicant
Texas Instruments, UCC3817 BiCMOS Power Factor Preregulator Evaluation Board User's Guide, Nov. 2002.Applicant
Unitrode, L. Balogh, Design Note UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input Current for PFC Front Ends, SLUA196A, Nov. 2001.Applicant
A. Silva De Morais et al., A High Power Factor Ballast Using a Single Switch with Both Power Stages Integrated, IEEE Transactions on Power Electronics, vol. 21, No. 2, Mar. 2006.Applicant
M. Ponce et al., High-Efficient Integrated Electronic Ballast for Compact Fluorescent Lamps, IEEE Transactions on Power Electronics, vol. 21, No. 2, Mar. 2006.Applicant
A. R. Seidel et al., A Practical Comparison Among High-Power-Factor Electronic Ballasts with Similar Ideas, IEEE Transactions on Industry Applications, vol. 41, No. 6, Nov.-Dec. 2005.Applicant
F. T. Wakabayashi et al., An Improved Design Procedure for LCC Resonant Filter of Dimmable Electronic Ballasts for Fluorescent Lamps, Based on Lamp Model, IEEE Transactions on Power Electronics, vol. 20, No. 2, Sep. 2005.Applicant
J. A. Vilela Jr. et al., An Electronic Ballast with High Power Factor and Low Voltage Stress, IEEE Transactions on Industry Applications, vol. 41, No. 4, Jul./Aug. 2005.Applicant
S. T.S. Lee et al., Use of Saturable Inductor to Improve the Dimming Characteristics of Frequency-Controlled Dimmable Electronic Ballasts, IEEE Transactions on Power Electronics, vol. 19, No. 6, Nov. 2004.Applicant
M. K. Kazimierczuk et al., Electronic Ballast for Fluorescent Lamps, IEEETransactions on Power Electronics, vol. 8, No. 4, Oct. 1993.Applicant
S. Ben-Yaakov et al., Statics and Dynamics of Fluorescent Lamps Operating at High Frequency: Modeling and Simulation, IEEE Transactions on Industry Applications, vol. 38, No. 6, Nov.-Dec. 2002.Applicant
H. L. Cheng et al., A Novel Single-Stage High-Power-Factor Electronic Ballast with Symmetrical Topology, IEEE Transactions on Power Electronics, vol. 50, No. 4, Aug. 2003.Applicant
J.W.F. Dorleijn et al., Standardisation of the Static Resistances of Fluorescent Lamp Cathodes and New Data for Preheating, Industry Applications Conference, vol. 1, Oct. 13, 2002-Oct. 18, 2002.Applicant
Q. Li et al., An Analysis of the ZVS Two-Inductor Boost Converter under Variable Frequency Operation, IEEE Transactions on Power Electronics, vol. 22, No. 1, Jan. 2007.Applicant
H. Peng et al., Modeling of Quantization Effects in Digitally Controlled DC-DC Converters, IEEE Transactions on Power Electronics, vol. 22, No. 1, Jan. 2007.Applicant
G. Yao et al., Soft Switching Circuit for Interleaved Boost Converters, IEEE Transactions on Power Electronics, vol. 22, No. 1, Jan. 2007.Applicant
C. M. De Oliviera Stein et al., A ZCT Auxiliary Communication Circuit for Interleaved Boost Converters Operating in Critical Conduction Mode, IEEE Transactions on Power Electronics, vol. 17, No. 6, Nov. 2002.Applicant
W. Zhang et al., A New Duty Cycle Control Strategy for Power Factor Correction and FPGA Implementation, IEEE Transactions on Power Electronics, vol. 21, No. 6, Nov. 2006.Applicant
H. Wu et al., Single Phase Three-Level Power Factor Correction Circuit with Passive Lossless Snubber, IEEE Transactions on Power Electronics, vol. 17, No. 2, Mar. 2006.Applicant
O. Garcia et al., High Efficiency PFC Converter to Meet EN61000-3-2 and A14, Proceedings of the 2002 IEEE International Symposium on Industrial Electronics, vol. 3, 2002.Applicant
P. Lee et al., Steady-State Analysis of an Interleaved Boost Converter with Coupled Inductors, IEEE Transactions on Industrial Electronics, vol. 47, No. 4, Aug. 2000.Applicant
D.K.W. Cheng et al., A New Improved Boost Converter with Ripple Free Input Current Using Coupled Inductors, Power Electronics and Variable Speed Drives, Sep. 21-23, 1998.Applicant
B.A. Miwa et al., High Efficiency Power Factor Correction Using Interleaved Techniques, Applied Power Electronics Conference and Exposition, Seventh Annual Conference Proceedings, Feb. 23-27,1992.Applicant
Z. Lai et al., A Family of Power-Factor-Correction Controllers, Twelfth Annual Applied Power Electronics Conference and Exposition, vol. 1, Feb. 23, 1997-Feb. 27, 1997.Applicant
L. Balogh et al., Power-Factor Correction with Interleaved Boost Converters in Continuous-Inductor-Current Mode, Eighth Annual Applied Power Electronics Conference and Exposition, 1993. APEC '93. Conference Proceedings, Mar. 7, 1993-Mar. 11, 1993.Applicant
Fairchild Semiconductor, Application Note 42030, Theory and Application of the ML4821 Average Current Mode PFC Controller, Oct. 25, 2000.Applicant
Unitrode Products From Texas Instruments, BiCMOS Power Factor Preregulator, Feb. 2006.Applicant
D. Hausman, Lutron, RTISS-TE Operation, Real-Time Illumination Stability Systems for Trailing-Edge (Reverse Phase Control) Dimmers, v. 1.0 Dec. 2004.Applicant
International Rectifier, Data Sheet No. PD60230 revC, IR1150(S)(PbF), uPFC One Cycle Control PFC IC Feb. 5, 2007.Applicant
Texas Instruments, Application Report SLUA308, UCC3817 Current Sense Transformer Evaluation, Feb. 2004.Applicant
Texas Instruments, Application Report SPRA902A, Average Current Mode Controlled Power Factor Correctiom Converter using TMS320LF2407A, Jul. 2005.Applicant
Unitrode, Design Note DN-39E, Optimizing Performance in UC3854 Power Factor Correction Applications, Nov. 1994.Applicant
Fairchild Semiconductor, Application Note 42030, Theory and Application of the ML4821 Average Currrent Mode PFC Controller, Aug. 1997.Applicant
Fairchild Semiconductor, Application Note AN4121, Design of Power Factor Correction Circuit Using FAN7527B, Rev.1.0.1, May 30, 2002.Applicant
Fairchild Semiconductor, Application Note 6004, 500W Power-Factor-Corrected (PFC) Converter Design with FAN4810, Rev. 1.0.1, Oct. 31, 2003.Applicant
Fairchild Semiconductor, FAN4822, ZVA Average Current PFC Controller, Rev. 1.0.1 Aug. 10, 2001.Applicant
Fairchild Semiconductor, ML4821, Power Factor Controller, Rev. 1.0.2, Jun. 19, 2001.Applicant
Fairchild Semiconductor, ML4812, Power Factor Controller, Rev. 1.0.4, May 31, 2001.Applicant
Linear Technology, 100 Watt LED Driver, undated.Applicant
Fairchild Semiconductor, FAN7544, Simple Ballast Controller, Rev. 1.0.0.Applicant
Fairchild Semiconductor, FAN7532, Ballast Controller, Rev. 1.0.2.Applicant
Fairchild Semiconductor, FAN7711, Ballast Control IC, Rev. 1.0.2.Applicant
Fairchild Semiconductor, KA7541, Simple Ballast Controller, Rev. 1.0.3.Applicant
St Microelectronics, L6574, CFL/TL Ballast Driver Preheat and Dimming, Sep. 2003.Applicant
St Microelectronics, AN993, Application Note, Electronic Ballast with PFC Using L6574 and L6561, May 2004.Applicant
International Search Report and Written Opinion for PCT/US2008/062384 dated Jan. 14, 2008.Applicant
S. Dunlap et al., Design of Delta-Sigma Modulated Switching Power Supply, Circuits & Systems, Proceedings of the 1998 IEEE International Symposium, 1998.Applicant
Power Integrations, Inc., “TOP200-4/14 TOPSwitch Family Three-terminal Off-line PWM Switch”, XP-002524650, Jul. 1996, Sunnyvale, California.Applicant
Texas Instruments, SLOS318F, “High-Speed, Low Noise, Fully-Differential I/O Amplifiers,” THS4130 and THS4131, US, Jan. 2006.Applicant
Prodic, A. et al, “Dead Zone Digital Controller for Improved Dynamic Response of Power Factor Preregulators,” IEEE, 2003.Applicant
International Search Report and Written Opinion, PCT US200900032358, dated Jan. 29, 2009.Applicant
Hirota, Atsushi et al, “Analysis of Single Switch Delta-Sigma Modulated Pulse Space Modulation PFC Converter Effectively Using Switching Power Device,” IEEE, US, 2002.Applicant
Prodic, Aleksandar, “Digital Controller for High-Frequency Rectifiers with Power Factor Correction Suitable for On-Chip Implementation,” IEEE, US, 2007.Applicant
International Search Report and Written Opinion, PCT US20080062378, dated Feb. 5, 2008.Applicant
International Search Report and Written Opinion, PCT US20090032351, dated Jan. 29, 2009.Applicant
Erickson, Robert W. et al, “Fundamentals of Power Electronics,” Second Edition, Chapter 6, Boulder, CO, 2001.Applicant
Allegro Microsystems, A1442, “Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and Soft-Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection,” Worcester MA, 2009.Applicant
Texas Instruments, SLUS828B, “8-Pin Continuous Conduction Mode (CCM) PFC Controller”, UCC28019A, US, revised Apr. 2009.Applicant
Analog Devices, “120 kHz Bandwidth, Low Distortion, Isolation Amplifier”, AD215, Norwood, MA, 1996.Applicant
Burr-Brown, IS0120 and IS0121, “Precision Los Cost Isolation Amplifier,” Tucson AZ, Mar. 1992.Applicant
Burr-Brown, ISO130, “High IMR, Low Cost Isolation Amplifier,” SBOS220, US, Oct. 2001.Applicant
International Search Report and Written Report PCT US20080062428 dated Feb. 5, 2008.Applicant
“HV9931 Unity Power Factor LED Lamp Driver, Initial Release”, Supertex Inc., Sunnyvale, CA USA 2005.Applicant
AN-H52 Application Note: “HV9931 Unity Power Factor LED Lamp Driver” Mar. 7, 2007, Supertex Inc., Sunnyvale, CA, USA.Applicant
Spiazzi G et al: “Analysis of a High-Power Factor Electronic Ballast for High Brightness Light Emitting Diodes” Power Electronics Specialists, 2005 IEEE 36th Conference on June 12, 2005, Piscatawa, NJ, USA, IEEE, Jun. 12, 2005, pp. 1494-1499.Applicant
Partial International Search Report PCT/US2008/062387 dated Feb. 5, 2008.Applicant
Written Opinion of the International Searching Authority PCT/US2008/056739 dated Dec. 3, 2008.Applicant
International Search Report PCT/US2008/062387 dated Jan. 10, 2008.Applicant
Data Sheet LT3496 Triple Output LED Driver, Linear Technology Corporation, Milpitas, CA 2007.Applicant
Linear Technology, News Release,Triple Output LED, LT3496, Linear Technology, Milpitas, CA, May 24, 2007.Applicant
Linear Technology, “Single Switch PWM Controller with Auxiliary Boost Converter,” LT1950 Datasheet, Linear Technology, Inc. Milpitas, CA, 2003.Applicant
Yu, Zhenyu, 3.3V DSP for Digital Motor Control, Texas Instruments, Application Report SPRA550 dated Jun. 1999.Applicant
International Rectifier, Data Sheet No. PD60143-O, Current Sensing Single Channel Driver, El Segundo, CA, dated Sep. 8, 2004.Applicant
Balogh, Laszlo, “Design and Application Guide for High Speed MOSFET Gate Drive Circuits” [Online] 2001, Texas Instruments, Inc., SEM-1400, Unitrode Power Supply Design Seminar, Topic II, TI literature No. SLUP133, XP002552367, Retrieved from the Internet: URL:htt/://focus.ti.com/lit/ml/slup169/slup169.pdf.Applicant
PCT US2008/062387 Notification of International Preliminary Report on Patentability and Written Opinion dated Nov. 12, 2009.Applicant
ST Datasheet L6562, Transition-Mode PFC Controller, 2005, STMicroelectronics, Geneva, Switzerland.Applicant
Maksimovic, Regan Zane and Robert Erickson, Impact of Digital Control in Power Electronics, Proceedings of 2004 International Symposium on Power Semiconductor Devices & Ics, Kitakyushu Apr. 5, 2010, Colorado Power Electronics Center, ECE Department, University of Colorado, Boulder, CO.Applicant
Mamano, Bob, “Current Sensing Solutions for Power Supply Designers”, Unitrode Seminar Notes SEM1200, 1999.Applicant
http://toolbarpdf.com/docs/functions-and-features-of-inverters.html printed on Jan. 20, 2011.Applicant

Abstract

Description

Cross-Reference to Related Application

Background of the Invention

[0002] 1. Field of the Invention

[0003] The present invention relates in general to the field of signal processing, and more specifically, to power factor correction and a power factor correction controller with feedback reduction.

[0004] 2. Description of the Related Art

Summary of the Invention

- [0011] (a) determine at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;
- [0012] (b) provide a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;
- [0013] (c1) wherein, if the line input voltage is determined in (a), the PFC controller is further configured to determine the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval; and
- [0014] (c2) wherein, if the output voltage of the switching power converter is determined in (a), the PFC controller is further configured to determine the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

- [0018] (a) determining at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;
- [0019] (b) providing a control signal to the switch such that during each period of the switch the switching power converter responds to the control signal and current ramps-up in the inductor for a first time interval when the switch conducts and ramps-down in the inductor for an inductor flyback time interval when the switch is nonconductive;
- [0020] (c1) wherein, if the line input voltage is determined in (a), determining the output voltage of the switching power converter using the line input voltage, the inductor flyback time interval, and the first time interval; and
- [0021] (c2) wherein, if the output voltage of the switching power converter is determined in (a), determining the line input voltage using the output voltage, the inductor flyback time interval, and the first time interval.

Brief Description of the Drawings

[0025] FIG. 1 (labeled prior art) depicts a power control system with power factor correction and output voltage regulation.

[0026] FIG. 1A depicts a power control system with a single feedback signal to determine a line input voltage and an output voltage.

[0027] FIG. 2 depicts an embodiment of the power control system of FIG. 1A.

[0028] FIG. 3 depicts a power factor correction and output voltage regulation process.

[0029] FIGS. 4 and 5 depict sensor/converters.

[0030] FIG. 6 depicts a time domain graph of a voltage feedback signal, an inductor current i_L, and corresponding states of a switching power converter switch.

[0031] FIG. 7 depicts an inductor flyback time interval determination module.

[0032] FIG. 8 depicts a PFC and output voltage controller.

[0033] FIG. 9 depicts an embodiment of the power control system of FIG. 1A.

[0034] FIG. 10 depicts a graph of a feedback signal and corresponding ideal and actual gate voltages and actual currents of a switching power converter switch.

[0035] FIG. 11 depicts an inductor flyback time interval determination module.

[0036] FIG. 12 depicts an embodiment of the power control system of FIG. 1A.

[0037] FIG. 13 depicts an inductor flyback time interval determination module.

[0038] FIG. 14 depicts an embodiment of the power control system of FIG. 1A that includes a redundancy and reliability module.

Detailed Description

[0058]

\begin{matrix} V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2} . & Equation [1] \end{matrix}

[0059] If operation 304 determines the output voltage V_c(t), in at least one embodiment, operation 308 determines the line input voltage V_x(t) in accordance with Equation [2]:

[0060]

\begin{matrix} V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)} . & Equation [2] \end{matrix}

[0071] Operations 308-312 are performed by PFC and output voltage controller 904 as described in conjunction with PFC and output voltage controller 202.

[0077]

\begin{matrix} V_{P} (t) = - V_{S} (t) \cdot \frac{n_{S}}{n_{P}} = - V_{S} (t) \cdot k . & Equation [3] \end{matrix}

[0080] Operations 308-312 are performed by PFC and output voltage controller 1204 as described in conjunction with PFC and output voltage controller 202.

Claims

What is claimed is:

an input to receive a feedback signal from the switching power converter;

wherein the PFC controller is configured to cause the switching power converter to operate in discontinuous conduction mode and is further configured to:

(a) determine at least one of: (i) a line input voltage and (ii) an output voltage of the switching power converter from the feedback signal;

2. The PFC controller of claim 1 wherein the PFC controller is configured to determine the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

3. The PFC controller of claim 1 wherein the PFC controller is configured to determine the line input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}

wherein T1 is the first time interval, T2 is the inductor flyback time interval, V_cis the output voltage, and V_xis the line input voltage.

5. The PFC controller of claim 1 wherein, during operation of the PFC controller and the switching power converter, a sensor senses the line input voltage across the inductor.

6. The PFC controller of claim 5 wherein the sensor further comprises a secondary winding magnetically coupled to the inductor to sense the voltage across the inductor.

9. The PFC controller of claim 1 wherein:

if the input voltage of the switching power converter is determined in (a), the PFC controller is configured to determine the output voltage of the switching power converter in accordance with:

V_{C} = V_{X} \cdot \frac{(T 1 + T 2)}{T 2},

if the output voltage of the switching power converter is determined in (a), the PFC controller is configured to determine the line input voltage of the switching power converter in accordance with:

V_{X} = V_{C} \cdot \frac{T 2}{(T 1 + T 2)}