On-chip temperature sensor

[0001] This application is a Continuation of U.S. application Ser. No. 11/891,949, titled “ON-CHIP TEMPERATURE SENSOR” filed Aug. 14, 2007, now U.S. Pat. No. 7,630,265 (Allowed) that claims priority to Italian Patent Application Serial No. RM2006A000675, filed Dec. 14, 2006, entitled “ON-CHIP TEMPERATURE SENSOR,” all of which are commonly assigned and incorporated herein by reference.

[0002] Embodiments of the present invention relate generally to temperature sensing and more particularly to temperature sensing in an integrated circuit.

[0003] It is sometimes desirable to know the internal temperature of integrated circuits. The integrated circuit temperature can be used to improve circuit operation by compensating signals that change from nominal operation when the chip temperature changes.

[0004] For example, in a non-volatile memory device such as a NAND flash memory, programming and reading memory cell data requires various voltages for programming the cell to a desired threshold voltage and then applying that threshold voltage to the cell to determine if the cell turns on and conducts. If the cell does not turn on, it has not been programmed to the desired threshold.

[0005] During operation of the integrated circuit, the temperature varies both due to ambient temperature, as well as to the electrical operation of the integrated circuit, causing a temperature increase. The temperature change can cause a change in the operating characteristics of the memory cell. For example, a threshold voltage of 1V at room temperature may turn into a threshold voltage of 900 mV as the chip temperature increases. The change in voltage levels can have an impact on reading, programming, and verifying operations that are expecting a certain voltage.

[0006] Temperature change in a dynamic random access memory (DRAM) device can also have an impact on memory operation. A DRAM requires periodic refresh cycles in order to maintain the integrity of the data stored in the memory. The temperature of the memory device affects the frequency at which the memory device needs to be refreshed. As the device heats up, the cells lose their ability to hold a charge due to current leakage. Therefore, the warmer the device the more often it has to be refreshed.

[0007] Designers typically take into account the worst case requirement for refreshing a DRAM and design the memory to refresh at a fixed rate consistent with the maximum operating temperature of the part. However, the faster refresh rate is not required when the device is operating at a cooler temperature, thus wasting power. It would therefore be beneficial to be able to determine the memory device's internal temperature in order to adjust the refresh rate in response to changing temperature.

[0008] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for temperature sensing in an integrated circuit.

[0019] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments is defined only by the appended claims and equivalents thereof.

[0020] FIG. 1 illustrates a block diagram of one embodiment of a temperature sensing circuit 100. The circuit is comprised of a reference voltage generator circuit 101 that outputs a temperature invariant voltage V_bg and a temperature variant value F(T). The temperature variant value F(T) is a physical quantity (e.g., a voltage or a current) having a linear temperature coefficient.

[0021] In one embodiment, the reference voltage generator circuit 101 is a band-gap voltage reference circuit. FIG. 2 illustrates one such band-gap voltage reference circuit that is described subsequently in greater detail.

[0022] The temperature independent voltage V_bg is input to an amplifier 103 that outputs a reference voltage V_ref that is optimized for other parts of the circuit 100. In one embodiment, V_bg is in the range of 1.12V to 1.25V and the amplifier 103 provides a gain factor, G, of 1.12 to output a V_ref voltage of 1.4V. Alternate embodiments can use other voltages.

[0023] The amplifier 103 also provides a buffer function between the reference voltage generator circuit 101 and the level generator circuit 107. The amplifier 103 electrically isolates the circuitry of the band-gap reference circuit 101 from the level generation circuit 107.

[0024] The level generation circuit 107 divides the temperature invariant V_ref voltage from the amplifier 103 (e.g., 1.4V) into 2ⁿ−1 voltage levels through taps on a series of resistors. One embodiment of the level generation circuit 107 is illustrated in greater detail in FIG. 4 and is described subsequently.

[0025] A temperature sensor circuit 105 is coupled to the physical quantity F(T) that is output from the reference voltage generator. One embodiment of a temperature sensor 105 is illustrated in greater detail in FIG. 3 and described subsequently.

[0026] The temperature sensor 105 generates a voltage, V₀(T), that is linearly dependent on the temperature starting from the physical quantity F(T). This voltage at 0 Kelvin is 0V while the slope of V₀(T) is determined by a digital control referred to in FIG. 1 as slope adjust.

[0027] The slope adjust input is a digital correction factor that is determined during testing and calibration phase of the integrated circuit manufacturing process. The slope adjust corrects each individual die for the variations that occur between dies during manufacturing so that all of the dies have a uniform operation.

[0028] The slope adjust is determined by inputting a known physical quantity F(T) to the temperature sensor 105 at a certain operating temperature. A known V₀(T) is expected at the output. If the expected V₀(T) is not output by the sensor, the required slope adjust is determined that would generate the desired V₀(T) level. The slope adjust is input to the temperature sensor 105 and stored in memory in the integrated circuit for future use.

[0029] An analog-to-digital converter (ADC) 109, or other comparison circuit, compares the V₀(T) signal with the 2ⁿ−1 voltage levels and generates an n-bit digital output that is proportional to the actual temperature. The ADC 109 determines to which of the 2ⁿ−1 levels V₀(T) is closest.

[0030] The ADC 109 can be a comparison circuit that is comprised of one of many different architectures. One embodiment is a flash ADC comprising 2ⁿ−1 comparators with outputs coupled to a decoder that provides the binary output. Another embodiment can be a linear ramp ADC that uses a comparator coupled to an n-bit counter that provides the output. Still another ADC includes a successive approximation ADC that uses a comparator coupled to an n-bit successive approximation register.

[0031] As an example of operation of the temperature sensing circuit 100 of FIG. 1, FIG. 6 illustrates a flowchart of one embodiment of a method for measuring the temperature of an integrated circuit. The method begins by generating the temperature invariant voltage, V_bg, and the temperature variant physical quantity, F(T), in response to the temperature of the integrated circuit 601.

[0032] The amplifier provides a gain factor to V_bg to increase the approximately 1.12-1.25V output from the reference voltage generator to 1.4V. This is input to the level generator circuit that generates a plurality of levels 603 in response to the temperature invariant voltage. The temperature sensor circuit generates a temperature variant voltage V₀(T) in response to F(T) 605.

[0033] The ADC compares the temperature variant voltage to the 2ⁿ−1 voltage levels to determine which level is closest 607. For example, if V₀(T) is closes to the third level, n=2 is output from the ADC 109 since 2²−1=3 (third level). The ADC then outputs the n-bit voltage level 609 in response to this comparison. An integrated circuit controller circuit reads this n-bit value and determines the temperature or temperature range of the integrated circuit 611 from a look-up table stored in memory. The greater the quantity of bits generated by the ADC, the greater the granularity possible in determining the integrated circuit temperature.

[0034] FIG. 2 illustrates one embodiment of a reference voltage generator circuit 101. This circuit 101 is a band-gap voltage reference circuit. The temperature invariant voltage, V_bg, is obtained by adding two voltages in the circuit: the base-emitter voltage (V_be) across the PMOS transistor 203 and the voltage drop across the resistor 205 that is coupled to the V_bg output.

[0035] The bipolar transistors 207, 209 have area N and 1 respectively, where N>1. Area N is conventionally obtained by multiple placements of transistors of area 1. Increasing N has the effect of modifying the current amplification.

[0036] The PMOS transistors 201, 203 are equal in size and symmetrical in layout. Since the PMOS transistors 201, 203 are arranged in a current mirror configuration, the currents I₁ and I₂ are substantially equal. From basic silicon junction diode equations, the forward current I_b of the base-emitter diode of a bipolar transistor 207, 209 is I_b2=I₀e^Vbe/Vt where I₀ is the diode saturation current, proportional to the base-emitter area; V_be is the base-emitter voltage; and V_t is kT/q (k=Boltzmann constant; T=absolute temperature; q=electron charge).

[0037] Since the base-emitter area of the bipolar transistor 207 is N times greater than the base-emitter area of the other bipolar transistor 209, I_b1=NI₀e^{(Vbe−Ve)/Vt}. The collector currents, I_c1 and I_c2, are: I_c1=β₁I_b1 and I_c2=β₂I_b2; where β₁ and β₂ are the current gains (h_FE) of the bipolar transistors 207, 209.

[0038] From Kirchoff's first law as applied to the collector node of the bipolar transistor 209, I₂=I_c2+I_b1+I_b2. Assuming β₁ and β₂ being large, I_b1 and I_b2 can be ignored in an approximation. Therefore, I_c2=I₂ and I_c1=I₁ and I_c2=I_c1.

[0039] Considering if β₁=β₂, I_b2=I_b1 is obtained. Thus, from the above equations, it can be seen that: NI₀e^{(Vbe−Ve)/Vt}=I₀e^Vbe/Vt. From simple calculations, this becomes V_e=V_t ln(N)=kT ln(N)/q. The voltage V_e is typically referred to as ΔV_be and has the same expression as most band-gap reference architectures. By construction, V_bg=V_be+R₂I₂ and I₁=V_e/R₁. Therefore, I₂=V_e/R₁. From these equations it can be seen that V_bg=V_be+R₂kT ln(N)/R₁q.

[0040] It is well known in the art that ∂V_be/∂T is approximately −2 mV/° C. It is possible to have ∂V_bg/∂T=0. By proper selection of resistor R₂ 205, N, and resistor R₁ 211: −∂V_be/∂T=(R₂/R₁)k ln(N)/q. The second term in this equation is the slope of the voltage across resistor R₂ 205 versus temperature T. Another way to write the second term of this equation is (R₂/R₁)ΔV_be. The quantity I₁=I_ptat is proportional to absolute temperature. With respect to FIG. 1, it is possible to write F(T) as:

[0041] $F\left(T\right)=I_{\mathrm{ptat}}=\frac{k}{q}*\frac{1}{R_1}*\ln \left(N\right)*T=\mathrm{Hi}*T$

[0042] The band-gap reference circuit 101 of FIG. 2 is for purposes of illustration only. Alternate embodiments such as a Brokaw-cell band-gap reference circuit or other types of reference voltage generator circuits may also be used.

[0043] FIG. 3 illustrates one embodiment of a temperature sensor circuit 105 as used in FIG. 1. This circuit 105 is comprised of a PMOS transistor 301 connected to a resistor 303. The source of the transistor 301 is connected to the supply voltage V_CC node of FIG. 2 and the node between the transistor's drain and the resistor 303 is the output voltage V₀(T). The gate of transistor T3 301 is connected to the same terminal as the gates of transistors T1 201 and T2 203 of the reference voltage generator circuit of FIG. 2.

[0044] In operation, the current through the transistor 301 mirrors the current through the T1 201 and T2 203 transistors of FIG. 2. When substantially the same lengths for the MOS devices 201, 203, and 301 are chosen, the current mirrors are used to multiply the current by a given factor. However, these transistors 201, 203, 301 have different widths so that the ratio of the current that flows through two of these transistors is equal to the width ratio. In other words, the ratio between the current that flows through transistor T3 301 and the current that flows through transistor T2 203 is fixed by their geometry and is subsequently referred to as Hm.

[0045] The temperature sensor 105 of FIG. 3 is used when the physical quantity F(T) output from the reference voltage generator circuit is a current-based quantity. The variation of (R₂/R₁)ΔV_be in the band-gap circuit of FIG. 2 is assigned according to the equation −∂V_be/∂T=(R₂/R₁)k ln(N)/q. Its absolute value can be amplified to adapt it to drive the circuit of FIG. 3.

[0046] In the combination of the temperature sensor circuit 105 of FIG. 3 and the band-gap circuit of FIG. 2, V₀=R₃*I₃ where I₃=Hm*I_ptat (Hm: mirror ratio M₃/M₂). Thus, V₀=Hm*Hi*T=G*T where Hi=(k/q)*ln(N)/R₁ and G is a constant that nominally depends only by three geometric ratios: N, Hm, and R₃/R₁.

[0047] By adjusting the resistance of R₃, it is possible to change the slope of V₀(T). Thus, one embodiment for operation of the slope adjust of FIG. 1 as described previously is to set the value of the resistance of R₃ depending on the desired slope for nominal operation.

[0048] In another embodiment, F(T) is a temperature dependent voltage. In this case, the temperature sensor can use another programmable gain buffer (i.e., gain block G 103 in FIG. 1) to provide the output voltage V₀(T).

[0049] FIG. 4 illustrates one embodiment of a level generation circuit 107. The reference voltage V_ref is divided down into 2ⁿ−1 levels by a plurality of resistors 401-403, where m=2ⁿ, connected as a resistor divider circuit. By assigning the gain G, from the amplifier 103 of FIG. 1, and/or the slope of V₀(T), it ensures that V_ref=V₀(T_max). Using the series of resistors 401-403 with a nominal value of R_a and one resistor with a nominal value of R_b, the voltage levels generated are

[0050] $\mathrm{lev}\left(k\right)=\frac{R_b+kR}{R_b+\left(2^n-2\right)R_a}·V_{\mathrm{ref}}$
The knowledge of the highest level lev(2ⁿ−1)=V_ref and the lowest lev(0)=V₀(T_max), allows the ratio between R_a and R_b to be calculated.

[0051] FIG. 5 illustrates a plot of V₀(T) versus absolute temperature. The 2ⁿ−1 voltage levels are also shown. With the 2ⁿ−1 levels, it is possible to identify 2ⁿ temperature ranges. The amplitude of each temperature range is ΔT=(T_max−T_min)/(2ⁿ−2). The quantity S=V₀(T_max)/T_max is the sensitivity in volts per kelvin. FIGS. 10A and 10B illustrate tables of examples of the execution of these equations.

[0052] FIG. 10A shows the case when T_max=360K, T_min=240K, n=2, and V₀(T_max)=1.8V. In this embodiment, the sensitivity, S, is 5 mV/K and ΔT=60K. FIG. 10B shows the case when T_max=360K, T_min=240K, and n=3. In this embodiment, ΔT=20K.

[0053] During operation of the embodiments of the temperature sensing method, the integrated circuit controller reads the n-bit values illustrated in FIGS. 10A and 10B and uses a look-up table stored in memory to determine the respective temperature range.

[0054] FIG. 7 illustrates one embodiment of an implementation of the temperature sensing device 100. In this embodiment, the temperature sensing device 100 is embedded in a memory device 400. Examples of such a memory device include dynamic random access memory (DRAM) and flash memory. Other embodiments can use other types of memory, volatile or non-volatile, or other types of integrated circuits requiring temperature sensing.

[0055] The embodiment of FIG. 7 includes ROM fuses 701 that store the voltage levels L_i=L₀, L₁, . . . L_n-1. The temperature sensing circuit 100 enables the memory controller circuit 703 to select the L_i value corresponding to the temperature T_i. The controller circuit 703 determines an operational voltage that is necessary in response to the temperature. This can be accomplished by the controller circuit 703 accessing a look-up table in memory to compare the measured absolute temperature range to an operational voltage associated with that particular temperature range.

[0056] The selected operational voltage is output as the LEV signal to the analog voltage generator 705 of the memory device. The LEV signal is a digital representation of the desired voltage necessary to compensate for the temperature of the memory device.

[0057] The analog voltage generator is comprised of a digital-to-analog converter 710 that converts the digital LEV signal to the analog operational voltage that is needed to compensate the memory array 706 operation based on the integrated circuit temperature. The compensated operational voltages can include voltage for biasing the memory cell word line, the bit line voltage, or some other operational voltage.

[0058] FIG. 8 illustrates a functional block diagram of a memory device 800 that can incorporate embodiments of the temperature sensing device described herein. The memory device 800 is coupled to a controller 810. The controller 810 may be a microprocessor or some other type of controlling circuitry. The memory device 800 and the controller 810 form part of a memory system 820. The memory device 800 has been simplified to focus on features of the memory that are helpful in understanding the present invention. The memory and controller can be discreet devices, separate integrated circuits, a common device or a common integrated circuit.

[0059] The memory device includes an array of memory cells 830 that, in one embodiment, are non-volatile memory cells such as flash memory cells. The memory array 830 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bit lines. As is well known in the art, the connection of the cells to the bit lines depends on whether the array is a NAND architecture, a NOR architecture, an AND architecture, or some other array architecture.

[0060] An address buffer circuit 840 is provided to latch address signals provided over I/O connections 862 through the I/O circuitry 860. Address signals are received and decoded by row decoders 844 and column decoders 846 to access the memory array 830. It will be appreciated by those skilled in the art that, with the benefit of the present description, the number of address input connections and row/column decoders depends on the density and architecture of the memory array 830. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

[0061] The memory integrated circuit 800 reads data in the memory array 830 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 850. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 830. Data input and output buffer circuitry 860 is included for bi-directional data communication over the I/O connections 862 with the processor 810. Write circuitry 855 is provided to write data to the memory array.

[0062] Control circuitry 870 decodes signals provided on control connections 872 from the processor 810. These signals are used to control the operations on the memory array 830, including data read, data write, and erase operations. The control circuitry 870 may be a state machine, a sequencer, or some other type of controller. The control circuitry 870 of the present invention, in one embodiment, is responsible for executing the embodiments of the temperature measuring method.

[0063] The flash memory device illustrated in FIG. 8 has been simplified to facilitate a basic understanding of the features of the memory and is for purposes of illustration only. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. Other embodiments may include the flash memory cell of the present invention in other types of electronic systems.

[0064] FIG. 9 is an illustration of a memory module 900 that incorporates the temperature sensing embodiments as discussed previously. Although the memory module 900 is illustrated as a memory card, the concepts discussed with reference to memory module 900 are applicable to other types of removable or portable memory, e.g., USB flash drives. In addition, although one example form factor is depicted in FIG. 9, these concepts are applicable to other form factors as well.

[0065] The memory module 900 includes a housing 905 to enclose one or more memory devices 910 of the present invention. The housing 905 includes one or more contacts 915 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiment, the contacts 915 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 915 might be in the form of a USB Type-A male connector. In general, however, contacts 915 provide an interface for passing control, address and/or data signals between the memory module 900 and a host having compatible receptors for the contacts 915.

[0066] The memory module 900 may optionally include additional circuitry 920. For some embodiments, the additional circuitry 920 may include a memory controller for controlling access across multiple memory devices 910 and/or for providing a translation layer between an external host and a memory device 910. For example, there may not be a one-to-one correspondence between the number of contacts 915 and a number of I/O connections to the one or more memory devices 910. Thus, a memory controller could selectively couple an I/O connection (not shown in FIG. 9) of a memory device 910 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 915 at the appropriate time. Similarly, the communication protocol between a host and the memory module 900 may be different than what is required for access of a memory device 910. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 910. Such translation may further include changes in signal voltage levels in addition to command sequences.

[0067] The additional circuitry 920 may further include functionality unrelated to control of a memory device 910. The additional circuitry 920 may include circuitry to restrict read or write access to the memory module 900, such as password protection, biometrics or the like. The additional circuitry 920 may include circuitry to indicate a status of the memory module 900. For example, the additional circuitry 920 may include functionality to determine whether power is being supplied to the memory module 900 and whether the memory module 900 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 920 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 900.

[0068] The embodiments of the present invention provide a temperature sensing circuit that can be embedded in an integrated circuit such as a memory device. The temperature sensing device generates an n-bit value that is an indication of the temperature of the memory device or other integrated circuit. This value can be read by a controller circuit to provide a temperature or temperature range indicative of the n-bit value.

[0069] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.