Temperature compensation of memory signals using digital signals

[0001] This application claims priority to Italian Patent Application Serial No. RM2006A000652, filed Dec. 6, 2006, entitled “TEMPERATURE COMPENSATION OF MEMORY SIGNALS USING DIGITAL SIGNALS,” which is commonly assigned.

[0002] The embodiments of the present invention relate generally to temperature sensing and more particularly to temperature sensing in a memory device.

[0003] It is sometimes desirable to know the internal temperature of integrated circuits. The integrated circuit temperature can be used to improve circuit operation by compensating signals that change from nominal operation when the chip temperature changes.

[0004] A memory device, such as a NAND flash memory, requires various voltages for programming and reading memory cell data. Programming a cell includes biasing the cell control gate with a programming voltage until the cell is at a desired threshold voltage. The cell is verified with a sense amplifier by applying that threshold voltage to the cell to determine if the cell turns on and conducts. If the cell does not turn on, it has not been programmed to the desired threshold.

[0005] During operation of an integrated circuit, the temperature varies due to both ambient temperature as well as the electrical operation of the integrated circuit. The temperature change can cause a change in the nominal operating characteristics of a memory cell. For example, a threshold voltage of 1V at room temperature may turn into a threshold voltage of 900 mV as the chip temperature increases. The change in voltage levels can have an impact on reading, programming, and verifying operations that are expecting a certain voltage.

[0006] For example, FIG. 1 illustrates a plot of a threshold voltage distribution, V_t. This graph shows typical effects of temperature on the V_t distribution.

[0007] The dependence of the decision edge of a sense amplifier on the temperature affects the distribution width of the V_t through the spread of the program verify operation. The program verify operation may be performed at different temperatures such as T1 and T2. If the program algorithm provides a distribution width W, a programming algorithm performed at temperature T1 results in the first distribution 101 that is W wide and starts at pgm_vfy1. If the programming algorithm performs at temperature T2, a second distribution 103 that is W wide starts at pgm_vfy2. The total distribution 104 after the two program operations will be a distribution 104 that is D wide where W_tot≧W+pgm_vfy2−pgm_vfy1. FIG. 1 illustrates the program verify spread 106 resulting from pgm_vfy2−pgm_vfy1.

[0008] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for temperature compensation of signals in an integrated circuit.

[0015] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments is defined only by the appended claims and equivalents thereof.

[0016] FIG. 2 illustrates a block diagram of one embodiment of a temperature compensation circuit 200 in a memory device. In one embodiment, the memory device is a NAND flash memory. However, the present embodiments are not limited to any one type of memory. Any type of non-volatile memory or volatile memory can be substituted for the NAND flash memory including NOR flash memory and dynamic random access memory (DRAM).

[0017] The temperature sensor circuit 203 generates a digital representation, T, of the temperature of the integrated circuit. The digital representation may be an actual temperature of the integrated circuit or a digital signal that is proportional to the temperature that can then be used by other circuits as an indication of the temperature.

[0018] The temperature sensor circuit 203 encompasses any type of temperature sensor. For example, a thermistor varies its resistance in response to temperature changes. An analog-to-digital circuit would then change the analog resistance to a digital representation of the temperature. The embodiments of the present invention are not limited to any one temperature sensor circuit.

[0019] The logic circuit 210 reads the temperature representation from the temperature sensor 203. The logic circuit 210 is comprised of a controller circuit 201 and a parameter calculation block 202.

[0020] The controller circuit 201 can be the controller of the memory device such as a state machine that controls the memory operations (i.e., program, erase, read) of the memory device. Alternate embodiments may use a controller circuit that is dedicated to the temperature compensation control operation.

[0021] The parameter calculation block 202 is comprised of a hardware circuit, a software module, or a combination of the two. This block 202 is responsible for generating the compensation parameters as a function of temperature. In the embodiment of FIG. 2, these digital parameters are the digital representation of the vector of voltages V(q), referred to as xv(T), and the digital representation of the vector of timings t(q), referred to as xt(T). Alternate embodiments may generate additional parameters, depending on the type of memory. The digital words representing the voltage and the timing signals are not limited to any one quantity of bits. The greater the quantity of bits, the greater the granularity for generating the analog voltages and times, respectively.

[0022] In one embodiment, the parameter calculation block 202 includes a look-up table, stored in memory, of the digital representations of the voltages and times required for different temperatures and memory operations (i.e., programming, erasing, reading). For example, the table can have columns of temperatures and memory functions matched up with their respective word line voltage, bit line voltage, sensing time, and sensing delay time. The table of values is generated during manufacture and testing of the integrated circuit.

[0023] In another embodiment, the look-up table includes voltage/temperature offsets instead of the actual digital voltage/time representations. In still another embodiment, the parameter calculation block 202 dynamically generates appropriate voltages and times, as a function of the temperature, with an algorithm.

[0024] A voltage generation circuit 205 generates the temperature compensated voltages in response to the digital signal xv(T). These voltages are illustrated generically as V(xv). In one embodiment, the voltage generation circuit 205 generates the word line voltage, V_wl(xv). Alternate embodiments can generate other voltages necessary for temperature compensated operation of a memory array and sense amplifier 206. These voltages can include the bit line sense voltage and the bit line precharge voltage.

[0025] FIG. 3 illustrates one embodiment of a voltage generation circuit 205. In this embodiment, the circuit is a digital-to-analog converter 302 that generates an analog voltage output as a function of the digital word input xv(T). The analog voltage is generated from a temperature invariant reference voltage V_ref. One embodiment generates the reference voltage from a band-gap voltage reference circuit 301. The digital-to-analog converter 302 can output a voltage in the range of 0V to V_ref, depending on the digital word input.

[0026] The analog voltage generated by the digital-to-analog converter 302 is input to a voltage regulator circuit having an operational amplifier 304 and a voltage pump 303. The regulated output voltage, V(xv), of the voltage pump 303 is in the range of 0V to V_out—max. The resistor divider made up of resistors R1 305 and R2 306 translate the range of V(xv) into the range of the digital-to-analog converter. In other words, V_out—max*R2/(R1+R2)=V_ref.

[0027] A timing generation circuit 204 generates the temperature compensated timing signals (i.e., sense time−t_sense) for the memory array and sense amplifier 206 in response to the multiple bit digital representation of the timing xt(T). The sense time, t_sense, in a non-volatile memory device, is the time between the start and end of the memory cell discharge to the bit line.

[0028] The multiple bit word, xt(T) is generated by the logic block 210 according to the temperature T. For example, if at 90° C. the sensing time is 5 μs and four bits are used to linearly code the sensing time from 0 to 16 μs, then xt(90° C.)=0101 (binary) and the time between the timing signal t(0101) will have the time between the start and end discharge pulses equal to 5 μs.

[0029] The output of the timing generation block 204, t_sense=t(xt), is a logic signal comprising a set of pulses indicating the starting and ending times of the time period necessary for the cell to discharge the bit line. The pulses are separated by the time xt. The timing generation block 204, in combination with the logic block 210, thus uses the digital representation of the temperature to calculate the digital representation of the sensing time needed to compensate the temperature effect on the sensing circuit.

[0030] The present embodiments are not limited to any one method for generating t(xt). These methods can include using a digital counter with a clock reference, a monostable circuit trimmed by xt, or a dedicated routine in the controller circuit 201.

[0031] The memory array and sense amplifier circuit block 206 includes the memory cells that are arranged in an array fashion. Word lines are coupled to the control gates of rows of memory cells and bit lines are coupled to the columns of memory cells.

[0032] The bit lines are coupled to the sense amplifiers so that, after the control gate of an addressed cell is biased during a verify/read operation, its current is sensed on the bit line for the time period t_sense. The sensing operation determines the state of the cell.

[0033] FIG. 4 illustrates a flow chart of one embodiment of a method for adjusting the voltage and/or timing of memory operation signals in response to temperature changes of the integrated circuit. This method refers to the block diagram of FIG. 2.

[0034] A digital indication of the temperature T, such as the actual temperature or a proportional indication, is read from the temperature sensor 401. The memory operation to be performed (i.e., erase, program, read) is then determined 403.

[0035] It is desirable to know the memory operation to be performed since different operations require different word line and bit line voltages as well as different timing requirements. Therefore, the parameter calculation block 202 of FIG. 2 needs this information to determine which digital representations of the voltage and timing to generate.

[0036] The parameter calculation block 202 then generates the digital representation of the voltage 405 as a function of temperature and based on the memory operation to be performed. The parameter calculation block 202 can also generate the digital representation of the memory operation timing as a function of temperature and based on the memory operation to be performed.

[0037] The analog voltage for the memory operation is then generated based on the digital representation 407. If the embodiment includes generating the memory operation timing, the timing signals are generated as well 407.

[0038] FIG. 5 illustrates a functional block diagram of a memory device 500 that can incorporate embodiments of the temperature compensation described herein. The memory device 500 is coupled to a controller 510. The controller 510 may be a microprocessor or some other type of controlling circuitry. The memory device 500 and the controller 510 form part of a memory system 520. The memory device 500 has been simplified to focus on features of the memory that are helpful in understanding the present invention. The memory and controller can be discreet devices, separate integrated circuits, a common device or a common integrated circuit.

[0039] The memory device includes an array of memory cells 530 that, in one embodiment, are non-volatile memory cells such as flash memory cells. The memory array 530 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bit lines. As is well known in the art, the connection of the cells to the bit lines depends on whether the array is a NAND architecture, a NOR architecture, an AND architecture, or some other array architecture.

[0040] An address buffer circuit 540 is provided to latch address signals provided over I/O connections 562 through the I/O circuitry 560. Address signals are received and decoded by row decoders 544 and column decoders 546 to access the memory array 530. It will be appreciated by those skilled in the art that, with the benefit of the present description, the number of address input connections and row/column decoders depends on the density and architecture of the memory array 530. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

[0041] The memory integrated circuit 500 reads data in the memory array 530 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 550. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 530. Data input and output buffer circuitry 560 is included for bi-directional data communication over the I/O connections 562 with the processor 510. Write circuitry 555 is provided to write data to the memory array.

[0042] Control circuitry 570 decodes signals provided on control connections 572 from the processor 510. These signals are used to control the operations on the memory array 530, including data read, data write, and erase operations. The control circuitry 570 may be a state machine, a sequencer, or some other type of controller. The control circuitry 570 of the present invention, in one embodiment, is responsible for executing the embodiments of the temperature compensation method.

[0043] The temperature compensation circuit 200 of FIG. 2 is shown coupled to the control circuitry 570. In another embodiment, this control circuitry 570 can be included in the temperature compensation circuit block 200.

[0044] The flash memory device illustrated in FIG. 5 has been simplified to facilitate a basic understanding of the features of the memory and is for purposes of illustration only. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. Alternate embodiments may include the flash memory cell of the present invention in other types of electronic systems.

[0045] FIG. 6 is an illustration of a memory module 600 that incorporates the temperature compensation embodiments as discussed previously. Although the memory module 600 is illustrated as a memory card, the concepts discussed with reference to the memory module 600 are applicable to other types of removable or portable memory, e.g., USB flash drives. In addition, although one example form factor is depicted in FIG. 6, these concepts are applicable to other form factors as well.

[0046] The memory module 600 includes a housing 605 to enclose one or more memory devices 610 of the present invention. The housing 605 includes one or more contacts 615 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiment, the contacts 615 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 615 might be in the form of a USB Type-A male connector. In general, however, contacts 615 provide an interface for passing control, address and/or data signals between the memory module 600 and a host having compatible receptors for the contacts 615.

[0047] The memory module 600 may optionally include additional circuitry 620. For some embodiments, the additional circuitry 620 may include a memory controller for controlling access across multiple memory devices 610 and/or for providing a translation layer between an external host and a memory device 610. For example, there may not be a one-to-one correspondence between the number of contacts 615 and a number of I/O connections to the one or more memory devices 610. Thus, a memory controller could selectively couple an I/O connection (not shown in FIG. 6) of a memory device 610 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 615 at the appropriate time. Similarly, the communication protocol between a host and the memory module 600 may be different than what is required for access of a memory device 610. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 610. Such translation may further include changes in signal voltage levels in addition to command sequences.

[0048] The additional circuitry 620 may further include functionality unrelated to control of a memory device 610. The additional circuitry 620 may include circuitry to restrict read or write access to the memory module 600, such as password protection, biometrics or the like. The additional circuitry 620 may include circuitry to indicate a status of the memory module 600. For example, the additional circuitry 620 may include functionality to determine whether power is being supplied to the memory module 600 and whether the memory module 600 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 620 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 600.

[0049] The temperature compensation apparatus embodiments provide memory array digitally generate voltages that have been adjusted for temperature. Another embodiment can digitally generate both voltages and timing that have been adjusted for temperature. Still another embodiment can generate only temperature compensated timing signals.

[0050] The word line voltage applied to a memory cell during a sensing operation can be compensated according to the integrated circuit temperature to keep the decision edge of the sense amplifier the same as during nominal temperature operation. This reduces the distribution widths experienced in the prior art operation of FIG. 1 where, if the word line voltage is applied the same at every temperature, the decision edge of the sense amplifier spreads. Additionally, the margin needed between the read and verify operations is reduced by reducing the dependence on temperature of the sensing discrimination.

[0051] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.