Process for fabricating a strained channel MOSFET device

[0001] This application is a divisional of patent application Ser. No. 10/919,684, entitled, “Process For Fabricating a Strained Channel MOSFET Device,” filed on Aug. 17, 2004, now U.S. Pat. No. 7,279,430, which application is incorporated herein by reference.

[0002] The present invention relates generally to methods used to fabricate semiconductor devices and more specifically to a method used to fabricate a metal oxide semiconductor field effect transistor (MOSFET) device comprised with a strained channel region.

[0003] In a continuing effort to increase performance MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for N channel (NMOSFET) or for P channel (PMOSFET) devices. The use of semiconductor alloy layers, such as silicon-germanium or silicon-germanium-carbon, followed by an overlying thin semiconductor layer can result in the overlying semiconductor layer having the desired strain component needed for carrier mobility enhancement. Thus, a strained semiconductor layer overlying a semiconductor alloy layer, underlying a gate structure and surrounded by adjacent source/drain regions, can be used as an attractive configuration for MOSFET devices.

[0004] This configuration can, however, be difficult to process in addition to presenting junction leakage concerns as a result of the blanket semiconductor alloy layer. The epitaxial growth of the semiconductor alloy layer, such as a silicon-germanium layer, can be costly and difficult to accurately control the level of germanium in the epitaxially grown semiconductor alloy layer. In addition, the presence of a blanket semiconductor alloy layer allows an unwanted interface between the source/drain regions to exist, possibly introducing junction leakage.

[0005] Embodiments of the present invention provide a strained channel region for MOSFET, or for complimentary (CMOS) devices, wherein a silicon-germanium region will be formed in a channel region, while reducing or eliminating junction leakage that can result when a blanket silicon-germanium region directly interfaces between source/drain regions. Embodiments of the present invention may also feature a process sequence that allows integration of the process steps used for formation of the semiconductor alloy region and for formation of the MOSFET lightly-doped source/drain (LDD) region.

[0006] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention.

[0007] In accordance with an embodiment of the present invention, a MOSFET device featuring a strained channel region is provided. The MOSFET device includes a gate structure with spacers alongside thereof. Lightly-doped source/drain regions are provided on opposing sides of the gate structure extending below the spacers. Raised silicon shapes comprising germanium are formed on the substrate alongside the spacers, and heavily-doped source/drain regions are located in the substrate below the raised silicon shapes. A semiconductor alloy region is located in the substrate below the gate structure.

[0008] In accordance with another embodiment of the present invention, a MOSFET device featuring a strained channel region is provided. The MOSFET device includes a gate stack with spacers alongside thereof. An alloy region is located below the gate stack extending the length of the channel region. Lightly-doped source/drain regions are provided on opposing sides of the gate stack extending below the spacers. Raised silicon shapes comprising germanium are formed on the substrate alongside the spacers, and heavily-doped source/drain regions are located in the substrate below the raised silicon shapes.

[0009] In accordance with another embodiment of the present invention, a MOSFET device featuring a strained channel region is provided. The MOSFET device includes a gate stack with raised silicon shapes formed on a substantially planar surface of the substrate on opposing sides of the gate stack. Spacers are located between the raised silicon shapes and the gate stack. Lightly-doped source/drain regions are provided on opposing sides of the gate stack extending below the spacers, and heavily-doped source/drain regions are located in the substrate below the raised silicon shapes. An alloy region is located below the gate stack.

[0012] A MOSFET device featuring a strained channel region obtained via pocket implantation of germanium ions in a portion of a semiconductor substrate located underlying the conductive gate structure will now be described in detail. The strained channel region featured in this invention can be applied to either an N channel (NMOSFET), or to a P channel (PMOSFET) device, and for this description will be applied to a complimentary (CMOS) device comprised with both NMOSFET and PMOSFET devices.

[0013] Semiconductor substrate 1, comprised of P-type single crystalline silicon featuring a <100> crystallographic orientation, is used and schematically shown in FIG. 1. Region 2 of semiconductor substrate 1 will be used to accommodate a subsequent NMOSFET device while region 3 of semiconductor substrate 1 will be the location for a PMOSFET device. Isolation region 4, such as an insulator filled shallow trench (STI) region, a thermally grown field oxide (FOX) region, or the like may be formed in an area of semiconductor substrate 1 where physical isolation of the MOSFET regions is desired. The STI region may comprise silicon oxide deposited by chemical vapor deposition (CVD) techniques, while the FOX region may comprise thermally grown silicon dioxide. An N well region, not shown in the drawings, may be formed in a top portion of substrate 1 in region 3 to accommodate a subsequent PMOSFET device. The N well region may be formed via implantation of arsenic or phosphorous ions. The result of these procedures is schematically shown in FIG. 1.

[0014] Gate insulator layer 5, may comprise silicon dioxide thermally grown on exposed surfaces of semiconductor substrate 1, preferably to a thickness between about 10 and about 40 Angstroms. Conductive layer 6, such as a doped polysilicon layer, may be formed via low pressure chemical vapor deposition (LPCVD) procedures to a thickness between about 800 and about 2000 Angstroms. Doped polysilicon layer 6 may be doped in situ during deposition via the addition of arsine or phosphine to a silane ambient, or a polysilicon layer can be intrinsically deposited then doped via implantation of arsensic or phosphorous ions. Insulator layer 7 may comprise silicon oxide or silicon oxynitride deposited via LPCVD or via plasma enhanced chemical vapor deposition (PECVD) procedures to a thickness between about 100 and about 500 Angstroms.

[0015] The gate insulator layer 5, conductive layer 6, and insulator layer 7 may be patterned by deposition and patterning a photoresist shape, not shown in the drawings. The photo resist shape may be used as a mask to allow an etching process, such as an anisotropic reactive ion etch (RIE) procedure, to define conductive gate structures 6, overlaid with insulator hard mask shapes 7, in both NMOSFET region 2, and PMOSFET region 3. The anisotropic RIE procedure may be performed using CF₄ or CHF₃ as an etchant for insulator layer 7, while C₁₂ may be used as a selective etchant for the conductive layer 6 formed of polysilicon, with the selective C₁₂ etch cycle terminating at the appearance of the top surface of silicon dioxide gate insulator layer 5. Removal of the photoresist shape may be accomplished via plasma oxygen ashing and wet cleans with a buffered hydrofluoric (BHF) acid cycle of the wet clean procedure resulting in removal of portions of gate insulator 5 not covered by the conductive gate structures.

[0016] Referring now to FIG. 2, a silicon oxide layer 8 may be formed by a thermal oxidation procedure to a thickness between about 30 and about 100 Angstroms on the exposed surfaces of the conductive gate structures 6, as well as on the portions of semiconductor substrate 1 not covered by the conductive gate structures 6. A silicon nitride layer may be formed via LPCVD or PECVD procedures to a thickness between about 300 and about 1000 Angstroms. A selective anisotropic RIE procedure may be performed using Cl₂ or CF₄ to define silicon nitride dummy spacers 9 on the portions of silicon oxide layer 8 located on the sides of conductive gate structures 6 and on the sides of insulator hard mask shapes 7. The dummy spacer defining RIE procedure selectively terminates at the appearance of the top surface of silicon oxide layer 8.

[0017] Referring now to FIG. 3, after removal of portions of silicon oxide layer 8 (FIG. 2) via, for example, a BHF procedure, portions of semiconductor substrate 1 that are not covered by conductive gate structures 6 or by silicon nitride dummy spacers 9 are exposed. An epitaxial growth procedure may be employed to selectively grow intrinsic silicon shapes 10a on the exposed portions of semiconductor substrate 1. The epitaxial silicon growth procedure may be performed, for example, at a temperature between about 700 and about 100° C. using silane or disilane as a source, resulting in the growth of intrinsic silicon regions 10a at a thickness between about 200 and about 800 Angstroms.

[0018] Referring now to FIG. 4, photoresist masking and ion implantation procedures are next applied to intrinsic silicon shapes 10a (FIG. 3) in NMOSFET region 2 resulting in N⁺ silicon shapes 10b, while additional photoresist masking and ion implantation procedures are used to allow the intrinsic silicon shapes 10a (FIG. 3) in PMOSFET region 3 to be P⁺ doped, resulting in P⁺ silicon shapes 10c. Ion implantation procedures may be performed, for example, using arsenic or phosphorous ions at energy between about 5 and about 40 KeV at a dose between about 1E15 and about 5E15 atoms/cm² for N⁺ silicon shapes 10b, while boron ions implanted at an energy between about 3 and about 15 KeV at a dose between about 1E15 and about 5E15 atoms/cm² may be employed for P⁺ silicon shapes 10c.

[0019] Removal of silicon nitride dummy spacers 9 is illustrated in FIG. 5. A wet etch procedure employing a hot phosphoric acid solution may be used to selectively etch the silicon nitride dummy spacers 9. The wet etch procedure selectively terminates on the portion of the silicon oxide layer 8 overlying the portions of semiconductor substrate 1 located between the raised silicon shapes 10b, 10c and the conductive gate structure 6. Insulator hard mask shapes 7 provide protection of conductive gate structure 6 during the selective hot phosphoric acid procedure.

[0020] Referring now to FIG. 6, a silicon-germanium region 11 is formed. The silicon-germanium region 11 may be formed by the implantation of germanium ions into a portion of semiconductor substrate 1 to be employed as a strained channel region for a MOSFET device. The implantation of germanium ions may be performed at an energy of about 50 and about 150 KeV at a dose of about 5E14 and about 1E16 atoms/cm² with an implant angle of about 15 and about 30°. The combination of the implant angle and the presence of the raised silicon shapes results in the strained silicon-germanium region 11 being located under the conductive gate structure 6. The raised silicon shapes 10 prevent the silicon-germanium region from extending into the area of the substrate 1 underlying the raised silicon shapes 10c. It should be noted that the insulator hard mask shape 7 protected the conductive gate structure 6 from the germanium implantation procedure.

[0021] In this embodiment, the germanium implant procedure is not performed simultaneously with an LDD implantation procedure. Therefore, photoresist masking to accommodate both P type and N type LDD implantation procedures may not be needed with this embodiment.

[0022] An anneal procedure, such as a rapid thermal anneal (RTA) procedure may be employed at a temperature of about 800 and about 1050° C. to activate the implanted germanium ions in the strained silicon-germanium region 11. It should be noted that the anneal procedure may cause out diffusion of dopants from the raised silicon shapes 10b and 10c into substrate 1, thereby forming source/drain regions 12b and 12c. In particular, the N type dopant in raised silicon shapes 10b may out diffuse into the substrate to create N type source/drain regions 12b, and the P-type dopant in raised silicon shapes 10c may out diffuse into the substrate to create P type source/drain regions 12c. It is preferred, however, that the silicon-germanium channel region 11 and the heavily-doped source/drain regions 12b and 12c do not contact each other to reduce the risk of junction leakage, which can occur if these regions directly interface.

[0023] Formation of the LDD regions in NMOSFET region 2 and in PMOSFET region 3 is next addressed and schematically shown in FIG. 7. Insulator hard mask shapes 7 may be removed by, for example, a dry or wet etch procedure, which may also remove the exposed portions of silicon oxide layer 8. A photoresist masking procedure may be used to protect PMOSFET region 3 from implantation of arsenic or phosphorous ions, which may be preferred at an energy of about 1 and about 5 KeV at a dose of about 5E14 and about 5E15 atoms/cm² and at an implant angle of about 0 and about 7°, creating N type LDD region 13b, in NMOSFET region 2. Another photoresist masking procedure may be used to protect NMOSFET region 2 during the formation of P type LDD region 13c in PMOSFET region 3, which may be accomplished, for example, via implantation of boron or BF₂ ions at an energy between about 1 and about 5 KeV at a dose between about 5E14 and about 5E14 atoms/cm² using an implant angle between about 0 and about 7. An anneal procedure, such as a rapid thermal anneal (RTA) procedure, may be employed to activate the implanted ions of the LDD regions.

[0024] A second embodiment of this invention features the sequential implantation of germanium for formation of the strained silicon-germanium channel region and of the ions needed for formation of LDD regions. This embodiment entails photoresist block out masking of the PMOSFET region followed by implantation of germanium using a first implant angle, followed by implantation of the N type LDD ions performed using a second implant angle into NMOSFET areas. Another photoresist block out masking procedure is then used to protect the NMOSFET region from a germanium implantation procedure performed using a first implant angle followed by implantation of the P type LDD ions accomplished using a second implant angle.

[0025] Insulator spacers 14, shown schematically in FIG. 8, are next formed on the sides of conductive gate structures 6. Insulator spacers 14 may be formed by forming an insulator layer such as silicon oxide or silicon nitride, to a thickness between about 300 and about 1000 Angstroms via LPCVD or PECVD procedures. A selective anisotropic RIE procedure may be performed using CHF₃ or CF₄ as an etchant to define the insulator spacers 14.

[0026] Metal silicide shapes 15, shown schematically in FIG. 9, may be used to improve the conductivity of conductive gate structures 6, as well as to decrease source/drain resistance. The metal silicide shapes may be formed by depositing a metal layer such as titanium, nickel, tungsten, or cobalt to a thickness between about 50 and about 200 Angstroms via plasma vapor deposition (PVD) procedures. An anneal procedure performed at a temperature between about 400 and about 800° C. causes the metal layer to react with conductive gate structures 6 and the silicon shapes 10b and 10c to form metal silicide shapes 15. Portions of the metal layer overlying insulator spacers 14 remain unreacted. Selective removal of the unreacted portions of the metal layer may be accomplished, for example, via wet etch procedures. An additional anneal cycle may be used if desired to alter the phase of metal silicide regions 15, resulting in a lower resistance metal silicide shape.

[0027] While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention.