US 7,799,592 B2Grant

Tri-gate field-effect transistors formed by aspect ratio trapping

Issue Date:2010-09-21

•23 Claims

•6 Drawing Sheets

Abstract

Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Metadata

Assignee

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor

Anthony J. Lochtefeld

Application Information

Application Number:US 11/861,931

Filing Date:2007-09-26

Priority Date:2006-09-27

Art Unit:2812

Classifications

IPC:

H01L21/00

Patent Drawings (6 sheets)

Description

Related Application

[0001] This application claims the benefit of and priority to U.S. Provisional Application Ser. No. 60/847,424 filed Sep. 27, 2006, the entire disclosure of which is hereby incorporated by reference in its entirety.

Field of the Invention

[0002] This invention relates generally to semiconductor processing and particularly to the formation of tri-gate field-effect transistors.

Background

[0003] Due to the increasing difficulty in shrinking complementary metal-oxide-semiconductor (CMOS) transistor gate lengths while simultaneously controlling leakage current, the traditional single-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure (where the inversion layer is formed only in the plane of the wafer surface) may be supplanted by dual- or triple-gate MOSFET structures. These structures, by increasing the gate's control of the channel potential, allow greater ability to turn off MOSFETs with ultra-short channel lengths. Of the various multi-gate MOSFETs structures explored in recent years, the most promising in terms of manufacturability and performance are typically variations of the so-called “FinFET” structure; these variations are known by such terms as “Tri-gate,” “Omega-FET,” or “MuGFET.” Generally, for each of these device types, a strip or “fin” of silicon (Si) is formed; subsequently the gate material is deposited and etched, so that the resulting gate surrounds the fin on the three exposed sides. The channel region of the device is located in the fin. To introduce strain into such a strip or fin, researchers have explored process-inducement methods similar to those employed in single-gate MOSFETs, such as, for example, epitaxially raised silicon germanium (SiGe) or silicon carbide (SiC) source and drain regions. There are, however, limitations to such methods, including limitations on how much strain can be introduced into the channel.

Summary

[0004] In various embodiments, the invention includes methods and structures for introducing strain into FinFET-type devices by exploiting differences in natural lattice constants between the channel region in the fin and a substantially relaxed semiconductor region below the channel.

[0005] Accordingly, an aspect of the invention features a method for forming a structure. The method includes forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material. A trench is defined in the dielectric layer, extending to a surface of the substrate, and having a height h and a width w; the ratio of h to w is preferably ≧0.5.

[0006] A crystalline material is formed in the trench. The crystalline material includes (i) a first layer comprising a second semiconductor material and (ii) a second layer comprising a third semiconductor material. A majority of dislocation defects in the crystalline material terminate within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material.

[0007] One or more of the following features may be included. The second and third semiconductor materials may have different lattice constants; the difference between lattice constants may be less than 1%. The second semiconductor material may be relaxed and the third semiconductor material may be strained. Removing a portion of the dielectric layer may include exposing at least a portion of a sidewall of the second layer. The second semiconductor material may include SiGe, and/or the third semiconductor material may include at least one of Si and Ge.

[0008] The second semiconductor material may have a bandgap of at least 0.5 eV. It may include at least one of a III-V compound, such as aluminum antimonide (AlSb), indium aluminum antimonide (InAlSb), gallium antimonide (GaSb), or a II-VI compound, such as cadmium selenide (CdSe), zinc telluride (ZnTe), or cadmium telluride (CdTe).

[0009] The third semiconductor material may have a bulk electron mobility greater than 2000 cm²/V·s and may include at least one of indium antimonide (InSb), indium arsenide (InAs), or indium gallium arsenide (InGaAs).

[0010] In another aspect, the invention features a method for forming a structure, in which a dielectric layer is formed over a semiconductor substrate including a first semiconductor material. A trench is defined in the dielectric layer, extending to a surface of the substrate, and having a height h and a width w; the ratio of h to w is preferably ≧0.5. A. At least one crystalline material layer including a second semiconductor material having a lattice mismatch with the first semiconductor material is formed in the trench, such that a majority of dislocation defects in the second semiconductor material terminate within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material.

[0011] One or more of the following features may be included. The second semiconductor material may include at least one of a III-V compound or a II-VI compound. The second semiconductor material may have a bandgap of at least 0.5 eV and/or have a bulk electron mobility greater than 2000 cm²/V·s.

[0012] The crystalline material layer(s) may include a first layer comprising the second semiconductor material and a second layer comprising a third semiconductor material. The third semiconductor material may include at least one of a III-V compound or a II-VI compound, and the third semiconductor material may be different from the second semiconductor material. The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. The third semiconductor material may include at least one element contained in the second semiconductor material. Defining the dielectric layer may include thermal oxidation and/or plasma-enhanced chemical vapor deposition (PECVD).

[0013] In yet another aspect, the invention features a method for forming a structure, including removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin. A dielectric layer is deposited over the substrate and the fin, and then planarized such that a top surface of the dielectric layer is substantially co-planar with a top surface of the fin. A trench is formed by removing at least a portion of the fin, the trench has a height h and a width w, and the ratio of h to w is preferably ≧0.5. A crystalline material is formed in the trench, and includes a second semiconductor material lattice-mismatched to the first semiconductor material. A majority of dislocation defects in the crystalline material terminating within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the second semiconductor material.

[0014] In still another aspect, the invention features a structure having a strained channel and including multiple semiconductor material layers at least partially disposed in a trench. The structure includes a dielectric layer disposed over a semiconductor substrate comprising a first semiconductor material. A trench is disposed in the dielectric layer. The trench (i) extends to a surface of the substrate, (ii) is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, and (iii) has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material includes a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material. A side portion of the crystalline material extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h to the width w is ≧0.5, and a majority of dislocation defects in the crystalline material terminate at or below the predetermined vertical distance H (with h≧H). The third semiconductor material defines a strained channel.

[0015] In another aspect, a semiconductor device includes a transistor structure formed above a defect trapping region. The semiconductor device includes a defect-trapping region comprising a trench including a dielectric sidewall. The defect-trapping region is proximate a substrate having a first lattice constant. A semiconductor material, disposed within the defect trapping region, has a second lattice constant different from the first lattice constant. A majority of crystalline defects in the semiconductor material terminate within the defect trapping region. A fin having a semiconducting sidewall is disposed above the semiconductor material disposed within the defect trapping region, and a transistor gate is disposed over the semiconducting sidewall and top surface of the fin.

[0016] Still another aspect of the invention features a method for forming a structure. The method includes the steps of forming a dielectric layer over a semiconductor substrate that itself includes a first semiconductor material, and defining a trench in the dielectric layer extending to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate; the trench is substantially rectangular and has a width w. A crystalline material including a first layer and a second layer is formed in the trench. The first layer includes a second semiconductor material, and the second layer includes a third semiconductor material. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, and dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H (h≧H).

[0017] The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. Removing a portion of the dielectric layer may include exposing at least a portion of a sidewall of the second layer. The second semiconductor material may comprise SiGe, and the third semiconductor material may include at least one of Si and Ge.

[0018] The second semiconductor material may have a bandgap of at least 0.5 eV. The second semiconductor material may include at least one of a III-V material and a II-VI material, e.g., at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, and CdTe.

[0019] The third semiconductor material may have a bulk electron mobility greater than 2000 cm²/V·s. The third semiconductor material may include at least one of InSb, InAs, and InGaAs. The difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material may be less than 1%.

[0020] In another aspect, the invention features a method for forming a structure. The method includes removing a portion of a semiconductor substrate including a first semiconductor material to define a fin, and depositing a dielectric layer over the substrate and the fin. The dielectric layer is planarized such that a top surface of the dielectric layer is substantially co-planar with a top surface of the fin. A trench is defined by removing at least a portion of the fin. The trench has at least one sidewall having a height h at least equal to a predetermined distance H from the bottom of the trench. The trench is substantially rectangular and has a width w. A crystalline material including a second semiconductor material is formed in the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the second semiconductor material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, and dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, and h≧H.

[0021] In another aspect, the invention features a structure including a dielectric layer disposed over a semiconductor substrate that itself includes a first semiconductor material. A trench is disposed in the dielectric layer and extends to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material comprises a first layer including a second semiconductor material and a second layer including a third semiconductor material. A side portion of the second layer extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the third semiconductor material defines a strained channel.

[0022] The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. In some embodiments, the second semiconductor material may include SiGe and the third semiconductor material may include at least one of Si and Ge.

[0023] In another aspect, the invention features a structure including a dielectric layer disposed over a semiconductor substrate that itself includes a first semiconductor material. A trench is disposed in the dielectric layer and extends to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material comprises a first layer including a second semiconductor layer and a second layer including a third semiconductor material. A side portion of the second layer extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the second semiconductor material has a bandgap of at least 0.5 eV.

[0024] The second semiconductor material may include at least one of a III-V material and a II-VI material, e.g., at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, or CdTe. The third semiconductor material may have a bulk electron mobility greater than 2000 cm²/V·s, and may include, e.g., at least one of InSb, InAs, and InGaAs. The difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material may be less than 1%.

Brief Description of Figures

[0025] In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

[0026] FIGS. 1-2 are schematic perspective views illustrating a method for formation of a device on a semiconductor substrate in accordance with an aspect of the invention;

[0027] FIGS. 3-4 are schematic perspective views illustrating an alternative method for formation of a device on a semiconductor substrate in accordance with other aspects of the invention; and

[0028] FIGS. 5-7 are schematic perspective views illustrating another alternative method for formation of a device on a semiconductor substrate in accordance with another aspect of the invention.

Detailed Description

[0029] Referring to FIG. 1, a substrate 100 includes a first semiconductor material S1. The substrate 100 may be, for example, a bulk Si wafer, a bulk germanium (Ge) wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of the first semiconductor material, such as a group IV element, e.g., Ge or Si, a III-V compound, or a II-VI compound. In an embodiment, substrate 100 includes or consists essentially of (100) Si.

[0030] A dielectric layer 110 is formed over the semiconductor substrate 100. The dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride (Si₃N₄) or silicon dioxide (SiO₂). The dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or PECVD. As discussed below, the dielectric layer may have a thickness t₁corresponding to a desired height h of crystalline material to be deposited in a trench formed through the dielectric layer. In some embodiments, the thickness t₁of the dielectric layer 110 may be in the range of, e.g., 25-1000 nm.

[0031] A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110. The mask is patterned to expose at least a portion of the dielectric layer 110. The exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define a defect trapping region, e.g., trench 120. Trench 120 extends to a surface of the substrate 100 and may be defined by at least one sidewall 130. The height h of the sidewall 130 corresponds to the thickness t₁of the dielectric layer 110, and may be at least equal to a predetermined vertical distance H from a top surface 135 of the substrate, calculated as described below.

[0032] It has been observed experimentally that dislocations in a mismatched cubic semiconductor grown on a Si (100) surface in the near vicinity (e.g., within approximately 500 nm or less) of a vertical dielectric sidewall surface bend toward that surface at approximately 30 degrees through 60 degrees. For example, the dislocations may bend toward that surface at approximately a 45-degree angle to that surface. Based on this relationship, the predetermined vertical distance H necessary to trap defects is, typically, approximately equal to a width between ½ w and 2 w, where w is the width of the trench. This range is based on the range of intersection angles of approximately 30 degrees through 60 degrees; then, tan(30°)w≦H≦tan(60°)w, which roughly corresponds to ½ w≦H≦2 w.

[0033] The trench may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than a length l of the trench. For example, the width w of the trench may be less than about 500 nm, e.g., about 10-100 nm, and the length l of the trench may exceed each of w and H. The ratio of the height h of the trench to the width w of the trench 120 may be ≧0.5, e.g., ≧1.

[0034] A crystalline material 140 is formed in the trench 120. The crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include Ge, Si, SiGe, and SiC. Examples of suitable III-V compounds include gallium arsenide (GaAs), gallium nitride (GaN), InAs, InSb, InAlSb, AlSb, indium aluminum arsenide (InAlAs), indium phosphide (InP), and InGaAs. Examples of suitable II-VI compounds include CdSe, ZnTe, and CdTe.

[0035] The crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300° C. to about 900° C., depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics.

[0036] The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.

[0037] Dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the trench 120 in the dielectric material 110 at or below the predetermined vertical distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the trench 120. Accordingly, the upper portion of the crystalline material is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be substantially eliminated from the upper portion of the crystalline material.

[0038] A planarization step such as, e.g., CMP may be used to ensure that the top surface of the crystalline material 140 is substantially co-planar with the top surface of the dielectric material 110.

[0039] Referring to FIG. 2, a portion of the dielectric layer 110 is selectively removed to expose a side portion 200 of the crystalline material 140. A height h_channelof the exposed side portion 200 may be equivalent to the thickness of a channel region to be formed. Preferably, the portion of the dielectric layer 110 is removed by an isotropic etch, e.g., a wet etch employing, for example, HF. A dry etch may also be used, e.g., a plasma etch employing CF₄and H₂.

[0040] The crystalline material 140 may be considered as having two portions: a lower portion for trapping dislocation defects and an upper portion for a channel portion of a tri-gate MOSFET incorporating the crystalline material 140. The height h of the crystalline material thus has two components: the height h_trappingof the lower portion (where defects are concentrated) and the height h_channelof the upper portion (which is largely free of defects). The height h_trappingof the trapping portion may be selected from a range of about ½ w≦h_trapping≦2 w, to ensure effective trapping of dislocation defects. The actual value of h_trappingrequired may depend upon the type of dislocation defects encountered, which, in turn, may depend on the materials used, and also upon the orientation of the trench sidewalls. In some instances, the height h_trappingneed not be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the channel portion. In this way, the deleterious effects of dislocation defects upon device performance are not experienced. For example, h_trappingmay be, e.g., 10-100 nm greater than required for effective trapping of defects. For the channel portion, the height h_channelmay typically be selected from the range of approximately ½ w≦h_channel≦10 w. In some cases, if h_channelis significantly less than ½ w, the device may no longer be considered a multi-gate device, i.e., if conduction occurs primarily on the top surface of the gates disposed over the channel portion. If h_channelis significantly greater than 10 w, subsequent device processing may be challenging, for example, because of possible mechanical instability of the fin during processing, or because of challenges in implanting ions in sidewalls of closely packed devices that include tall fins.

[0041] A gate 210 is defined over the crystalline material 140 by deposition and selective removal of a gate dielectric material 220 and a conductive gate material 230. The gate dielectric material may be, e.g., SiO₂, Si₃N₄, HfO₂, HfSiON, and/or HfSiO. The conductive gate material 230 may be, for example, polysilicon, amorphous Si, Ge, or SiGe gate material, or a metal or metal alloy. In a tri-gate device, gate 210 has three portions, one on each exposed side portion of the crystalline material 140 and one on a top surface of the crystalline material 140.

[0042] A source and a drain may be defined in source and drain regions 240, 250 of the crystalline material 140 proximate to the gate 210 and next to a channel 260 disposed under the gate 210. The resulting structure is a tri-gate MOSFET 270, employing the benefits of aspect ratio trapping (“ART”). As used herein, “ART” refers generally to the technique(s) of causing defects in a material to terminate on a side surface as the material grows vertically, e.g., at a dielectric sidewall, with the sidewall being sufficiently high with respect to a width of the growth area, such that it traps most, if not all, of the defects.

[0043] Referring to FIGS. 3 and 4, in some embodiments, the crystalline material 140 includes a first layer 300 and a second layer 310. The first layer 300 includes a second semiconductor material S2, and the second layer 310 includes a third semiconductor material S3. Each of the semiconductor material S2, S3 may include or consist essentially of one or more of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include Ge, SiGe, and SiC. Examples of suitable III-V compounds include GaAs, GaN, InAs, InSb, InAlSb, AlSb, InAlAs, rip, and InGaAs. Examples of suitable II-VI compounds include CdSe, ZnTe, and CdTe.

[0044] In an embodiment, the second and third semiconductor materials S2, S3 may be different materials having different lattice constants. The lattice mismatch may be selected from a range of, e.g., 0.2-4.0%. If the lattice mismatch is too low, the benefit to performance may not be significant. If the lattice mismatch is too high, the allowable thickness of the third semiconductor material S3 may be too limited, if gross relaxation of third semiconductor material S3 is to be avoided. The second semiconductor material S2 may be relaxed and the third semiconductor material S3 may be strained.

[0045] In one embodiment, the second semiconductor material S2 includes or consists essentially of relaxed SiGe, and the third semiconductor material S3 includes or consists essentially of Si. This combination results in tensile strain in the channel 260. The strain may be primarily uniaxial in the direction of current flow due to lateral elastic relaxation. This type of strain is particularly beneficial for n-type metal-oxide-semiconductor (NMOS) device performance.

[0046] In another embodiment, the second semiconductor material includes or consists essentially of relaxed SiGe, and the third semiconductor material S3 includes or consists essentially of Ge. This combination results in compressive strain in the channel 240. The strain may be primarily uniaxial in the direction of current flow due to lateral elastic relaxation. This type of strain is particularly beneficial for p-type metal-oxide-semiconductor (PMOS) device performance.

[0047] The resulting tri-gate MOSFET 270 or FinFET (FIG. 4) includes dielectric layer 110 disposed over the semiconductor substrate 100 including the first semiconductor material S1. Trench 120 is disposed in the dielectric layer 110, extends to the surface 135 of the substrate 100, and is defined by at least one sidewall 130. The sidewall 130 has a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. Crystalline material 140 is at least partially disposed in the trench. The crystalline material comprises a first layer 300 that includes a second semiconductor material, and a second layer 310 that includes a third semiconductor material. A side portion of the second layer extends above the dielectric layer. Gate 210 is disposed over the crystalline material. A ratio of the height h of the trench to the width w of the trench is preferably ≧0.5, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the third semiconductor material defines a strained channel 260.

[0048] A height h_S2of the first layer 300 may be approximately equal to h_trapping, and a height h_s3of the second layer 310 may be approximately equal to h_channel, with h_trappingand h_channelbeing determined as discussed above with reference to FIG. 2. The height of the first layer h_s2and the height of the second layer h_s3may be selected so that the second semiconductor material S2 is relaxed and the third semiconductor material S3 is strained, or vice versa.

[0049] The following relationships may be taken into consideration when selecting h_S2and h_s3. For compressively strained films, substantial relaxation occurs at a film thickness of approximately 3-4 times h_c, where h_cis the critical thickness for the appearance of misfit dislocations. For tensilely strained films, substantial relaxation occurs at a film thickness of about 10 h_c.

[0050] Referring still to FIGS. 3 and 4, in another embodiment, the second and third semiconductor materials S2, S3 may be selected to allow the formation of a bi-layer tri-gate device with high-mobility channel material and suppressed junction leakage. For example, the second semiconductor material S2 may have a bandgap of at least 0.5 eV. The second semiconductor material S2 may include or consist essentially of a III-V material and/or a II-VI material, such as AlSb, InAlSb, GaSb, CdSe, ZnTe, and/or CdTe. The third semiconductor material S3 may have a high bulk electron mobility, e.g., greater than 2000 cm²/V·s. Materials that are suitable for NMOS and have high mobilities include, e.g., InSb, InAs, and InGaAs.

[0051] For some potential III-V channel materials, straining the channel may not lead to significant performance benefits. In such cases, preferably the second semiconductor material S2 and the third semiconductor material S3 have similar lattice constants. Matching lattice constants helps avoid significant defect formation at an interface 400 between these two materials, while also allowing a sufficient height h_S3(e.g., 20-200 nm) of the second layer 310 to make this layer suitable for use as a MOS channel. In a preferred embodiment, the difference between the lattice constant of the second semiconductor material and the lattice constant of the third semiconductor material is less than 1%.

[0052] In forming the tri-gate device 270, a source and a drain are defined in source and drain regions 240, 250, respectively. Preferably, bottom portions of the source and the drain are disposed in second semiconductor material S2, such that the relatively high bandgap of second semiconductor material S2 helps limit junction leakage.

[0053] Referring to FIGS. 5-7, in some circumstances, from the standpoint of photolithography, it may be easier to define a narrow line than a narrow trench. Accordingly, an alternative process sequence for creating trench 120 begins with formation of a mask (not shown) over semiconductor substrate 100. A portion of the semiconductor substrate 100 is removed to define a fin 500. Fin 500 may have dimensions substantially identically to the dimensions of trench 120. Dielectric layer 110 is deposited over the semiconductor substrate 100 and the fin 500. The dielectric layer 110 is then planarized by, e.g., chemical-mechanical polishing (CMP) such that a top surface of the dielectric layer is substantially co-planar with a top surface 510 of the fin 500.

[0054] Trench 120 is defined by removing at least a portion of the fin 500. The fin may be selectively removed with a wet or dry etch that removes semiconductor material S1 with respect to the dielectric layer 110. For example, if semiconductor material S1 primarily comprises Si, and dielectric layer 110 primarily comprises SiO₂, a dry etch utilizing Cl₂and/or HBr may be used to selectively remove the Si. The etch may be a timed etch, thereby avoiding undercutting a bottom portion of the dielectric layer 110.

[0055] As discussed above with respect to FIG. 1, trench 120 is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the bottom of the trench. The trench may be substantially rectangular and have a width w. The ratio of the height h of the trench to the width w of the trench is preferably ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, and h≧H. A crystalline material 140 is formed in the trench. The crystalline material includes second semiconductor material S2.

[0056] Referring to FIG. 7, a portion of the dielectric layer 110 is removed to expose a side portion of the crystalline material. A gate dielectric 220 and a gate 210 are formed over the second semiconductor material S2, to define a FinFET.

[0057] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

What is claimed is:

1. A method for forming a structure, the method comprising the steps of:

forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;

defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;

forming, in the trench, a crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;

removing a portion of the dielectric layer to expose a side portion of the crystalline material; and

defining a gate over the crystalline material.

2. The method of claim 1, wherein the second and third semiconductor materials have different lattice constants.

3. The method of claim 2, wherein the second semiconductor material is relaxed and the third semiconductor material is strained.

4. The method of claim 1, wherein removing a portion of the dielectric layer comprises exposing at least a portion of a sidewall of the second layer.

5. The method of claim 1, wherein the second semiconductor material comprises SiGe.

6. The method of claim 5, wherein the third semiconductor material comprises at least one of Si and Ge.

7. The method of claim 1, wherein the second semiconductor material has a bandgap of at least 0.5 eV.

8. The method of claim 7, wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.

9. The method of claim 8, wherein the second semiconductor material comprises at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, or CdTe.

10. The method of claim 1, wherein the third semiconductor material has a bulk electron mobility greater than 2000 cm²/V·s.

11. The method of claim 10, wherein the third semiconductor material comprises at least one of InSb, InAs, or InGaAs.

12. The method of claim 1, wherein a difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material is less than 1%.

13. A method for forming a structure, the method comprising the steps of:

forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;

defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;

forming, in the trench, at least one crystalline material layer comprising a second semiconductor material having a lattice mismatch with the first semiconductor material, a majority of dislocation defects in the second semiconductor material terminating within the trench;

removing a portion of the dielectric layer to expose a side portion of the crystalline material; and

defining a gate over the crystalline material.

14. The method of claim 13, wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.

15. The method of claim 13, wherein the second semiconductor material has a bandgap of at least 0.5 eV.

16. The method of claim 13, wherein the second semiconductor material has a bulk electron mobility greater than 2000 cm²/V·s.

17. The method of claim 13, wherein the at least one crystalline material layer includes a first layer comprising the second semiconductor material and a second layer comprising a third semiconductor material.

18. The method of claim 17, wherein the third semiconductor material comprises at least one of a III-V compound or a II-VI compound, and the third semiconductor material is different from the second semiconductor material.

19. The method of claim 17, wherein the second and third semiconductor materials have different lattice constants.

20. The method of claim 17, wherein the second semiconductor material is relaxed and the third semiconductor material is strained.

21. The method of claim 17, wherein the third semiconductor material includes at least one element contained in the second semiconductor material.

22. The method of claim 13, wherein defining the dielectric layer comprises at least one of thermal oxidation or PECVD.

23. A method for forming a structure, the method comprising:

removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin;

depositing a dielectric layer over the substrate and the fin;

planarizing the dielectric layer such that a top surface thereof is substantially co-planar with a top surface of the fin;

defining a trench by removing at least a portion of the fin, the trench having a height h and a width w, the ratio of h to w being ≧0.5;

forming, in the trench, a crystalline material comprising a second semiconductor material lattice-mismatched to the first semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;

removing a portion of the dielectric layer to expose a side portion of the crystalline material; and

defining a gate over the second semiconductor material.

Patent Citations (272)

Patent	Date	Inventor	Cited By
US4545109(A)	1985-10-01	Reichert	Applicant
US4551394(A)	1985-11-01	Betsch et al.	Applicant
US4651179(A)	1987-03-01	Reichert	Applicant
US4727047(A)	1988-02-01	Bozler et al.	Applicant
US4774205(A)	1988-09-01	Choi et al.	Applicant
US4789643(A)	1988-12-01	Kajikawa	Applicant
US4826784(A)	1989-05-01	Salerno et al.	Applicant
US4860081(A)	1989-08-01	Cogan	Applicant
US4876210(A)	1989-10-01	Barnett et al.	Applicant
US4948456(A)	1990-08-01	Schubert	Applicant
US5032893(A)	1991-07-01	Fitzgerald, Jr. et al.	Applicant
US5034337(A)	1991-07-01	Mosher et al.	Applicant
US5061644(A)	1991-10-01	Yue et al.	Applicant
US5091333(A)	1992-02-01	Fan et al.	Applicant
US5091767(A)	1992-02-01	Bean et al.	Applicant
US5093699(A)	1992-03-01	Weichold et al.	Applicant
US5098850(A)	1992-03-01	Nishida et al.	Applicant
US5105247(A)	1992-04-01	Cavanaugh	Applicant
US5156995(A)	1992-10-01	Fitzgerald, Jr. et al.	Applicant
US5166767(A)	1992-11-01	Kapoor et al.	Applicant
US5236546(A)	1993-08-01	Mizutani et al.	Applicant
US5238869(A)	1993-08-01	Shichijo et al.	Applicant
US5256594(A)	1993-10-01	Wu et al.	Applicant
US5269852(A)	1993-12-01	Nishida et al.	Applicant
US5269876(A)	1993-12-01	Mizutani et al.	Applicant
US5281283(A)	1994-01-01	Tokunaga et al.	Applicant
US5285086(A)	1994-02-01	Fitzgerald, Jr.	Applicant
US5295150(A)	1994-03-01	Vangieson et al.	Applicant
US5403751(A)	1995-04-01	Nishida et al.	Applicant
US5417180(A)	1995-05-01	Nakamura et al.	Applicant
US5427976(A)	1995-06-01	Koh et al.	Applicant
US5432120(A)	1995-07-01	Meister et al.	Applicant
US5438018(A)	1995-08-01	Mori et al.	Applicant
US5518953(A)	1996-05-01	Takasu et al.	Applicant
US5589696(A)	1996-12-01	Baba et al.	Applicant
US5621227(A)	1997-04-01	Joshi	Applicant
US5640022(A)	1997-06-01	Inai et al.	Applicant
US5710436(A)	1998-01-01	Tanamoto et al.	Applicant
US5717709(A)	1998-02-01	Sasaki et al.	Applicant
US5792679(A)	1998-08-01	Nakato	Applicant
US5825049(A)	1998-10-01	Simmons et al.	Applicant
US5849077(A)	1998-12-01	Kenney	Applicant
US5886385(A)	1999-03-01	Arisumi et al.	Applicant
US5953361(A)	1999-09-01	Borchert et al.	Applicant
US5966620(A)	1999-10-01	Sakaguchi et al.	Applicant
US6011271(A)	2000-01-01	Sakuma et al.	Applicant
US6015979(A)	2000-01-01	Sugiura et al.	Applicant
US6049098(A)	2000-04-01	Sato et al.	Applicant
US6100106(A)	2000-08-01	Yamaguchi et al.	Applicant
US6111288(A)	2000-08-01	Watanabe et al.	Applicant
US6191432(B1)	2001-02-01	Sugiyama et al.	Applicant
US6228691(B1)	2001-05-01	Doyle	Applicant
US6235547(B1)	2001-05-01	Sakuma et al.	Applicant
US6252261(B1)	2001-06-01	Usui et al.	Applicant
US6271551(B1)	2001-08-01	Schmitz et al.	Applicant
US6320220(B1)	2001-11-01	Watanabe et al.	Applicant
US6342404(B1)	2002-01-01	Shibata et al.	Applicant
US6348096(B1)	2002-02-01	Sunakawa et al.	Applicant
US6362071(B1)	2002-03-01	Nguyen et al.	Applicant
US6407425(B1)	2002-06-01	Babcock et al.	Applicant
US6475869(B1)	2002-11-01	Yu	Applicant
US6492216(B1)	2002-12-01	Yeo et al.	Applicant
US6512252(B1)	2003-01-01	Takagi et al.	Applicant
US6521514(B1)	2003-02-01	Gehrke et al.	Applicant
US6576532(B1)	2003-06-01	Jones et al.	Applicant
US6579463(B1)	2003-06-01	Winningham et al.	Applicant
US6603172(B1)	2003-08-01	Segawa et al.	Applicant
US6617643(B1)	2003-09-01	Goodwin-Johansson	Applicant
US6635110(B1)	2003-10-01	Luan et al.	Applicant
US6686245(B1)	2004-02-01	Mathew et al.	Applicant
US6710368(B2)	2004-03-01	Fisher et al.	Applicant
US6720196(B2)	2004-04-01	Kunisato et al.	Applicant
US6727523(B2)	2004-04-01	Morita et al.	Applicant
US6753555(B2)	2004-06-01	Takagi et al.	Applicant
US6762483(B1)	2004-07-01	Krivokapic et al.	Applicant
US6767793(B2)	2004-07-01	Clark et al.	Applicant
US6784074(B2)	2004-08-01	Shchukin et al.	Applicant
US6787864(B2)	2004-09-01	Paton et al.	Applicant
US6794718(B2)	2004-09-01	Nowak et al.	Applicant
US7061065(B2)	2004-09-01	Horng	Applicant
US6800910(B2)	2004-10-01	Lin et al.	Applicant
US6803598(B1)	2004-10-01	Berger et al.	Applicant
US6809351(B2)	2004-10-01	Kuramoto et al.	Applicant
US6812495(B2)	2004-11-01	Wada et al.	Applicant
US6815241(B2)	2004-11-01	Wang	Applicant
US6815738(B2)	2004-11-01	Rim	Applicant
US6825534(B2)	2004-11-01	Chen et al.	Applicant
US6835246(B2)	2004-12-01	Zaidi	Applicant
US6835618(B1)	2004-12-01	Dakshina-Murthy et al.	Applicant
US6838322(B2)	2005-01-01	Pham et al.	Applicant
US6841410(B2)	2005-01-01	Sasaoka et al.	Applicant
US6841808(B2)	2005-01-01	Shibata et al.	Applicant
US6849487(B2)	2005-02-01	Taylor, Jr. et al.	Applicant
US6849884(B2)	2005-02-01	Clark et al.	Applicant
US6855583(B1)	2005-02-01	Krivokapic et al.	Applicant
US6855982(B1)	2005-02-01	Xiang et al.	Applicant
US6855990(B2)	2005-02-01	Yeo et al.	Applicant
US6867433(B2)	2005-03-01	Yeo et al.	Applicant
US6873009(B2)	2005-03-01	Hisamoto et al.	Applicant
US6887773(B2)	2005-05-01	Gunn, III et al.	Applicant
US6888181(B1)	2005-05-01	Liao et al.	Applicant
US6900070(B2)	2005-05-01	Craven et al.	Applicant
US6900502(B2)	2005-05-01	Ge et al.	Applicant
US6902965(B2)	2005-06-01	Ge et al.	Applicant
US6902991(B2)	2005-06-01	Xiang et al.	Applicant
US6909186(B2)	2005-06-01	Chu	Applicant
US6917068(B1)	2005-07-01	Krivokapic	Applicant
US6919258(B2)	2005-07-01	Grant et al.	Applicant
US6920159(B2)	2005-07-01	Sidorin et al.	Applicant
US6921673(B2)	2005-07-01	Kobayashi et al.	Applicant
US6921963(B2)	2005-07-01	Krivokapic et al.	Applicant
US6921982(B2)	2005-07-01	Joshi et al.	Applicant
US6936875(B2)	2005-08-01	Sugii et al.	Applicant
US6943407(B2)	2005-09-01	Ouyang et al.	Applicant
US6946683(B2)	2005-09-01	Sano et al.	Applicant
US6949769(B2)	2005-09-01	Hu et al.	Applicant
US6955969(B2)	2005-10-01	Djomehri et al.	Applicant
US6955977(B2)	2005-10-01	Kong et al.	Applicant
US6958254(B2)	2005-10-01	Seifert et al.	Applicant
US6960781(B2)	2005-11-01	Currie et al.	Applicant
US6974733(B2)	2005-12-01	Boyanov et al.	Applicant
US6977194(B2)	2005-12-01	Belyansky et al.	Applicant
US6982204(B2)	2006-01-01	Saxler et al.	Applicant
US6984571(B1)	2006-01-01	Enquist	Applicant
US6991998(B2)	2006-01-01	Bedell et al.	Applicant
US6994751(B2)	2006-02-01	Hata et al.	Applicant
US6995430(B2)	2006-02-01	Langdo et al.	Applicant
US6995456(B2)	2006-02-01	Nowak	Applicant
US6998684(B2)	2006-02-01	Anderson et al.	Applicant
US7001804(B2)	2006-02-01	Dietz et al.	Applicant
US7012298(B1)	2006-03-01	Krivokapic	Applicant
US7012314(B2)	2006-03-01	Bude et al.	Applicant
US7015497(B1)	2006-03-01	Berger	Applicant
US7015517(B2)	2006-03-01	Grant et al.	Applicant
US7033436(B2)	2006-04-01	Biwa et al.	Applicant
US7033936(B1)	2006-04-01	Green et al.	Applicant
US7041178(B2)	2006-05-01	Tong et al.	Applicant
US7045401(B2)	2006-05-01	Lee et al.	Applicant
US7049627(B2)	2006-05-01	Vineis et al.	Applicant
US7074623(B2)	2006-07-01	Lochtefeld et al.	Applicant
US7078299(B2)	2006-07-01	Maszara et al.	Applicant
US7078731(B2)	2006-07-01	D'Evelyn et al.	Applicant
US7084051(B2)	2006-08-01	Ueda et al.	Applicant
US7084441(B2)	2006-08-01	Saxler	Applicant
US7087965(B2)	2006-08-01	Chan et al.	Applicant
US7091561(B2)	2006-08-01	Matsushita et al.	Applicant
US7095043(B2)	2006-08-01	Oda et al.	Applicant
US7098508(B2)	2006-08-01	Ieong et al.	Applicant
US7101444(B2)	2006-09-01	Shchukin et al.	Applicant
US7109516(B2)	2006-09-01	Langdo et al.	Applicant
US7118987(B2)	2006-10-01	Fu et al.	Applicant
US7119402(B2)	2006-10-01	Kinoshita et al.	Applicant
US7125785(B2)	2006-10-01	Cohen et al.	Applicant
US7128846(B2)	2006-10-01	Nishijima et al.	Applicant
US7132691(B1)	2006-11-01	Tanabe et al.	Applicant
US7138292(B2)	2006-11-01	Mirabedini et al.	Applicant
US7138302(B2)	2006-11-01	Xiang et al.	Applicant
US7160753(B2)	2007-01-01	Williams, Jr.	Applicant
US7164183(B2)	2007-01-01	Sakaguchi et al.	Applicant
US7176522(B2)	2007-02-01	Cheng et al.	Applicant
US7180134(B2)	2007-02-01	Yang et al.	Applicant
US7195993(B2)	2007-03-01	Zheleva et al.	Applicant
US7198995(B2)	2007-04-01	Chidambarrao et al.	Applicant
US7205586(B2)	2007-04-01	Takagi et al.	Applicant
US7205604(B2)	2007-04-01	Ouyang et al.	Applicant
US7211864(B2)	2007-05-01	Seliskar	Applicant
US7224033(B2)	2007-05-01	Zhu et al.	Applicant
US7244958(B2)	2007-07-01	Shang et al.	Applicant
US7247534(B2)	2007-07-01	Chidambarrao et al.	Applicant
US7247912(B2)	2007-07-01	Zhu et al.	Applicant
US7250359(B2)	2007-07-01	Fitzgerald	Applicant
US7262117(B1)	2007-08-01	Gunn, III et al.	Applicant
US7268058(B2)	2007-09-01	Chau et al.	Applicant
US7344942(B2)	2008-03-01	Korber	Applicant
US2001/0006249(A1)	2001-07-01	Fitzgerald	Applicant
US2001/0045604(A1)	2001-11-01	Oda et al.	Applicant
US2002/0030246(A1)	2002-03-01	Eisenbeiser et al.	Applicant
US2002/0066403(A1)	2002-06-01	Sunakawa et al.	Applicant
US2002/0070383(A1)	2002-06-01	Shibata et al.	Applicant
US2002/0084000(A1)	2002-07-01	Fitzgerald	Examiner
US2003/0030117(A1)	2003-02-01	Iwasaki et al.	Applicant
US2003/0045017(A1)	2003-03-01	Hiramatsu et al.	Applicant
US2003/0064535(A1)	2003-04-01	Kub et al.	Applicant
US2003/0087462(A1)	2003-05-01	Koide et al.	Applicant
US2003/0089899(A1)	2003-05-01	Lieber et al.	Applicant
US2003/0155586(A1)	2003-08-01	Koide et al.	Applicant
US2003/0178677(A1)	2003-09-01	Clark et al.	Applicant
US2003/0207518(A1)	2003-11-01	Kong et al.	Applicant
US2004/0012037(A1)	2004-01-01	Venkatesan et al.	Applicant
US2004/0072410(A1)	2004-04-01	Motoki et al.	Applicant
US2004/0075105(A1)	2004-04-01	Leitz et al.	Applicant
US2004/0195624(A1)	2004-10-01	Liu et al.	Applicant
US2004/0227187(A1)	2004-11-01	Cheng et al.	Applicant
US2005/0003572(A1)	2005-01-01	Hahn et al.	Applicant
US2005/0017351(A1)	2005-01-01	Ravi	Applicant
US2005/0040444(A1)	2005-02-01	Cohen	Applicant
US2005/0045983(A1)	2005-03-01	Noda et al.	Applicant
US2005/0054164(A1)	2005-03-01	Xiang	Applicant
US2005/0054180(A1)	2005-03-01	Han	Applicant
US2005/0073028(A1)	2005-04-01	Grant et al.	Examiner
US2005/0093021(A1)	2005-05-01	Ouyang et al.	Applicant
US2005/0093154(A1)	2005-05-01	Kottantharayil et al.	Applicant
US2005/0104152(A1)	2005-05-01	Snyder et al.	Applicant
US2005/0104156(A1)	2005-05-01	Wasshuber	Applicant
US2005/0118793(A1)	2005-06-01	Snyder et al.	Applicant
US2005/0118825(A1)	2005-06-01	Nishijima et al.	Applicant
US2005/0127451(A1)	2005-06-01	Tsuchiya et al.	Applicant
US2005/0139860(A1)	2005-06-01	Snyder et al.	Applicant
US2005/0145941(A1)	2005-07-01	Bedell et al.	Applicant
US2005/0145954(A1)	2005-07-01	Zhu et al.	Applicant
US2005/0156169(A1)	2005-07-01	Chu	Applicant
US2005/0156202(A1)	2005-07-01	Rhee et al.	Applicant
US2005/0161711(A1)	2005-07-01	Chu	Applicant
US2005/0164475(A1)	2005-07-01	Peckerar et al.	Applicant
US2005/0181549(A1)	2005-08-01	Barr et al.	Applicant
US2005/0184302(A1)	2005-08-01	Kobayashi et al.	Applicant
US2005/0205859(A1)	2005-09-01	Currie et al.	Applicant
US2005/0205932(A1)	2005-09-01	Cohen	Applicant
US2005/0212051(A1)	2005-09-01	Jozwiak et al.	Applicant
US2005/0217565(A1)	2005-10-01	Lahreche et al.	Applicant
US2005/0250285(A1)	2005-11-01	Yoon et al.	Examiner
US2006/0009012(A1)	2006-01-01	Leitz et al.	Applicant
US2006/0019462(A1)	2006-01-01	Cheng et al.	Applicant
US2006/0049409(A1)	2006-03-01	Rafferty et al.	Applicant
US2006/0105533(A1)	2006-05-01	Chong et al.	Applicant
US2006/0113603(A1)	2006-06-01	Currie	Applicant
US2006/0128124(A1)	2006-06-01	Haskell et al.	Applicant
US2006/0131606(A1)	2006-06-01	Cheng	Applicant
US2006/0145264(A1)	2006-07-01	Chidambarrao et al.	Applicant
US2006/0160291(A1)	2006-07-01	Lee et al.	Applicant
US2006/0175601(A1)	2006-08-01	Lieber et al.	Applicant
US2006/0186510(A1)	2006-08-01	Lochtefeld et al.	Applicant
US2006/0189056(A1)	2006-08-01	Ko et al.	Applicant
US2006/0197123(A1)	2006-09-01	Lochtefeld et al.	Applicant
US2006/0197124(A1)	2006-09-01	Lochtefeld et al.	Applicant
US2006/0197126(A1)	2006-09-01	Lochtefeld et al.	Applicant
US2006/0202276(A1)	2006-09-01	Kato	Applicant
US2006/0205197(A1)	2006-09-01	Yi et al.	Applicant
US2006/0211210(A1)	2006-09-01	Bhat et al.	Applicant
US2006/0267047(A1)	2006-11-01	Murayama	Applicant
US2006/0292719(A1)	2006-12-01	Lochtefeld et al.	Applicant
US2007/0029643(A1)	2007-02-01	Johnson et al.	Applicant
US2007/0054465(A1)	2007-03-01	Currie et al.	Applicant
US2007/0054467(A1)	2007-03-01	Currie et al.	Applicant
US2007/0105256(A1)	2007-05-01	Fitzgerald	Applicant
US2007/0105274(A1)	2007-05-01	Fitzgerald	Applicant
US2007/0105335(A1)	2007-05-01	Fitzgerald	Applicant
US2007/0181977(A1)	2007-08-01	Lochtefeld et al.	Applicant
US2007/0187668(A1)	2007-08-01	Noguchi et al.	Applicant
US2007/0196987(A1)	2007-08-01	Chidambarrao et al.	Applicant
US2007/0267722(A1)	2007-11-01	Lochtefeld et al.	Applicant
US2008/0001169(A1)	2008-01-01	Lochtefeld	Applicant
US2008/0070355(A1)	2008-03-01	Lochtefeld et al.	Applicant
US2008/0073641(A1)	2008-03-01	Cheng et al.	Applicant
US2008/0093622(A1)	2008-04-01	Li et al.	Applicant
US2008/0099785(A1)	2008-05-01	Bai et al.	Applicant
US2008/0187018(A1)	2008-08-01	Li	Applicant
US2009/0039361(A1)	2009-02-01	Li et al.	Applicant
US2009/0065047(A1)	2009-03-01	Fiorenza et al.	Applicant
EP1551063	2005-07-01		Applicant
EP1796180	2007-06-01		Applicant
JP2-62090	1990-03-01		Applicant
JP2062090	1990-03-01		Examiner
JP2000-286449	2000-10-01		Applicant
JP2004-200375	2004-07-01		Applicant
WO-02/086952	2002-10-01		Applicant
WO2004/023536	2004-03-01		Applicant
WO-2005/013375	2005-02-01		Applicant
WO-2005/048330	2005-05-01		Applicant
WO-2005/098963	2005-10-01		Applicant
WO-2005/122267	2005-12-01		Applicant
WO-2006/125040	2006-11-01		Applicant

Non-Patent Literature (213)

68 Applied Physics Letters 7, pp. 774-779 (1999). (trans. of relevant portions attached).Applicant
Asano, T. et al., “AIGaInN laser diodes grown on an ELO-GaN substrate vs. on a sapphire substrate,” 2000 IEEE 17th International Semiconductor Laser Conference, Conference Digest., pp. 109-110.Applicant
Ashby, C.I.H. et al., “Low-dislocation-density GaN from a single growth on a textured substrate.” Applied Physics Letters, v 77, n 20, Nov. 13, 2000, p. 3233-35.Applicant
Ashley et al., “Heternogeneous InSb Quantum Well Transistors on Silicon for ultra-high speed, low power logic applications,” 43 Electronics Letters 14 (Jul. 2007).Applicant
Bai et al, “Study of the defect elimination mechanisms in aspect ratio trapping Ge growth,” Appl. Phys. Letters, vol. 90 (2007).Applicant
Bakkers et al., “Epitaxial Growth on InP Nanowires on Germanium,” Nature Materials, vol. 3 (Nov. 2004), pp. 769-773.Applicant
Baron et al., “Chemical Vapor Deposition of Ge Nanocrystals on SiO2,” Applied Physics Letters, vol. 83, No. 7 (Aug. 18, 2003), pp. 1444-1446.Applicant
Beckett et al., “Towards a reconfigurable nanocomputer platform,” ACM Int'l. Conf. Proceeding Series, vol. 19, pp. 141-150 (2002).Applicant
Beltz et al., “A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth,” Materials Science and Engineering, A234-236 (1997), pp. 794-797.Applicant
Borland, J.O., “Novel device structures by selective epitaxial growth (SEG),” 1987 International Electron Devices Meeting, pp. 12-15.Applicant
Bryskiewicz, T., “Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method,” Applied Physics Letters, v 66, n 10, Mar. 6, 1995, p. 1237-39.Applicant
Bushroa, A.R. et al., “Lateral epitaxial overgrowth and reduction in defect density of 3C-SiC on patterned Si substrates,” Journal of Crystal Growth, v 271, Oct. 15, 2004, pp. 200-206.Applicant
Cannon et al., “Monolithic Si-based Technology for Optical Receiver Circuits,” Proceedings of SPIE, vol. 4999 (2003), pp. 145-155.Applicant
Chan et al., “Influence of metalorganic Sources on the Composition Uniformity of Selectively Grown GaxIn1-xP,” Jpn J. Appl. Phys., vol. 33 (1994) pp. 4812-4819.Applicant
Chang et al., “Epitaxial Lateral Overgrowth of Wide Dislocation-Free GaAs on Si Substrates,” Electrochemical Soc'y Proceedings, vol. 97-21, pp. 196-200.Applicant
Chang, Y.S. et al., “Effect of growth temperature on epitaxial lateral overgrowth of GaAs on Si substrate,” Journal of Crystal Growth, 174, Apr. 1997, pp. 630-634.Applicant
Chau et al., “Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications,” IEEE CSIC Digest, pp. 17-20 (2005).Applicant
Chen, Y. et al., “Dislocation reduction in GaN thin films via lateral overgrowth from trenches,” Applied Physics Letters, v 75, n 14, Oct. 4, 1999, p. 2062-63.Applicant
Dadgar et al., “MOVPE Growth of GaN on Si (111) Substrates,” Journal of Crystal Growth, 248 (2003) pp. 556-562.Applicant
Datta et al., “Silicon and III-V Nanoelectronics,” IEEE Int'l. Conf. on Indium Phosphide & Related Mat., pp. 7-8 (2005).Applicant
Datta et al., “Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate,” 28 Electron Device Letters 8, pp. 685-687 (2007).Applicant
Davis, R.F. et al., “Lateral epitaxial overgrowth of and defect reduction in GaN thin films,” IEEE Lasers and Electro-Optics Society Annual Meeting, 1998, vol. 1, pp. 360-361.Applicant
de Boeck et al., “The fabrication on a novel composite GaAs/SiO2 nucleation layer on silicon for heteroepitaxial overgrowth by molecular beam epitaxy,” Mat. Sci. and Engineering, B9 (1991), pp. 137-141.Applicant
Dong et al., “Selective area growth of InP through narrow openings by MOCVD and its application to InP HBT,” 2003 International Conference on Indium Phosphide and Related Materials, pp. 389-392, May 12-16, 2003.Applicant
Dong-Ho Kim et al., “GaN nano epitaxial lateral overgrowth on holographically patterned substrates,” International Symposium on Compound Semiconductors, pp. 27-28, Aug. 2003.Applicant
Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, 28 Jap. J. App. Physics 3, pp. L337-L339 (Mar. 1989).Applicant
Fang et al., “Electrically pumped hybrid AIGaInAs-silicon evanescent laser,” 14 Optics Express 20, pp. 9203-9210 (2006).Applicant
Feltin, E. et al., “Epitaxial lateral overgrowth of GaN on Si (111),” Journal of Applied Physics, v 93, n 1, Jan. 1, 2003, pp. 182-185.Applicant
Fitzgerald et al., “Elimination of Dislocations in Heteroepitaxial MBE and RTCVD GexSi1-x Grown on Patterned Si Substrates,” Journal of Electronic Materials, vol. 19, No. 9 (1990), pp. 949-955.Applicant
Fitzgerald et al., “Epitaxial Necking in GaAs Grown on Pre-patterned Si Substrates,” Journal of Electronic Materials, vol. 20, No. 10 (1991), pp. 839-853.Applicant
Fitzgerald et al., “Nucleation Mechanisms and the Elimination of Misfit Dislocations at Mismatched Interfaces by Reduction in Growth Area,” J. Applied Phys., vol. 65, No. 6, (Mar. 15, 1989), pp. 2220-2237.Applicant
Fitzgerald, “The Effect of Substrate Growth Area on Misfit and Threading Dislocation Densities in Mismatched Heterostructures,” J. Vac. Sci. Technol., vol. 7, No. 4 (Jul./Aug. 1989), pp. 782-788.Applicant
Gallagher et al., “Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip,” 50 IBM J. Research & Dev. 1 (2006).Applicant
Gallas et al, “Influence of Doping on Facet Formation at the SiO2/Si Interface,” Surface Sci. 440, pp. 41-48 (1999).Applicant
Geppert, L., “Quantum transistors: toward nanoelectronics,” IEEE Spectrum, pp. 46-51 (Sep. 2000).Applicant
Glew et al., “New DFB grating structure using dopant-induced refractive index step,” J. Crystal Growth 261 (2004) pp. 349-354.Applicant
Gould et al., “Magnetic resonant tunneling diodes as voltage-controlled spin selectors,” 241 Phys. Stat. Sol. (B) 3, pp. 700-703 (2004).Applicant
Groenert et al., “Monolithic integration of room-temperature cw GaAs/AIGaAs lasers on Si substrates via relaxed graded GeSi buffer layers,” 93 J. Appl. Phys. 362 (2003).Applicant
Gustafsson et al., “Cathodoluminescence from relaxed GexSi1-x grown by heteroepitaxial lateral overgrowth,” J. Crystal Growth 141 (1994), pp. 363-370.Applicant
Gustafsson et al., “Investigations of high quality GexSi1-x grown by heteroepitaxial lateral overgrowth using cathodoluminescence,” Inst. Phys. Conf. Ser. No. 134: Section 11, pp. 675-678 (1993).Applicant
Hayafuji et al., Jap. J. Appl. Phys. 29, pp. 2371 (1990).Applicant
Hersee, et al., “The Controlled Growth of GaN Nanowires,” Nano Letters, vol. 6, No. 8 (2006), pp. 1808-1811.Applicant
Hiramatsu, K. et al., “Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO),” Journal of Crystal Growth, v 221, Dec. 2000, pp. 316-326.Applicant
Hollander et al., “Strain and Misfit Dislocation Density in Finite Lateral Size Si1-xGex Films Grown by Sective Epitaxy,” Thin Solid Films, vol. 292, (1997) pp. 213-217.Applicant
Huang et al., “Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding,” 49 IEEE Trans. on Electron Devices 9, pp. 1566-1571 (2002).Applicant
International Search Report and Written Opinion for Patent Application No. PCT/US2006/019152, dated Oct. 19, 2006.Applicant
International Search Report and Written Opinion for Patent Application No. PCT/US2006/029247, dated May 7, 2007.Applicant
International Search Report and Written Opinion for Patent Application No. PCT/US2006/033859, dated Sep. 12, 2007.Applicant
Ipri, A.C. et al., “Mono/Poly technology for fabricating low-capacitance CMOS integrated circuits,” IEEE Trans. on Electron Devices, vol. 35, No. 8, pp. 1382-1383, Aug. 1988.Applicant
Ishitani et al., “Facet Formation in Selective Silicon Epitaxial Growth,” 24 Jap. J. Appl. Phys. 10, pp. 1267-1269 (1985).Applicant
Jing Wang et al., “Fabrication of patterned sapphire substrate by wet chemical etching for maskless lateral overgrowth of GaN,” J. Electrochemical Soc'y, v. 153, n. 3, Mar. 2006, pp. C182-C185.Applicant
Ju, W. et al. , “Epitaxial lateral overgrowth of gallium nitride on silicon substrate,” J. Crystal Growth, v. 263, Mar. 1, 2004, p. 30-4.Applicant
Kamiyama, S. et al., “UV laser diode with 350.9-nm-lasing wavelength grown by hetero-epitaxial-lateral overgrowth technology,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, No. 5, pp. 1069-1073, Sep.-Oct. 2005.Applicant
Kamiyama, S. et al., “UV light-emitting diode fabricated on hetero-ELO-grown Al0.22Ga0.78N with low dislocation density,” Physica Status Solidi A, v 192, n 2, Aug. 2002, pp. 296-300.Applicant
Kazi et al., “Realization of GaAs/AIGaAs Lasers on Si Substrates Using Epitaxial Lateral Overgrowth by Metalorganic Chemical Vapor Deposition,” Jpn. J. Appl. Physics, vol. 40 (2001), pp. 4903-4906.Applicant
Kidoguchi, I. et al., “Air-bridged lateral epitaxial overgrowth of GaN thin films,” Applied Physics Letters, v 76, n 25, Jun. 19, 2000, pp. 3768-3770.Applicant
Kimura et al., “Vibronic Fine Structure Found in the Blue Luminescence from Silicon Nanocolloids,” Jpn. J. Appl. Physics, vol. 38 (1999), pp. 609-612.Applicant
Klapper, “Generation and Propagation of Dislocations During Crystal Growth,” Mat. Chem. and Phys. 66, pp. 101-109 (2000).Applicant
Knall et al., Threading Dislocations in GaAs Grown with Free Sidewalls on Si mesas, J Vac. Sci. Technol. B, vol. 12, No. 6, (Nov./Dec. 1994) pp. 3069-3074.Applicant
Krost et al., “GaN-based Optoelectronics on Silicon Substrates,” Mat. Sci. & Engineering, B93 (2002) pp. 77-84.Applicant
Kushida, K. et al., “Epitaxial growth of PbTiO3 films on SrTiO3 by RF magnetron sputtering,” Ultrasonics, IEEE Transactions on Ferroelectrics and Frequency Control, vol. 38, No. 6, pp. 656-662, Nov. 1991.Applicant
Kwok K Ng, Complete Guide to Semiconductor Devices, 2nd ed., Chapter 18 (2002).Applicant
Langdo et al., “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, vol. 76, No. 25 (Jun. 19, 2000), pp. 3700-3702.Applicant
Langdo, “Selective SiGe Nanostructures,” Ph.D. Thesis, Massachusetts Institute of Technology (2001).Applicant
Lee et al., “Strained-relieved, Dislocation-free InxGa1-xAs/GaAs(001) Heterostructure by Nanoscale-patterned Growth,” Applied Physics Letters, vol. 85, No. 18 (Nov. 1, 2004), pp. 4181-4183.Applicant
Lee, S.C. et al., “Growth of GaN on a nanoscale periodic faceted Si substrate by metal organic vapor phase epitaxy,” 2003 International Symposium on Compound Semiconductors: Post-Conference Proceedings, pp. 15-21.Applicant
Li et al, “Heteropitaxy of High-quality Ge on Si by Nanoscale Ge seeds Grown through a Thin Layer of SiO2,” Applied Physics Letters, vol. 85, No. 11 (Sep. 13, 2004), pp. 1928-1930.Applicant
Li et al., “Defect Reduction of GaAs Epitaxy on Si (001) Using Selective Aspect Ratio Trapping,” 91 Applied Physics Letters 021114-1-021114-3 (2007).Applicant
Li et al., “Morphological Evolution and Strain Relaxation of Ge Islands Grown on Chemically Oxidized Si(100) by Molecular-beam Epitaxy,” J. Applied Physics, vol. 98, (2005), pp. 073504-1-073504-8.Applicant
Li et al., “Selective Growth of Ge on Si(100) through vias of SiO2 Nanotemplate Using Solid Source Molecular Beam Epitaxy,” Applied Physics Letters, vol. 83, No. 24 (Dec. 15, 2003), pp. 5032-5034.Applicant
Liang et al., “Critical Thickness Enhancement of Epitaxial SiGe films Grown on Small Structures,” Journal of Applied Physics, vol. 97, (2005) pp. 043519-1-043519-7.Applicant
Lim et al., “Facet Evolution in Selective Epitaxial Growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition,” J. Vac. Sci. Tech. B 22(2), p. 682 (2004).Applicant
Liu et al., “High Quality Single-crystal Ge on Insulator by Liquid-phase Epitaxy on Si Substrates,” Applied Physics Letters, vol. 84, No. 14, (Apr. 4, 2004) pp. 2563-2565.Applicant
Liu et al., “Rapid Melt Growth of Germanium Crystals with Self-Aligned Microcrucibles on Si Substrates,” J. Electrochemical Soc'y, vol. 152, No. 8, (2005) pp. G688-G693.Applicant
Loo et al., “Successful Selective Epitaxial Si1-x Gex Deposition Process for HBT-BiCMOS and high Mobility Heterojunction pMOS Applications,” 150 J. Electrochemical Soc'y 10, pp. G638-G647 (2003).Applicant
Lourdudoss, S. et al., “Semi-insulating epitaxial layers for optoelectronic devices,” 2000 IEEE International Semiconducting and Insulating Materials Conference, pp. 171-178.Applicant
Luan et al., “High-quality Ge Epilayers on Si with Low Threading-dislocation Densities,” Applied Phsics Letters, vol. 75, No. 19, (Nov. 8, 1999) pp. 2909-2911.Applicant
Luan, “Ge Photodectors for Si Microphotonics,” Ph.D. Thesis, Massachusetts Institute of Technology, Feb. 2001.Applicant
Lubnow et al., “Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits,” Jpn. J. Applied Phys., vol. 33 (1994) pp. 3628-3634.Applicant
Luryi et al., “New Approach to the High Quality Epitaxial Growth of Latticed-mismatch Materials,” Appl. Phys. Lett., vol. 49, No. 3, (Jul. 21, 1986) pp. 140-142.Applicant
Martinez et al., “Characterization of GaAs Conformal Layers Grown by Hydride Vapour Phase Epitaxy on Si Substrates by Microphotoluminescence Cathodoluminescence and microRaman,” J. Crystal Growth, vol. 210 (2000) pp. 198-202.Applicant
Matsunaga et al., “A New Way to Achieve Dislocation-free Heteroepitaxial Growth by Molecular Beam Epitaxy: Vertical Microchannel Epitaxy,” J. Crystal Growth, 237-239 (2002) pp. 1460-1465.Applicant
Monroy et al., “High UV/visible contrast photodiodes based on epitaxial lateral overgrown GaN layers,” Electronics Letters , vol. 35, No. 17, pp. 1488-1489, Aug. 19, 1999.Applicant
Nakano, K. et al., “Epitaxial lateral overgrowth of AIN layers on patterned sapphire substrates,” Source: Physica Status Solidi A, v 203, n 7, May 2006, p. 1632-35.Applicant
Nam et al., “Lateral Epitaxy of Low Defect Density GaN Layers via Organometallic Vapor Phase Epitaxy,” Appl. Phys. Letters, vol. 71, No. 18, (Nov. 3, 1997) pp. 2638-2640.Applicant
Naoi et al, “Epitaxial Lateral Overgrowth of GaN on Selected-area Si(111) Substrate with Nitrided Si Mask,” Journal of Crystal Growth, vol. 248, (2003) pp. 573-577.Applicant
Naritsuka et al., “InP Layer Grown on (001) Silicon Substrate by Epitaxial Lateral Overgrowth,” Jpn. J. Appl. Physics, vol. 34 (1995), pp. L1432-L1435.Applicant
Naritsuka et al., “Vertical Cavity Surface Emitting Laser Fabricated on GaAs Laterally Grown on Si Substrate,” Electrochemical Soc'y Proc. vol. 97-21, pp. 86-90.Applicant
Neudeck et al., “Novel silicon epitaxy for advanced MOSFET devices,” Electron Devices Meeting, 2000 IEDM Technical Digest, pp. 169-172.Applicant
Norman, A.G. et al., “Characterization of MOCVD lateral epitaxial overgrown III-V semiconductor layers on GaAs substrates,” Int'l Symposium on Compound Semiconductors, pp. 45-46, Aug. 25-27, 2003.Applicant
Parillaud et al, “High Quality InP on Si by Conformal Growth,” Appl. Phys. Lett., vol. 68, No. 19 (May 6, 1996) pp. 2654-2656.Applicant
Park et al., “Defect Reduction and Its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using Aspect Ratio Trapping,” Mat. Res. Soc'y Symp. Proc., vol. 994 (2007).Applicant
Park et al., “Defect Reduction of Selective Ge Epitaxy in Trenches on Si(001) Substrates using Aspect Ratio Trapping,” 90 Appl. Physics Letters (2007).Applicant
Park et al., “Growth of Ge Thick Layers on Si(001) Substrates Using Reduced Pressure Chemical Vapor Deposition,” 45 Japanese J. Applied Physics 11, pp. 8581-8585 (2006).Applicant
Partial International Search for International Application No. PCT/US2006/033859, 7 pages.Applicant
Piffault, N. et al., “Assessment of the strain of InP films on Si obtained by HVPE conformal growth,” Sixth Int'l Conference on Indium Phosphide and Related Materials, Conf. Proc., pp. 155-158, Mar. 27-31, 1994.Applicant
Pribat et al., “High Quality GaAs on Si by Conformal Growth,” Appl. Phys. Lett., vol. 60, No. 17 (Apr. 27, 1992) pp. 2144-2146.Applicant
Reed et al., “Realization of a three-terminal resonant tunneling device: the bipolar quantum resonant tunneling transistor,” 54 Appl. Phys. Letters 11, p. 1034 (1989).Applicant
Ren, D. et al., “Low-dislocation-density, nonplanar GaN templates for buried heterostructure lasers grown by lateral epitaxial overgrowth,” Applied Physics Letters, v 86, Mar. 14, 2005, 111901-1-111901-3.Applicant
Rim et al., “Fabrication and mobility characteristics of ultra-thin strained Si Directly on Insulator (SSDOI) MOSFETs,” 2003 IEDM Tech. Dig., pp. 49-52.Applicant
Ringel et al., “Single-junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers,” Prog. Photovolt.: Res. & Appl. 2002; 10:417-426.Applicant
Sakai, “Defect Structure in Selectively Grown GaN films with low threading dislocation density,” Appl. Physics Letters 71(16), pp. 2259-2261 (1997).Applicant
Sakai, “Transmission electron microscopy of defects in GaN films formed by epitaxial lateral overgrowth,” 73 App. Physics Letters 4, pp. 481-483 (1998).Applicant
Sakawa et al., “Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate,” Jpn. J. Appl. Physics, vol. 31 (1992), pp. L359-L361.Applicant
Sangwoo Pae et al., “Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth,” Electron Device Letters, vol. 20, No. 5, pp. 194-196, May 1999.Applicant
Schaub, J.D. et al., “Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth,” Photonics Technology Letters, vol. 11, No. 12, pp. 1647-1649, Dec. 1999.Applicant
Seabaugh et al., “Promise of Tunnel Diode Integrated Circuits,” Tunnel Diode and CMOS/HBT Integration Workshop, Dec. 9, 1999, Naval Research Laboratory.Applicant
Shahidi, G. et al., “Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing,” 1990 IEDM Tech. Dig., pp. 587-590.Applicant
Siekkinen, J.W. et al., “Selective epitaxial growth silicon bipolar transistors for material characterization,” IEEE Transactions on Electron Devices, vol. 35, No. 10, pp. 1640-1644, Oct. 1988.Applicant
Su et al., “Catalytic Growth of Group III-nitride Nanowires and Nanostructures by Metalorganic Chemical Vapor Deposition,” Applied Physics Letters, vol. 86 (2005) pp. 013105-1-013105-3.Applicant
Su et al., “New planar self-aligned double-gate fully-depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D),” IEEE International SOI Conference, 2000, pp. 110-111.Applicant
Sun, Y. et al., “Temporally resolved growth of InP in the openings off-oriented from [110] direction,” 2000 Int'l Conference on Indium Phosphide and Related Materials, Conf. Proc., pp. 227-230.Applicant
Sun, Y.T. et al., “InGaAsP multi-quantum wells at 1.5 μm wavelength grown on indium phosphide templates on silicon,” 2003 Int'l Conference on Indium Phosphide and Related Materials, pp. 277-280.Applicant
Sun, Y.T.; Lourdudoss, S., “Sulfur doped indium phosphide on silicon substrate grown by epitaxial lateral overgrowth,” 2004 Int'l Conference on Indium Phosphide and Related Materials, pp. 334-337.Applicant
Sun, Y.T.; Napierala, J.; Lourdudoss, S., “Selective area growth of InP on InP precoated silicon substrate by hydride vapor phase epitaxy,” 2002 Int'l Conference on Indium Phosphide and Related Materials, pp. 339-342.Applicant
Suryanarayanan, G. et al., “Microstructure of lateral epitaxial overgrown InAs on (100) GaAs substrates,” Applied Physics Letters, v 83, n 10, Sep. 8, 2003, pp. 1977-1979.Applicant
Takasuka et al., “AlGaAs/InGaAs DFB Laser by One-Time Selective MOCVD Growth on a Grating Substrate,” 43 Jap. J. App. Phys. 4B (2004) pp. 2019-2022.Applicant
Takasuka et al., “InGaAs/AIGaAs Quantum Wire DFB Buried HeteroStructure Laser Diode by One-Time Selective MOCVD on Ridge Substrate,” 44 Jap. J. App. Phys. 4B (2005) pp. 2546-2548.Applicant
Tamura et al., “Threading Dislocations in GaAs on Pre-patterned Si and in Post-patterned GaAs on Si,” J. Crystal Growth, vol. 147, (1995) pp. 264-273.Applicant
Tanaka et al., “Structural Characterization of GaN Laterally Overgrown on a (111) Si Substrate,” Applied Physics Letters, vol. 79, No, 7 (Aug. 13, 2001) pp. 955-957.Applicant
Tomiya, S. et al.., “Dislocation related issues in the degradation of GaN-based laser diodes,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 10, No. 6, pp. 1277-1286, Nov.-Dec. 2004.Applicant
Tran et al., “Growth and Characterization of InP on Silicon by MOCVD,” J. Crystal Growth, vol. 121, (1992) pp. 365-372.Applicant
Tsang, W. et al., “The heteroepitaxial ridge-overgrown distributed feedback laser,” IEEE Journal of Quantum Electronics, vol. QE-21, No. 6, pp. 519-526, Jun. 1985.Applicant
Tsaur, B.-Y. et al., “Low-dislocation-density GaAs epilayers grown on Ge-coated Si substrates by means of lateral epitaxial overgrowth,” Applied Physics Letters, v 41, n 4, Aug. 15, 1982, pp. 347-49.Applicant
Tseng et al., “Effects of Isolation Materials on Facet Formation for Silicon Selective Epitaxial Growth,” 71 Appl. Phys. Letters 16, p. 2328 (1997).Applicant
Tsuji et al., “Selective Epitaxial Growth of GaAs on Si with Strained Sort-period Superlattices by Molecular Beam Epitaxy under Atomic Hydrogen Irradiation,” J. Vac. Sci. Technol. B., vol. 22, No. 3, (May/Jun. 2004) pp. 1428-1431.Applicant
Vanamu et al., “Epitaxial Growth of High-quality Ge Films on Nanostructured Silicon Substrates,” Applied Physics Letters, vol. 88, (2006) pp. 204104-1-204104-3.Applicant
Vanamu et al., “Growth of High Quality Ge/Si1-xGex on Nano-scale Patterned Si Structures,” J. Vac. Sci. Techn. B, vol. 23, No. 4, (Jul./Aug. 2005) pp. 1622-1629.Applicant
Vanamu et al., “Heteroepitaxial Growth on Microscale Patterned Silicon Structures,” J. Crystal Growth, vol. 280, (2005) pp. 66-74.Applicant
Vanamu et al., “Improving Ge/SixGe1-x Film Quality through Growth onto Patterned Silicon Substrates,” Advances in Electronics Manufacturing Technology, V-EMT 1:25 (Nov. 8, 2004), pp. 1-4.Applicant
Vetury et al., “First Demonstration of AIGaN/GaN Heterostructure Field Effect Transistor on GaN grown by lateral epitaxial overgrowth (ELO),” Inst. Phys. Conf. Ser. No. 162: Ch. 5, pp. 177-183.Applicant
Wemersson et al., “InAs Epitaxial Lateral growth of W Marks,” J. Crystal Growth, vol. 280 (2005) pp. 81-86.Applicant
Wuu, D.S. et al., “Defect reduction and efficiency improvement of near-ultraviolet emitters via laterally overgrown GaN on a GaN/patterned sapphire template,” Applied Physics Letters, v 89, n 16, Oct. 16, 2006, pp. 161105-1-161105-3.Applicant
Xie et al., “From Porous Si to Patterned Si Substrate: Can Misfit Strain Energy in a Continuous Heteroepitaxial Film Be Reduced?” J Va. Sci. Technol. B, vol. 8, No. 2, (Mar./Apr. 1990) pp. 227-231.Applicant
Xu et al., “Spin-filter devices based on resonant tunneling antisymmetrical magnetic semiconductor hybrid structures,” 84 App. Phys. Letters 11, pp. 1955-1957 (2004).Applicant
Yamaguchi et al., “Analysis for Dislocation Density Reduction in Selective Area Grown GaAs Films on Si Substrates,” Appl. Phys. Lett. vol. 56, No. 1, (Jan. 1, 1990) pp. 27-29.Applicant
Yamaguchi et al., “GaAs Solar Cells Grown on Si Substrates for Space Use,” Prog. Photovolt.: Res. Appl. 2001; 9:191-201.Applicant
Yamaguchi et al., “Super-high-efficiency Multi-junction Solar Cells,” Prog. Photovolt.: Res. Appl. 2005; 13:125-132.Applicant
Yamaguchi et al., “Defect Reduction Effects in GaAs on Si Substrates by Thermal Annealing,” Appl. Phys. Letters 53(23), p. 2293 (1998).Applicant
Yamamoto et al., “Optimization of InP/Si Heteroepitaxial Growth Conditions Using Organometallic Vapor Phase Epitaxy,” J. Crystal Growth, vol. 96, (1989) pp. 369-377.Applicant
Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” 2003 IEDM Tech. Dig., pp. 453-456.Applicant
Yang et al., “Selective Area Deposited Blue GaN-InGaN Multiple-quantum Well Light Emitting Diodes over Silicon Substrates,” Applied Physics Letter, vol. 76, No. 3, (Jan. 17, 2000) pp. 273-275.Applicant
Yoon et al., “Selective Growth of Ge Islands on Noanometer-scale Patterned SiO2/Si Substrate by Molecular Beam Epitaxy,” Applied Physics Letters, vol. 89 (2006) pp. 063107-1-063107-3.Applicant
Zamir et al., “Thermal Microcrack Distribution Control in GaN Layers on Si Substrates by Lateral Confined Epitaxy,” Applied Physics Letters, vol. 78, No. 3, (Jan. 15, 2001) pp. 288-290.Applicant
Zang, K.Y. et al., “Nanoheteroepitaxial lateral overgrowth of GaN on nanoporous Si(111),” Applied Physics Letters, v 88, n 14, Apr. 3, 2006, p. 141925.Applicant
Zang, K.Y. et al., “Nanoscale lateral epitaxial overgrowth of GaN on Si (111),” Applied Physics Letters, v 87, Nov. 7, 2005, p. 193106-1-193106-3.Applicant
Zela et al., “Single-crystalline Ge Grown Epitaxially on Oxidized and Reduced Ge/Si (100) Islands,” J. Crystal Growth, vol. 263 (2004) pp. 90-93.Applicant
Zhang et al., “Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors by Glide to Sidewalls,” J. Electronic Materials, vol. 27, No. 11, (1998) pp. 1248-1253.Applicant
Zhang et al., “Strain Status of Self-assembled InAs Quantum Dots,” Applied Physics Letters, vol. 77, No. 9, (Aug. 28, 2000) pp. 1295-1297.Applicant
Zheleva, T.S.; Ok-Hyun Nam; Ashmawi, W.M.; Griffin, J.D.; Davis, R.F., “Lateral epitaxy and dislocation density reduction in selectively grown GaN structures,” J. Crystal Growth, v 222, n 4, Feb. 2001, pp. 706-718.Applicant
Zubia et al., “Initial Nanoheteroepitaxial Growth of GaAs on Si(100) by OMVPE.” J. Electronic Materials, vol. 30, No. 7, (2001) pp. 812-816.Applicant
Intel Press Release, “Intel's Tri-Gate Transistor to Enable Next Era in Energy-Efficient Performance,” Intel Corporation (Jun. 12, 2006).Applicant
Hammerschmidt, “Intel to Use Trigate Transistors from 2009 on,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=189400035 (Jun. 12, 2006).Applicant
Lammers, “Trigate and High-kstack up vs. planar,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=188703323&pgno=2&printable=true (Jun. 12, 2006).Applicant
Intel to Develop Tri-Gate Transistors Based Processors, available at: http://news.techwhack.com/3822/tri-gate-transistors/ (Jun. 13, 2006).Applicant
Ames, “Intel Says More Efficient Chips are Coming,” PC World, available at: http://www.pcworld.com/printable/article/id,126044/printable.html (Jun. 12, 2006).Applicant
Bergman et al., “RTD/CMOS Nanoelectronic Circuits: Thin-Film InP-based Resonant Tunneling Diodes Integrated with CMOS circuits,” 20 Electron Device Letters 3, pp. 119-122 (1999).Applicant
Cloutier et al., “Optical gain and stimulated emission in periodic nanopatterned crystalline silicon,” Nature Materials, Nov. 2005.Applicant
Feng et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” 27 Electron Device Letters 11, pp. 911-913 (2006).Applicant
Fischer et al., “Elastic stress relaxation in SiGe epilayers on patterned Si substrates,” 75 Journal of Applied Physics 1, pp. 657-659 (1994).Applicant
Fischer et al., “State of stress and critical thickness of Strained small-area SiGe layers,” Phys. Stat. Sol. (a) 171, pp. 475-485 (1999).Applicant
Fitzgerald et al., “Structure and recombination in InGaAs/GaAs heterostructures,” 63 Journal of Applied Physics 3, pp. 693-703 (1988).Applicant
Fitzgerald et al., “Totally relaxed GexSi1-x layers with low threading dislocation densities grown on Si Substrates,” 59 Applied Physics Letters 7, pp. 811-813 (1991).Applicant
Gibbon et al., “Selective-area low-pressure MOCVD of GaInAsP and related materials on planar InP substrates” Semicond Sci Tech. 8, pp. 998-1010 (1993).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US2006/019152, dated Nov. 20, 2007.Applicant
International Search Report and Written Opinion for International Application PCT/US2007/007373, dated Oct. 5, 2007.Applicant
Ismail et al., “High-quality GaAs on sawtooth-patterned Si substrates,” 59 Applied Physics Letters 19, pp. 2418-2420 (1991).Applicant
Jain et al., “Stresses in strained GeSi stripes and quantum structures: calculation using the finite element method and determination using micro-Raman and other measurements,” Thin Solid Films 292 (1997) pp. 218-226.Applicant
Neumann et a., “Growth of III V resonant tunneling diode,” J. of Crystal Growth (2003).Applicant
Prost, W., ed. QUDOS Technical Report 2002-2004.Applicant
Sun et al., “Thermal strain in Indium Phosphide on silicon obtained by Epitaxial Lateral Overgrowth,” 94 J. of Applied Physics 4, pp. 2746-2748 (2003).Applicant
Usuda et al., “Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation,” Applied Surface Sci. 224, pp. 113-116 (2004).Applicant
Usui et al., “Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitazy,” 36 Jap. J. of Applied Physics, pp. L899-L902 (1997).Applicant
Vescan et al., “Lateral confinement by low pressure chemical vapor deposition-based selective epitaxial growth of Si1-xGex/Si nanostructures,” 81 J. of Applied Physics 10, pp. 6709-6715 (1997).Applicant
Choi et al., “Monolithic Integration of Si MOSFET's and GaAs MESFET's,” Electron Device Letters, v. EDL-7, No. 4 (1986).Applicant
Choi et al., “Monolithic Integration of GaAs/AIGaAs Double-Heterostructure LED's and Si MOSFET's,” Electon Device Letters, v. EDL-7, No. 9 (1986).Applicant
Choi et al., “Monolithic Integration of GaAs/AIGaAs LED and Si Driver Circuit,” 9 Electron Device Letters 10 (1988).Applicant
Fiorenza et al., “Film Thickness Constraints for Manufacturable Strained Silicon CMOS,” 19 Semiconductor Sci. Technol., pp. L4 (2004).Applicant
Hu et al., “Growth of Well-Aligned Carbon Nanotube arrays on Silicon Substrates using Porous Alumina Film as a Nanotemplate,” 79 App. Physics Letters 19 (2001).Applicant
International Search Report and Written Opinion for International Application No. PCT/US2007/020181, dated Jan. 25, 2008.Applicant
International Search Report and Written Opinion for International Application No. PCT/US07/020777, mailed Feb. 8, 2008.Applicant
International Search Report and Written Opinion for International Application No. PCT/US2007/019568, mailed Feb. 6, 2008.Applicant
Rosenblad et al., “A Plasma Process for Ultrafast Deposition of SiGe Graded Buffer Layers,” 76 Applied Physics Letters 4, pp. 427-429 (2000).Applicant
Shichijo et al., “Co-Integration of GaAs MESFET & Si CMOS Circuits,” 9 Elec. Device. Letters 9 (1988).Applicant
Tamura et al., “Heteroepitaxy on high-quality GaAs on Si for Optical Interconnections on Si Chip,” Proceedings of the SPIE, vol. 2400, pp. 128-139 (1995).Applicant
IPRP for International Application No. PCT/US2006/029247, mailed Feb. 7, 2008.Applicant
Bean et al., “GexSi1-x/Si strained-later superlattice grown by molecular beam epitaxy,” J. Vac. Sci. Tech. A (2)2, pp. 436-440 (1984).Applicant
Blakeslee, “The Use of Superlattices to Block the Propogation of Dislocations in Semiconductors,” Mat. Res. Soc. Symp. Proc. 148, pp. 217-227.Applicant
Currie et al., “Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates,” J. Vac. Sci. Tech. B 19(6), pp. 2268-2279 (2001).Applicant
Donaton et al., “Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure,” 2006 IEDM, pp. 465-468.Applicant
International Technology Roadmap for Semiconductors- Front End Processes, pp. 1-62 (2005).Applicant
IPRP for International Application No. PCT/US2006/033859, mailed Mar. 20, 2008.Applicant
Matthews et al., “Defects in Epitaxial Multilayers- Misfit Dislocations,” J. Crystal Growth 27, pp. 118-125(1974).Applicant
Pidin et al., “MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node,” 2004 Symp. On VLSI Technology, Dig. Tech. Papers, pp. 54-55.Applicant
Rim et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs,” 1995 IEDM, pp. 517-520.Applicant
Thean et al., “Uniaxial-Biaxial Hybridization for Super-Critical Strained-Si Directly on Insulator (SC-SSSOI) PMOS with Different Channel Orientations,” IEEE, pp. 1-4 (2005).Applicant
Thompson et al., “A Logic Nanotechnology Featuring Strained-Silicon,” 25 IEEE Electron Device Letters 4, pp. 191-193 (2004).Applicant
Yin et al., “Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and FET Performance,” 52 IEEE Trans. on Electron Devices 10, pp. 2207-2214 (2005).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US2007/019568, mailed Mar. 19, 2009 (7 pages).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US07/021023, mailed Apr. 9, 2009 (8 pages).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US2007/020181, mailed Apr. 2, 2009 (9 pages).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US07/020777, mailed Apr. 9, 2009 (12 pages).Applicant
International Search Report and Written Opinion for International Application No. PCT/US07/022392, mailed Apr. 11, 2008 (20 pages).Applicant
Examination Report in European Patent Application No. 06800414.2, mailed Mar. 5, 2009 (3 pages).Applicant
Partial International Search Report for International Application No. PCT/US2008/068377, mailed Apr. 7, 2009 (7 pages).Applicant
Bogumilowicz et al., “Chemical vapour etching of Si, SiGe and Ge with HCI; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations,” Semicond. Sci. & Tech. 20, pp. 127-134 (2005).Applicant
Campo et al., “Comparison of etching processes of silicon and germanium in SF6 -O2 radio-frequency plasma, ” 13 J. Vac. Sci. Tech. B 2, pp. 235-241 (1995).Applicant
International Preliminary Report on Patentability for International Application No. PCT/US07/022392, mailed Apr. 30, 2009 (14 pages).Applicant
International Search Report and Written Opinion for International Application No. PCT/US2008/068377, mailed Jul. 6, 2009 (19 pages).Applicant
Oehrlein et al., “Studies of the reactive ion etching of SiGe alloys, ” 9 J. Vac. Sci. Tech. A 3, pp. 768-774 (1991).Applicant
Partial International Search Report for International Application No. PCT/US2008/004564, mailed Jul. 30, 2009 (9 pages).Applicant
Williams et al., “Etch rates for micromachining processing, ” 5 J. Microelectromechanical Sys, 4, pp. 256-269 (1996).Applicant
Williams et al., “Etch rates for micromachining processing—Part II, ” 12 J. Microelectromechanical Sys. 6, pp. 761-777 (2003).Applicant

Abstract