US 6,867,433 B2Grant
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
Issue Date:2005-03-15
•69 Claims
•10 Drawing Sheets
Abstract
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
Metadata
Assignee
- Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors
- Yee-Chia Yeo
- How-Yu Chen
- Chien-Chao Huang
- Wen-Chin Lee
- Fu-Liang Yang
- Chenming Hu
Application Information
Application Number:US 10/426,566
Filing Date:2003-04-30
Priority Date:2003-04-30
Art Unit:2815
Patent Drawings (10 sheets)
Description
Cross-Reference to Related Applications
[00002] The following U.S. patents and/or commonly assigned patent applications are hereby incorporated herein by reference:
[00002]
| U.S. Pa. No. or | Attorney | ||
|---|---|---|---|
| Ser. No. | Filing Date | Issue Date | Docket No. |
| 10/305,841 | Nov. 26, 2002 | TSMC2002-0895 | |
| 10/319,119 | Dec. 12, 2002 | TSMC2002-0979 | |
| 10/379,873 | Mar. 5, 2003 | TSMC2002-1384 | |
| 10/384,859 | Mar. 10, 2003 | TSMC2002-1385 | |
Technical Field
[00003] The present invention relates generally to the fabrication of semiconductor devices. More particularly, the preferred embodiment of the present invention relates to semiconductor-on-insulator chips incorporating partially-depleted, fully-depleted, and multiple-gate devices, and the introduction of strain in the channel of these devices.
Background
[00004] Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's semiconductor fabrication plants are routinely producing devices having 130 nm and even 90 nm feature sizes.
[00005] The desire for higher performance circuits has driven the development of high-speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. In SOI technology, metal-oxide semiconductor field-effect transistors (MOSFETs) are formed on a thin layer of silicon overlying a layer of insulating material such as silicon oxide. Devices formed on SOI offer many advantages over their bulk counterparts, including reduced junction capacitance, absence of reverse body effect, soft-error immunity, full dielectric isolation, and absence of latch-up. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
[00006] There are two types of conventional SOI devices: partially-depleted SOI (PD-SOI) devices, and fully-depleted (FD-SOI) devices. Conventional PD-SOI MOSFET is one in which the body thickness is thicker than the maximum depletion layer width Wd,max, and a conventional FD-SOI MOSFET is one in which the body thickness is thinner than Wd,max. The conventional PD-SOI and FD-SOI devices are planar devices, i.e., they are formed in the plane of the wafer.
[00007] It is noticed that remarkable progress has recently been achieved in PD-SOI technology. Although PD-SOI devices have the merit of being highly manufacturable, significant design burdens are faced by its users because of floating body effects. In PD-SOI devices, charge carriers generated by impact ionization near one source/drain region accumulate near the other source/drain region of the transistor. When sufficient carriers accumulate in the floating body, which is formed right below the channel region, the body potential is effectively altered.
[00008] Floating body effects occur in PD-SOI devices because of charge build-up in the floating body region. This results in kinks in the device current-voltage (I-V) curves, thereby degrading the electrical performance of the circuit. In general, the body potential of a PD-SOI device may vary during static, dynamic, or transient device operation, and is a function of many factors like temperature, voltage, circuit topology, and switching history. Therefore, circuit design using PD-SOI devices is not straightforward, and there is a significant barrier for the adoption of PD-SOI technology or the migration from bulk-Si design to PD-SOI design.
[00009] One traditional way to suppress floating body effects in PD-SOI devices is to provide an extra electrical connection to the body by adding a contact to the body for collection of current due to impact ionization. Various methods of making a contact to the body of a SOI transistor are known, but various disadvantages are known to be associated with these methods. One method for the suppression of the SOI floating-body effects is to use a linked-body device structure. However, the method is limited by a high body contact resistance.
[00010] Blake et al., in U.S. Pat. No. 4,946,799, described a process for making a body node to source node connection, where a contact region of the same conductivity type as the body node is formed within the source region in a self-aligned fashion, thus eliminating the floating body effects. In U.S. Pat. No. 6,387,739 issued to G. E. Smith III et al., a method for forming a body contact structure for SOI transistor is described.
[00011] Another way of avoiding floating body effects in SOI devices is to adopt a fully-depleted SOI (FD-SOI) technology. FD-SOI devices do not suffer from floating-body effects due to the fact that the body is fully-depleted. FD-SOI technology is therefore design-friendly since floating-body effects need not be accounted for in circuit design.
[00012] In a FD-SOI technology, devices with a low body-doping and/or a thin body thickness are used. Additionally, for good control of short-channel effects in ultra-scaled devices, the device body thickness is usually reduced to less than one third of gate length. Such a thin body thickness would require raised source/drain technology for series resistance reduction. However, raised source/drain formation, currently performed by selective epitaxy, is immature, expensive, pattern-density dependent, and may result in reduced manufacturing yield. In addition, SOI substrates with uniform ultra-thin Si films, as required for the manufacture of FD-SOI devices with ultra-thin body, are currently unavailable. Non-uniformity of the Si film thickness will result in significant fluctuations in the device characteristics and negatively impact the ease of manufacture.
[00013] U.S. Pat. No. 6,222,234, issued to K. Imai, describes a method for the fabrication of FD-SOI and PD-SOI devices on the same substrate. U.S. Pat. No. 6,414,355 issued to An et al. described the structure of silicon-on-insulator chips with an active layer of non-uniform thickness. U.S. Pat. No. 6,448,114 issued to An et al. described several methods of forming silicon-on-insulator chips with an active layer of non-uniform thickness. In these three patents, a SOI substrate with two different silicon film thicknesses is provided, where the FD-SOI devices reside in a region with a thinner silicon film, and the PD-SOI devices reside in a region with a thicker silicon film.
[00014] FIG. 2 illustrates a prior art integration of FD-SOI and PD-SOI transistors in the same chip, where FD-SOI transistors 12 are formed in a thin silicon layer 14 and PD-SOI transistors 16 are formed in thick silicon layer 18. The silicon layers 16 and 18 are both formed directly on a buried oxide 20, which is directly on a silicon substrate 22. Active areas 24 within the silicon layers 16 and 18 are separated from one another by isolation regions 26.
[00015] Other techniques have also been used to enhance transistor performance. For example, strain may be introduced in the transistor channel for improving carrier mobilities. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling.
[00016] In one approach, strain in the channel is introduced after the transistor is formed. In this approach, a high stress film 32 is formed over a completed transistor structure 30, as shown in FIG. 1. The stressor 32, i.e., the high stress film, exerts significant influence on the channel 34, modifying the silicon lattice spacing in the channel region 34, and thus introducing strain in the channel region 34. As shown in FIG. 1 , the stressor is placed above the complete planar transistor structure, which includes a source 34 and a drain 38 formed in silicon region 40. A gate 42 overlies channel region 34 and is separated therefrom by gate dielectric 44. Sidewall spaces 46 can be included adjacent gate 42. This scheme is described in detail in a paper by A. Shimizu et al., entitled “Local mechanical stress control (LMC): a new technique for CMOS performance enhancement,” published in pp. 433-436 of the Digest of Technical Papers of the 2001 International Electron Device Meeting. The strain contributed by the high stress film is believed to be uniaxial in nature with a direction parallel to the source-to-drain direction.
Summary of the Invention
[00017] In one embodiment, the present invention provides a method and system that overcomes the shortcomings of the prior art, and provides a highly manufacturable PD-SOI-like technology that produces FD-SOI type devices to eliminate floating body effects. Other embodiments of the invention provide a novel transistor geometry to magnify the effect of high-stress film on the channel strain. The present disclosure teaches a method of forming such a transistor.
[00018] In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
[00019] In accordance with another preferred embodiment of the present invention, an SOI chip including a multiple-gate fully-depleted SOI MOSFET has an insulator layer and a silicon fin overlying a portion of the insulator layer. A strained channel region formed in a portion of the silicon fin and a gate dielectric layer overlying the strained channel region is also included. A gate electrode is formed on the gate dielectric layer and a source region and a drain region is formed on portions of the semiconductor fin adjacent to the strained channel region, such that the source region is separated from the drain region by the strained channel region.
[00020] Another embodiment provides a method of forming a silicon-on-insulator device with a strained channel. In this method a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer is provided. At least one active region is defined in the silicon layer. A gate dielectric layer is formed in the active region and a gate electrode is formed on the gate dielectric layer. Source and drain regions can then be formed adjacent to the gate electrode and a high-stress film covers the gate electrode, source region, and drain region.
[00021] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
Brief Description of the Drawings
[00022] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
[00023] FIG. 1 shows a prior art planar transistor with a strained channel;
[00024] FIG. 2 shows a prior art integration of PD-SOI and FD-SOI transistors in the same chip by using a silicon-on-insulator wafer with multiple-thickness silicon layer thicknesses;
[00025] FIGS. 3 a-3d illustrate partially depleted SOI transistors and a fully depleted SOI transistors of the present invention;
[00026] FIGS. 4 a and 4b each provide a map showing the region of PD-SOI, FD-SOI, and multiple-gate transistors as a function of width Wand length Lg for NMOS (FIG. 4 a) and PMOS (FIG. 4 b) transistors;
[00027] FIG. 5 shows the three-dimensional perspective of a strained-channel multiple-gate transistor of one embodiment of the present invention;
[00028] FIGS. 6 a and 6b provide charts that show that the strain-induced drive current enhancement is increased as the channel width is reduced;
[00029] FIG. 7 shows the three-dimensional perspective of a strained-channel multiple-gate transistor where the silicon fin has rounded corners;
[00030] FIG. 8 a shows a top view of an active region or silicon fin;
[00031] FIGS. 8 b and 8c provide cross-sectional views of the active region or silicon fin showing the rounded corner with shallow trench (FIG. 8 b) isolation or with mesa isolation (FIG. 8 c);
[00032] FIG. 9 provides a chart that shows that the stress in channel increases with reduced silicon film thickness and reduced gate length;
[00033] FIG. 10 provides a chart that shows that the stress in channel increases with reduced spacer width and reduced gate length;
[00034] FIG. 11 shows a cross-section of the semiconductor-on-insulator starting material; and
[00035] FIGS. 12 a-12j provide cross-sections illustrating a process flow of one embodiment of the present invention.
Detailed Description of Illustrative Embodiments
[00036] The present invention is related to co-pending applications Ser. No. 10/305,841 entitled “Strained-Channel Multiple-Gate Transistor”, filed Nov. 26, 2002 and Ser. No. 10/319,119 entitled “Semiconductor-on-Insulator Chip Incorporating Partially-Depleted, Fully-Depleted, and Multiple-Gale Devices”, filed Dec. 12, 2002. Aspects of the present invention provide improvements.
[00037] For example, the preferred embodiment of the present invention teaches a method and architecture to incorporate partially-depleted SOI (PD-SOI) and fully-depleted SOI (FD-SOI) transistors in the same chip, and, to provide enhanced strain effects to improve carrier mobilities and device performance in ultra-scaled devices. Unlike other devices that utilize different silicon thicknesses to the achieve FD-SOI and PD-SOI transistors on the same chip, the preferred embodiment of the present invention employs a PD-SOI technology while implementing FD-SOI transistors by rearranging the transistor geometry, or by configuring the channel doping concentrations to achieve full transistor body depletion at selected channel lengths or channel widths. In this manner, it is possible to provide FD-SOI and PD-SOI transistors with similar silicon body thicknesses.
[00038] Two types of FD-SOI transistors are provided on the same chip: a planar FD-SOI type transistor where the depletion width is larger than the silicon thickness; and a non-planar multiple-gate transistor or FinFET-like FD-SOI transistor, which makes use of a novel device geometry to eliminate floating body effects. In general, planar FD-SOI transistors have widths of more than 50 nm while non-planar fully-depleted multiple-gate transistors have widths of less than 50 nm.
[00039] Concepts of the preferred embodiment of this invention are more clearly illustrated in FIGS. 3 a-3d. FIGS. 3 a-3d illustrate partially depleted SOI transistors and fully depleted SOI transistors of the present invention. The fully-depleted transistor of FIGS. 3 b uses a low body doping so that the maximum depletion width is larger than the silicon thickness to achieve full-depletion. The fully-depleted transistor of FIG. 3 d uses a novel geometry to allow the encroachment of gate electric field from the sides of the silicon body to achieve full body depletion.
[00040] Super-halo doping and light body doping are designed to achieve FD-SOI and PD-SOI devices at different gate lengths, as shown in FIGS. 3 a and 3b. Referring first to FIG. 3 a, a partially-depleted transistor device 100 is formed over a buried insulator 110, while not shown, the buried insulator 110 is formed over a substrate, e.g., an undoped or lightly doped silicon substrate.
[00041] The buried insulator 110 is typically an oxide such as silicon dioxide. Other insulators, such as silicon nitride or aluminum oxide, may alternatively be used. In some embodiments, the buried insulator can comprise a stack of layers, e.g., an oxide, nitride, oxide stack.
[00042] Transistor device 100 is formed in a semiconductor layer 112 and includes a source region 114 and a drain region 116. A gate 118 overlies a channel 120 and is separated therefrom by gate dielectric 122.
[00043] Similarly long-channel transistor 130 includes a source 132, a drain 134, a gate 136, and a gate dielectric 138. The transistor 130 can be formed in the same semiconductor layer 112 as transistor 100 or in a different semiconductor layer e.g., a different island or mesa on the same chips.
[00044] One feature is the design of the super-halo doping 140 in FIG. 3 b (or double halo doping 140 in FIG. 3 a) and light body doping 142 such that the effective doping concentration of the transistor body decreases as the gate length is increased. The doping concentration in the super-halo region 140 is in the range of about 1×1018 to about 2×1019 dopants per cubic centimeter. The doping concentration in the lightly doped body region 142 is in the range of about 1×1016 to about 1×1018 dopants per cubic centimeter.
[00045] In FIG. 3 a, the high super-halo doping concentration 140 in a short-channel transistor 100 results in a maximum depletion width that is smaller than the silicon film 112 thickness, and the transistor body is therefore partially-depleted. As the gate 118 length increases, an increasing portion of the body region is constituted by the lightly doped body region 142, and the effective body concentration decreases or the maximum depletion width increases. In FIG. 3 b, the long-channel transistor 130 has a light body-doping and a maximum depletion width that is larger than the silicon film 112 thickness, and the transistor body is fully-depleted.
[00046] Referring now to FIGS. 3 c and 3d, another way to achieve full depletion in the transistor body is to allow the electric field lines to encroach from the sides of the transistor body by using a novel transistor geometry. Referring now to FIG. 3 c, a transistor 150 is formed over a buried insulator. The buried insulator 152 can include any of the characteristics described above with respect to insulator 110 and may be formed on a substrate, where the discussion above with respect to FIGS. 3 a and 3b equally applies here. In this device, an active semiconductor layer region 155 includes a body region 154 and a depletion region 156. The active region 155 is isolated from the other active regions by isolation region 158. This isolation region 158 is preferably a shallow trench isolation (STI) region. It is understood that other isolation structures may be used.
[00047] A gate electrode 160 is formed to surround the transistor active region, e.g., the channel region. Accordingly, an intentional recess 162 is formed within the isolation region 158 so that the semiconductor layer 155 includes sidewalls. The gate electrode 160 is adjacent to the top surface as well as the sidewalls of active layer 155. A gate dielectric layer 164 is formed between the gate electrode 160 and the active layer 155.
[00048] The source and drain regions of the transistor device 150 are not shown in the illustration of FIG. 3 c. In this case, the channel current flows into and out of the page. As a result, one of the source/drain regions will be located in a plane above the page and the other located in a plane below the page.
[00049] FIG. 3 d shows a similar structure for a FinFET-like transistor device 170. Like elements from FIG. 3 c have been labeled with the same reference numerals. In this case, the active semiconductor layer is thin casing the body to be fully depleted.
[00050] One feature of the novel transistor geometry is the intentional recess 162 in the isolation region 158, as shown in FIGS. 3 c and 3d. The planar partially-depleted transistor 150 of FIG. 3 c has a width that is much bigger than the maximum depletion layer width Wd,max. When the active region width W(see FIG. 3 d) is reduced to less than twice the depletion width layer in the body, the gate field encroaches from the isolation edges and eliminates the undepleted body region, thereby making the device of FIG. 3 d fully depleted.
[00051] The resulting FD-SOI device has a non-planar geometry and is a multiple-gate transistor where the gate electrode 160 surrounds the transistor body 156 on multiple sides: the two sidewalls and the top surface. By having a gate electrode 160 that surrounds the transistor body 155, the multiple-gate transistor allows the encroachment of the gate electric field to the transistor body in the lateral direction, thus enhancing its ability to control short-channel effects.
[00052] The preferred embodiment of this invention teaches a unique way of incorporating PD-SOI and FD-SOI transistors on the same chip using the same process technology, with a distribution of FD-SOI and PD-SOI transistors according to transistor dimensions. FIGS. 4 a and 4b show the distribution of the PD-SOI and FD-SOI transistors according to the active region width Wand the transistor gate length Lg. FIG. 4 a provides data for NMOS devices and FIG. 4 b shows data for PMOS devices. These figures provide a map showing the region of PD-SOI transistors (gray region), conventional FD-SOI transistors (white region), and multiple-gate transistors (in region enclosed by dashed box) as a function of width Wand length Lg for NMOS and PMOS transistors.
[00053] Planar PD-SOI and FD-SOI transistors typically have active region width of more than 50 nm, while non-planar multiple-gate fully-depleted transistors generally have active region width of less than 50 nm. The results in FIG. 4 are obtained from an experiment where transistors are fabricated using a 65 nm PD-SOI-based process with a nominal gate length of 45 nm, a silicon body thickness of 40 nm, dual-doped poly-silicon gate electrodes, 14 angstroms nitrided gate oxide, and cobalt-silicided source/drain and gate.
[00054] The PD-SOI region is smaller for P-channel transistors (FIG. 4 b) than for N-channel transistors (FIG. 4 a) because the impact ionization induced parasitic bipolar action is weaker in P-channel transistors. The transition from PD- to FD-SOI occurs as the gate length is increased. In addition, the non-planar FinFET-like or multiple-gate transistors are obtained at small width W, typically less than 50 nm. Wide-channel devices with smaller gate length Lg are partially-depleted, showing a characteristic kink in the drain current IDS versus drain voltage VDS curves. As W is reduced, transition from PD-SOI to FD-SOI occurs and the characteristic IDS-VDS kink disappears.
[00055] It is clear that the advantages of PD-SOI and FD-SOI can be combined by using transistors with different combinations of W and Lg. For example, when converting a circuit design for bulk technology to a circuit design for SOI technology, critical portions of the circuits may employ FD-SOI devices to achieve minimal floating body effects while the remaining portions of the circuits may employ PD-SOI devices. For example, the critical portions of the circuits may include analog circuits and dynamic circuits.
[00056] The quasi-planar device structure or geometry of the multiple-gate FD-SOI transistor will now be described further. FIG. 5 illustrates a three-dimensional view of a multiple-gate FD-SOI transistor. The multiple-gate FD-SOI transistor has a gate electrode 160 on top of a gate dielectric layer 164 covering the two sidewalls as well as the top of a fin-like active region 155. The gate dielectric 164 straddles across the fin 155, wrapping around the fin 155 on the top surface 178 and the two sidewalls 176 of the fin or fin-like active region 155. The gate electrode 160 is formed on the gate dielectric 164, also wrapping around the fin-like active region 155. Effectively, the gate electrode 160 forms three gates in the multiple-gate device: a gate on the top surface 178 of the fin 155, and one gate on each of the two sidewalls 176 of the fin 155.
[00057] Shallow trench isolation filling materials 158 such as silicon oxide, as shown in FIG. 5 , may be used to fill the trenches surrounding the silicon fin 155. However, other isolation techniques, such as mesa isolation, as an example, may be used. When mesa isolation is used, no filling materials are used to fill the space surrounding the fin 155. It is noted that the source 172 and drain 174, which were not visible in the views shown in FIGS. 3 c and 3d, can now be seen.
[00058] FIG. 5 also shows the gate spacer 180 that surrounds the gate 160. The gate space has a spacer width 182. The gate also has a gate length 184, which determines the channel length of the transistor. The channel width is determined by the size of the exposed fin sidewalls 176 and top surface 178.
[00059] The novel transistor geometry according to this embodiment of the invention not only provides for the encroachment of electric field lines from the sides of the transistor to obtain full-body depletion and/or enhanced short-channel immunity, but also provides for enhanced strain effects. The enhancement of strain-induced transistor performance improvement provides one feature that can be incorporated with the present invention.
[00060] The novel device geometry of this embodiments of the invention provides for enhanced strain effects as follows. The contact area between the silicon body and a stressor is increased by allowing the stressor to contact the silicon body on the sidewalls of the silicon body. As a result of the increased influence of the stressor on the active region, strain in a strained channel transistor is enhanced. This technique is illustrated more clearly in a three-dimensional perspective of the multiple-gate transistor in FIG. 5. The stressor 166 not only contacts the top surface of the silicon fin 155, but also the sidewall surfaces of the silicon fin 155. The additional contact area between the stressor 166 and the silicon fin 155 on the two sidewalls of the silicon fin results in enhanced stress effects in the silicon fin 155. As a result, a strained-channel multiple-gate transistor may be formed with significantly enhanced performance. The arrows in FIG. 5 indicate the stress experienced by the channel region of the multiple-gate transistor.
[00061] The stressor 166 may be a high-stress material such as silicon nitride (e.g., Si3N4) deposited by plasma-enhanced chemical vapor deposition (PECVD). The stress in the PECVD silicon nitride can be in the range of −500 mega-pascals (MPa) to 1500 MPa, where negative stress indicates compressive stress and positive stress indicates tensile stress. As the channel width W decreases, the sidewall contact area as a proportion of the total contact area between the silicon fin 155 and the stressor 166 increases. Therefore, the enhancement in stress effects is expected to increase with a reduction in W.
[00062] This prediction of enhanced drive current is confirmed by our experimental results as shown in FIGS. 6 a and 6b. Strain-induced drive current enhancement is increased from 10% to 17% as the W is reduced from 1200 nm to 110 nm at an off-state leakage of 300 nA/micrometer. With further scaling of the gate length, the enhancement (dashed arrow) will become even larger, which is attributed to larger channel stress. Operation voltage is 1.0 V.
[00063] The silicon fin 155 of the multiple-gate transistor may have rounded corners 186, as shown in the three-dimensional perspective of FIG. 7. In FIG. 7 , the stressor 166 is not shown for the sake of simplicity. The novel corner rounding at the isolation edge of the active region 155 of the multiple-gate transistor is another feature of the present invention to avoid double-hump IGS˜VGS characteristics. Rounded corners, as compared with sharp corners, avoid excessive stress concentration in a small region that may result in defect generation and propagation. Such defects may result in degraded device performance and reduced yield.
[00064] FIG. 8 a shows the top view of the active region 155 or silicon fin 155 after the patterning of an active region surrounded by isolation regions 158. The cross-sectional view of this device is illustrated in FIG. 8 b, in which the isolation region 158 is depicted as a shallow trench isolation with an intentional recess 162 of amount R, where R may be greater than about 300 angstroms.
[00065] In another embodiment, as shown in FIG. 8 c, a mesa isolation structure is used for isolation purposes. Mesa isolation is an isolation technique where silicon islands 155 are formed on an insulator 152 and electrically isolated from each other. The cross-sections in FIG. 8 b and FIG. 8 c emphasize the rounded corners 186 in the edge portions of the active region adjacent to the isolation regions.
[00066] The radius of curvature of the round corner 186 is denoted by r. The value of r may vary from about 10 angstroms to about 200 angstroms in preferred embodiments. Comer rounding of the active silicon region 155 may be achieved by processes such as etching, oxidation, and/or annealing, performed after the active region definition. It is understood that the round corner in the sectional view are in fact two round top edges of the active region in a three dimensional view.
[00067] FIGS. 8 b and 8c schematically illustrate an intentional isolation recess 162 according to one example of the present invention. The recess R in both a shallow trench isolation or a mesa isolation is designed to be sufficiently large to allow the gate to deplete the narrow body from the isolation edges. In addition, the intentional recess will also give extra extended channel width. The value of R is preferably greater than about 300 angstroms. In general, R may be comparable to the thickness of the silicon film 155.
[00068] In addition, according to simulation and experimental results, the transistor performance enhancement due to the strain effects increases with reduced transistor dimensions such as gate length 184, spacer width 182, and silicon film 155 thickness. As shown experimentally in FIG. 6 , reduction of the gate length 184 results in a larger strain-induced drive-current enhancement (dashed arrow). This is attributed to larger strain in the channel.
[00069] In FIG. 9 , the stress in the channel region of the silicon-on-insulator transistor is plotted as a function of the silicon film thickness for different gate lengths. The stress in the channel region increases as the silicon film 155 thickness is reduced and as the gate length 184 is reduced. In the preferred embodiment, the silicon film 155 thickness ranges from about 20 angstroms to about 400 angstroms. FIG. 10 shows that the stress in the channel increases as the spacer width 182 is reduced and as the gate length 184 is reduced. According to embodiments of this invention, a spacer width of less than about 500 angstroms can be especially beneficial for significantly enhanced stress effects. In the preferred embodiment, the spacer width ranges from about 10 angstroms to about 500 angstroms.
[00070] According to the next embodiment of this invention, a method of providing the abovementioned semiconductor-on-insulator chip with strained-channel partially-depleted SOI transistors, fully-depleted SOI transistors, and multiple-gate transistors will be described. The starting material is a semiconductor-on-insulator wafer 200 as shown in FIG. 11. The semiconductor-on-insulator wafer 200, includes a semiconductor layer 202 overlying an insulator layer 152 which in turn overlies a substrate 204. It is understood that the semiconductor layer 202 may be formed from an elemental semiconductor such as silicon or germanium, an alloy semiconductor such as silicon-germanium, or a compound semiconductor such as gallium arsenide or indium phosphide. The insulator layer 152 may be any insulating material such as silicon oxide, aluminum oxide, or silicon nitride or stacked combinations of these materials. The underlying substrate may be any semiconductor substrate such as silicon substrate or gallium arsenide substrate or non-semiconductor substrate such as quartz or sapphire. Other examples for each of these materials are envisioned.
[00071] The method embodiment is more clearly illustrated in FIGS. 12 a-12j using a series of cross-sections depicting the transistor fabrication process. The cross-section of the device is taken in the plane containing the line A-A′ and parallel to the active region or silicon fin 155 as shown in FIG. 5. The cross-section therefore cuts through the active region or silicon fin 155, i.e., the source region 172, channel region (unlabeled), drain region 174, gate dielectric 164, and the gate electrode 180 of the completed transistor. In this view the portion of the gate 160 that overlies the sidewalls 176 of active region 155 is not shown because it is in a plane above (and below) the plane of the page.
[00072] In the preferred embodiment, a silicon-on-insulator wafer 200 is used as the starting material, as shown in FIG. 12 a, where the semiconductor layer 202 is a silicon layer, the insulator layer 152 is a silicon oxide layer, and the substrate 204 is a silicon substrate. More preferably, the silicon layer 202 in the preferred embodiment has a thickness in the range of about 10 angstroms to about 2000 angstroms and the silicon oxide layer may have a thickness in the range of about 100 to about 2000 angstroms.
[00073] An active region or silicon fin 155 is formed by patterning the silicon layer 202, as shown in FIG. 12 b. The patterning of the active region or silicon fin 155 may be accomplished, for example, by depositing a mask material (not shown) on the silicon layer 202, patterning the mask material by optical lithography to form a patterned mask, etching the silicon layer 202, and removing the patterned mask. The mask material can be a photoresist, silicon nitride, or a stack comprising of a silicon nitride layer overlying a silicon oxide layer.
[00074] A gate dielectric layer 164 is formed, as shown in FIG. 12 c. The gate dielectric layer 164 can have a thickness between about 3 to about 100 angstroms, as an example. The gate dielectric layer 164 on top 178 of the active region 155 can have a different thickness than the gate dielectric layer 164 on the two sidewalls 176. For example, the thickness of the gate dielectric layer 164 on the top 178 can be thinner than that on the sidewall 176. In some examples, the thickness of the gate dielectric layer 164 on top 178 of the active region 155 is less than about 20 angstroms.
[00075] The gate dielectric 164 may comprise of any gate dielectric material such as silicon oxide, silicon oxynitride, or nitrided silicon oxide. The insulating material 164 may also be a high permittivity material with permittivity larger than 5, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4) or lanthanum oxide (La2O3). In the preferred embodiment, the gate dielectric is silicon oxide, which may be formed by thermal oxidation in an oxygen ambient at temperatures ranging from about 500 to about 1000 degrees Celsius. The gate dielectric layer 164 can also be formed by chemical vapor deposition or reactive sputtering. The gate dielectric layer 164 covers the top 178 and the sidewalls 176 of the silicon fin 155.
[00076] With the gate dielectric layer 164 appropriately formed, the gate electrode 160 material can then be formed on top of the gate dielectric layer 164. The gate electrode 160 material can be comprised of conventional poly-crystalline silicon, poly-crystalline silicon germanium, metals, metallic silicides, metallic nitrides or other conductors. The gate electrode 160 material may be deposited by conventional techniques such as chemical vapor deposition. The gate electrode 160 may also be formed by the deposition of silicon and metal, followed by an anneal to form a metal silicide gate electrode material. An example, the suicide could be titanium silicide, nickel silicide or cobalt silicide.
[00077] The gate electrode 160 material is then patterned using photolithography techniques, and etched using plasma etch processes to form the gate electrodes. FIG. 12 d shows the device cross-section after gate electrode 160 formation. The gate dielectric 164 is retained at least in the portion of the device covered by the gate electrode 160.
[00078] Source and drain extensions 186 and 188 are then implanted using ion implantation techniques as shown in FIG. 12 e. Super-halo implant may also be performed at this stage. By implanting the super-halo implant at a large angle ranging from about 15 to about 45 degrees with respect to the normal of the wafer, devices with short channel lengths will receive a high effective channel doping concentration, while devices with long channel lengths will receive a low effective channel doping concentration.
[00079] The super halo implant creates super halo regions 190. A spacer 180 is formed using techniques known and used in the art, e.g., deposition of the spacer material and anisotropic plasma etching as shown in FIG. 12 f. The spacer material may comprise of a dielectric material such as silicon nitride or silicon dioxide. In the preferred embodiment, the spacer 180 is made from silicon nitride.
[00080] Following spacer formation, the source and drain regions 172 and 174 are implanted as shown in FIG. 12 g. The source and drain regions 172 and 174 can be strapped with one or more conductive materials such as metals and silicides 192 as shown in FIG. 12 h. The conductive materials 152 can reach the source and drain regions 172 and 174 through contacts on the sidewalls and/or the top of the active region 155.
[00081] Next, a high-stress film or a stressor 166 is deposited over the completed transistor structure as shown in FIG. 12 i. According to preferred embodiment of this invention, the high stress film 166 not only contacts the top surface 178 of the active region 155 but also the sidewall surfaces 176 of the active region 155, as shown in FIG. 5. As an example, the high-stress film 166 can be PECVD silicon nitride. PECVD silicon nitride can be used to introduce tensile or compressive stress in the channel region.
[00082] The residual film stress impacts the strain components in the channel. The residual film stress can be tailored from a high state of tension, for stoichiometric silicon nitride, to one of compression, for silicon-rich films. The tensile or compressive nature of the strain in the channel region can therefore be adjusted by varying process conditions such as temperature, pressure, and the ratio of the flow rate of a precursor gas, e.g., dichlorosilane, to the total gas flow rate.
[00083] Following the formation of the high-stress film 166, a passivation layer 194 is deposited with a thickness of a few thousand angstroms, e.g., about 1000 to about 5000 angstroms. The passivation layer 194 is preferably comprised of silicon oxide (e.g., formed by decomposition of TEOS or doped silicon oxide e.g., PSG or BPSG). Contact holes are etched through the passivation layer 194 and the high-stress film 166 and are filled with conductive materials 196 to electrically contact the source region 172, drain region 174, and gate electrode 160 of the transistor, as shown in FIG. 12 j. Metalization 198 can then be used to electrically couple these regions with other regions in the chip.
[00084] In summary, one aspect of the present invention provides an improvement over PD-SOI or FD-SOI technologies. The present invention can selectively combine the advantages of PD-SOI and FD-SOI. For example, when converting circuit design from bulk to SOI, this invention can achieve minimal floating body effects at critical circuits like analog circuits using FD-SOI devices, and can also have the freedom to adopt multiple threshold voltage Vth devices in the PD-SOI region. Another noticeable improvement of the preferred embodiment of the present invention is its introduction of FinFET-like devices, which benefit scalability and control of short-channel effects. The semiconductor technology disclosed herein may be referred to as FinFET/FD/PD-SOI (“FiP-SOI”). In yet another aspect of the invention is the provision of enhanced strain effects for improving transistor performance in the abovementioned transistors.
[00085] As discussed above, the silicon fin 155 can be stressed by stressor layer 166. The active area 155 can also be strained by way of the underlying layer. For example; the silicon active area film can comprise a silicon layer formed over a silicon-geranium (SiGe) layer. The SiGe layer will cause a strain in the silicon layer.
[00086] In another embodiment, the silicon film for active area 155 can be formed using techniques taught in co-pending application Ser. No. 10/379,873 (TSMC2002-1384), filed Mar. 5, 2003, and incorporated herein by reference. In this embodiment, the silicon layer 202 is formed on a donor substrate and attached above buried insulator 152 using wafer separation and bonding techniques. The various embodiments taught in the co-pending application can be utilized here.
[00087] In the foregoing specification, the invention has been described with reference to specific embodiments. However, various modifications and changes can be made by one skilled in the art without departing from the scope of the present invention. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is understood that several modifications, changes and substitutions are intended in the foregoing disclosure and in some instances some features of the invention will be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
1. A silicon-on-insulator (SOI) chip comprising:
a silicon layer of a predetermined thickness overlying an insulator layer;
a multiple-gate SOI MOSFET including a strained channel region formed on a first portion of the silicon layer; and
a planar SOI MOSFET including a strained channel region formed on a second portion of the silicon layer.
2. The SOI chip of claim 1 wherein the silicon layer has a thickness in the range of about 10 angstroms to about 2000 angstroms.
3. The SOI chip of claim 1 wherein the silicon layer has a thickness of less than about 200 angstroms.
4. The SOI chip of claim 1 wherein the planar SOI MOSFET is a planar fully-depleted SOI (FD-SOI) MOSFET.
5. The SOI chip of claim 4 wherein the planar FD-SOI MOSFET comprises of a body region with a doping concentration ranging from about 1016 to about 1018 cm−3.
6. The SOI chip of claim 5 wherein the planar FD-SOI MOSFET has a gate length and a width, the gate length being larger than the width.
7. The SOI chip of claim 1 wherein the planar SOI MOSFET is a planar partially-depleted SOI (PD-SOI) MOSFET.
8. The SOI chip of claim 7 wherein the planar PD-SOI MOSFET comprises of a body region with a doping concentration ranging from about 1×1018 to about 2×1019 cm−3.
9. The SOI chip of claim 7 wherein the planar PD-SOI MOSFET has a gate length and a width, the gate length being smaller than the width.
10. The SOI chip of claim 1 wherein the multiple-gate SOI MOSFET is processed by reducing a device width to less than twice of a maximum width of a depletion layer.
11. The SOI chip of claim 1 wherein the multiple-gate MOSFET and the planar SOI MOSFET are isolated by using a shallow trench isolation.
12. The SOI chip of claim 11 wherein the shallow trench isolation includes an isolation recess of more than about 300 angstroms.
13. The SOI chip of claim 1 wherein the multiple-gate MOSFET and the planar SOI MOSFET are isolated by using mesa isolation.
14. The SOI chip of claim 1 wherein an active region of the multiple-gate MOSFET has rounded corners.
15. The SOI chip of claim 14 wherein the rounded corner has a radius of between about 10 angstroms and about 200 angstroms.
16. The SOI chip of claim 1 wherein the multiple-gate 501 MOSFET comprises:
a silicon fin overlying a portion of the insulator layer;
a strained channel region formed in a portion of the silicon fin;
a gate dielectric layer overlying the strained channel region;
a gate electrode formed on the gate dielectric layer; and
a source region and a drain regions formed on portions of the semiconductor fin adjacent to the strained channel region such that the source region is separated from the drain region by the strained channel region.
17. The SOI chip of claim 16 and further comprising a high stress film overlying the gate electrode, the source region, and the drain region.
18. The SOI chip of claim 17 wherein the high stress film comprises silicon nitride.
19. The SOI chip of claim 17 wherein the silicon fin has a top surface and two sidewall surfaces, and wherein the high stress film contacts the sidewall surfaces of the semiconductor fin.
20. The SOI chip of claim 16 wherein the silicon fin has a height in the range of about 20 angstroms to about 1000 angstroms.
21. The SOI chip of claim 16 wherein the silicon fin has a height of less than about 200 angstroms.
22. The SOI chip of claim 16 wherein the silicon fin has a width in the range of about 20 angstroms to about 1000 angstroms.
23. The SOI chip of claim 16 wherein the silicon fin has rounded corners.
24. The SOI chip of claim 16 wherein the insulator layer comprises a dielectric.
25. The SOI of claim 24 wherein the insulator layer comprises silicon oxide.
26. The SOI chip of claim 16 wherein the strained channel region has a strain with a magnitude of between about 0.1% and about 2%.
27. The SOI chip of claim 16 where the gate dielectric layer comprises silicon oxynitride.
28. The SOI of claim 16 wherein the gate dielectric layer comprises a high permittivity material.
29. The SOI chip of claim 28 wherein the relative permittivity of the high permittivity material is greater than 5.
30. The SOI chip of claim 16 wherein the gate dielectric layer comprises aluminum oxide, hafnium oxide, halfnium silicon oxynitride, hafnium silicate, zirconium oxide, zirconium silicate, or lanthanum oxide, or combinations thereof.
31. The SOI chip of claim 16 wherein the gate dielectric layer has a thickness of between about 3 and about 100 angstroms.
32. The SOI chip of claim 16 wherein a thickness of the gate dielectric layer on a top surface of the silicon fin is different than a thickness of the gate dielectric layer on a sidewall surface of the silicon fin.
33. The SOI chip of claim 32 wherein the thickness of the gate dielectric layer on the top of the active region is thinner than the thickness of the gate dielectric layer on the sidewall.
34. The SOT chip of claim 16 wherein a thickness of the gate dielectric layer on a top surface of the silicon fin is less than about 20 angstroms.
35. The SOI chip of claim 16 wherein the gate electrode comprises poly-crystalline silicon.
36. The SOI chip of claim 16 wherein the gate electrode comprises poly-crystalline silicon germanium.
37. The SOI chip of claim 16 wherein the gate electrode comprises a metal, a metal suicide, or a metallic nitride.
38. The SOI chip of claim 16, further comprising spacers on the sides of the gate electrode.
39. The SOI chip of claim 38 wherein the spacer has a width of less than about 500 angstroms.
40. The SOI chip of claim 16 wherein the gate electrode has a gale length of less than about 65 nm.
41. A silicon-on-insulator (SOI) chip including a multiple-gate SOI MOSFET, wherein the multiple-gate SOI MOSFET comprises:
an insulator layer;
a silicon fin overlying a portion of the insulator layer;
a strained channel region formed in a portion of the silicon fin;
a gate dielectric layer overlying the strained channel region;
a gate electrode formed on the gate dielectric layer;
a source region and a drain region formed on portions of the semiconductor fin adjacent to the strained channel region, the source region being separated from the drain region by the strained channel region; and
an insulating film overlying at least a portion of the gate electrode and at least a portion of the semiconductor fin adjacent the strained channel region.
42. The SOI chip of claim 41 and wherein the insulating film comprises a high stress film overlying at least a portion of the gate electrode, at least a portion of the source region, and at least a portion of the drain region.
43. The SOI chip of claim 42 wherein the high stress film comprises silicon nitride.
44. The SOI of claim 42 wherein the silicon fin has a top and two sidewall surfaces, and the high stress film contacts the sidewall surfaces of the semiconductor fin.
45. The SOI chip of claim 41 wherein the silicon fin has a height in the range of about 20 angstroms to about 1000 angstroms.
46. The SOI chip of claim 41 wherein the silicon fin has a height of less than about 200 angstroms.
47. The SOI chip of claim 41 wherein the silicon fin has a width in the range of about 20 angstroms to about 1000 angstroms.
48. The SOI chip of claim 41 wherein the silicon fin has rounded corners.
49. The SOI chip of claim 41 wherein the insulator layer is comprised of a dielectric.
50. The SOI of claim 49 wherein the insulator layer is comprised of silicon oxide.
51. The SOI chip of claim 41 wherein the strained channel region has a strain with a magnitude of between about 0.1% and about 2%.
52. The SOI chip of claim 41 wherein the strained channel region has a strain with a magnitude of between about 1% and about 2%.
53. The SOI of claim 41 where the gate dielectric layer comprises silicon oxynitride.
54. The SOI chip of claim 41 wherein the gate dielectric layer comprises a high permittivity material.
55. The SOI chip of claim 54 wherein the high permittivity material has a relative permittivity that is greater than about 5.
56. The SOI chip of claim 41 wherein the gate dielectric layer comprises aluminum oxide, hafnium oxide, hafnium silicon oxynitride, hafnium silicate, zirconium oxide, zirconium silicate, or lanthanum oxide, or combinations thereof.
57. The SOI of claim 41 wherein the gate dielectric layer has a thickness of between about 3 and about 100 angstroms.
58. The SOI chip of claim 41 wherein the thickness of the gate dielectric layer on the top surface of the silicon fin is different from the thickness of the gate dielectric layer on the sidewall surfaces of the silicon fin.
59. The SOI of claim 41 wherein the thickness of the gate dielectric layer on the top of the active region is thinner than the thickness thereof on the sidewall.
60. The SOI chip of claim 41 wherein the thickness of the gate dielectric layer on the top surface of the silicon fin is less than about 20 angstroms.
61. The SOI of claim 41 wherein the gate electrode comprises poly-crystalline silicon.
62. The SOI of claim 41 wherein the gate electrode comprises poly-crystalline silicon germanium.
63. The SOI chip of claim 41 wherein the gate electrode comprises of a metal, a metal silicide, or a metallic nitride.
64. The SOI chip of claim 41, further comprising spacers on the sides of the gate electrode.
65. The SOI of claim 64 wherein the spacer has a width of less than about 500 angstroms.
66. The SOI chip of claim 41 wherein the gate electrode has a gate length of less than about 65 nm.
67. The SOI chip of claim 41 and further comprising a planar SOI MOSFET including a strained channel formed on a silicon layer over the insulator layer.
68. The SOI chip of claim 67 wherein the planar SOI MOSFET is a planar fully-depleted SOI (FD-SOI) MOSFET.
69. The SOI chip of claim 67 wherein the planar SOI MOSFET is a planar partially-depleted SOI (PD-SOI) MOSFET.
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