US 7,679,347 B2Grant
Closed-loop digital control system for a DC/DC converter
Issue Date:2010-03-16
•21 Claims
•8 Drawing Sheets
Abstract
A control system comprises a DC/DC converter that includes first and second inductances, that receives a first DC voltage and that generates a second DC voltage. A control module selectively charges or discharges the first inductance while discharging or charging the second inductance during a first mode and one of charges both of the first and second inductances or discharges both of the first and second inductances during a second mode.
Metadata
Assignee
- Marvell World Trade Ltd.
Inventors
- Runsheng He
- Zhipei Chi
Application Information
Application Number:US 11/710,384
Filing Date:2007-02-23
Priority Date:2004-07-13
Art Unit:2838
Classifications
IPC:
G05F1/40
Patent Drawings (8 sheets)
Description
Cross-Reference to Related Applications
[0001] This application is a continuation of U.S. patent application Ser. No. 10/890,491 filed on Jul. 13, 2004 and relates to U.S. patent application Ser. No. 10/621,058, filed on Jul. 15, 2003, entitled “Low Loss DC/DC Converter”, U.S. patent application Ser. No. 10/754,187, filed on Jan. 8, 2004, entitled “Digital Low Dropout Regulator”, which is a continuation-in-part of U.S. patent application Ser. No. 10/693,787, filed on Oct. 24, 2003, and U.S. patent application Ser. No. 10/810,452, filed on Mar. 26, 2004, entitled “Voltage Regulator”. The disclosures of the above applications are all hereby incorporated by reference in their entireties.
Field of the Invention
[0002] The present invention relates to DC/DC converters, and more particularly to digital control systems for DC/DC converters.
Background of the Invention
[0003] DC/DC converters are electronic devices that employ inversion and/or rectification to transform DC voltage at a first level into DC voltage at a second level. For example, a DC/DC converter may step-up DC voltage, step-down DC voltage, or may be capable of both stepping up and stepping down DC voltage. DC/DC converters typically include one or more inductors. Inductors are circuit elements that operate based on magnetic fields. The source of the magnetic field is charge that is in motion, or current. If current varies with time, the magnetic field that is induced also varies with time. A time-varying magnetic field induces a voltage in conductors that are linked by the magnetic field.
[0004] Referring to FIG. 1A , a DC/DC converter 10 includes an inductor 12. Inductors 12 in DC/DC converters 10 typically communicate with at least one switch and at least one capacitor. For example, the switch may be a transistor and the capacitor may be an output capacitor that filters an output voltage of the DC/DC converter 10. A control module may communicate with the switch to control when the inductor 12 charges or discharges. For example, when the switch is on, the input current may flow through the switch and inductor 12 to the capacitor while building up the magnetic field of the inductor 12. When the switch is off, the inductor 12 opposes the drop in current and supplies current to the capacitor.
[0005] Referring now to FIGS. 1B and 1C , one or more conductors form coupled inductor circuits 14 and 16, respectively. In FIG. 1B , first and second conductors pass through the same magnetic core and exhibit mutual coupling with a coupling coefficient that is approximately equal to 1. In FIG. 1C , a single conductor passes through the magnetic core two or more times and exhibits mutual coupling with a coupling coefficient that is approximately equal to 1. Those skilled in the art can appreciate that still other inductor circuits may be employed. In FIGS. 1B and 1C , the coupled inductor circuits 14 and 16 are implemented in DC/DC converters 18 and 20, respectively. DC/DC converters 18 and 20 that employ coupled inductor circuits 14 and 16 have a fast response with small voltage ripple and high efficiency.
[0006] Control modules in DC/DC converters generate control signals to turn the switches on an off and to adjust a rate at which the inductors charge and discharge. The control signals typically have fixed frequencies and duty cycles to obtain predetermined output voltages. However, when the control module maintains control signals at a fixed frequency and duty cycle, the control module is unable to adapt to changing circuit conditions.
Summary of the Invention
[0007] A closed-loop control system for a DC/DC converter according to the present invention includes a DC/DC converter that receives a first DC voltage and that generates a second DC voltage. The DC/DC converter includes first and second inductances. A control module communicates with the DC/DC converter, receives the second DC voltage, and generates at least one control signal to one of charge or discharge the first and second inductances. The control module has first and second modes. During the first mode the control module alternately charges one of the first and second inductances and discharges the other of the first and second inductances. During the second mode the control module one of charges or discharges both of the first and second inductances.
[0008] In other features, the control module initiates the second mode when a transient condition occurs in the DC/DC converter. The control module detects the transient condition when the second DC voltage is one of greater than a first predetermined voltage or less than a second predetermined voltage. During the second mode the control module initiates the first mode when the second DC voltage is both less than the first predetermined voltage and greater than the second predetermined voltage. The control module discharges both of the first and second inductances when the second voltage is greater than the first predetermined voltage. The control module charges both of the first and second inductances when the second DC voltage is less than the second predetermined voltage.
[0009] In still other features of the invention, the DC/DC converter includes an output capacitance. The control module detects the transient condition when current through the output capacitance is one of greater than a first predetermined current or less than a second predetermined current. During the second mode the control module initiates the first mode when the current is less than the first predetermined current and greater than the second predetermined current. The control module charges both of the first and second inductances when the current is less than the second predetermined current. The control module discharges both of the first and second inductances when the current is greater than the first predetermined current. The control module determines the current based on a rate of change of the second DC voltage. The current is one of greater than the first predetermined current or less than the second predetermined current when the rate of change is greater than a predetermined rate of change. The control module determines the current based on an average value of the second DC voltage during a predetermined time period.
[0010] In yet other features, during the second mode the control module initiates the first mode after a predetermined time period. The DC/DC converter includes an output capacitance. The output capacitance discharges when the control module discharges both of the first and second inductances. The DC/DC converter includes an output capacitance. The output capacitance charges when the control module charges both of the first and second inductances.
[0011] In still other features of the invention, the DC/DC converter includes first, second, third, and fourth switches. Second terminals of the first and third switches communicate with first terminals of the second and fourth switches, respectively. First terminals of the first and third switches communicate. Second terminals of the second and fourth switches communicate. A first end of the first inductance communicates with the second terminal of the third switch and the first terminal of the fourth switch. A first end of the second inductance communicates with the second terminal of the first switch and the first terminal of the second switch. Second ends of the first and second inductances communicate. A capacitance has a first end that communicates with the second ends of the first and second inductances and a second end that communicates with the second terminals of the second and fourth switches.
[0012] In yet other features, the first, second, third, and fourth switches comprise transistors. The control module generates first, second, third, and fourth control signals that communicate with control terminals of the first, second, third, and fourth switches, respectively. The control module asserts the third and fourth control signals to charge the first inductance and the first and second control signals to charge the second inductance. The first DC voltage is input to the first terminals of the first and third switches. The second DC voltage is referenced from the first end of the capacitance. The DC/DC converter includes a current source. A first end of the current source communicates with the second end of the first and second inductances and the first end of the capacitance and a second end of the current source communicates with the second terminals of the second and fourth switches and the second end of the capacitance.
[0013] Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Brief Description of the Drawings
[0014] The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
[0015] FIG. 1A is a functional block diagram and electrical schematic of an inductor implemented in an exemplary DC/DC converter according to the prior art;
[0016] FIG. 1B is a functional block diagram and electrical schematic of a coupled inductor circuit with two conductors implemented in an exemplary DC/DC converter according to the prior art;
[0017] FIG. 1C is a functional block diagram and electrical schematic of a coupled inductor circuit with one conductor implemented in an exemplary DC/DC converter according to the prior art;
[0018] FIG. 2 is a functional block diagram and electrical schematic of a coupled-inductor DC/DC converter with a control module that implements an open-loop control system according to the present invention;
[0019] FIG. 3 is a timing diagram that illustrates the control signal waveforms generated by the control module of FIG. 2 including alternating charging and discharging of the first and second inductors;
[0020] FIG. 4 is a functional block diagram of a closed-loop control system for a DC/DC converter;
[0021] FIG. 5 is a graph showing the output voltage of the DC/DC converter in FIG. 4 as a function of time;
[0022] FIG. 6 is a timing diagram that illustrates the control signal waveforms generated by the control module of FIG. 4 including an overlap of the charging pattern for the first and second inductors;
[0023] FIG. 7 is an electrical schematic of the closed-loop DC/DC control system of FIG. 4 ;
[0024] FIG. 8 is a flowchart illustrating steps performed by the control module of FIGS. 4 and 7 including initiating same-phase operation of the first and second inductors for a predetermined time period; and
[0025] FIG. 9 is a flowchart illustrating steps performed by the control module of FIGS. 4 and 7 including initiating same-phase operation of the first and second inductors while a variable is outside of a predetermined range.
Detailed Description of the Preferred Embodiments
[0026] The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
[0027] Referring now to FIG. 2 , an open-loop control system 28 for a DC/DC converter 30 includes a control module 32. The DC/DC converter 30 includes first, second, third, and fourth transistors 34, 36, 38, and 40, respectively. Sources (or second terminals) of the first and third transistors 34 and 38, respectively, communicate with drains (or first terminals) of the second and fourth transistors 36 and 40, respectively. Drains of the first and third transistors 34 and 38, respectively, communicate and sources of the second and fourth transistors 36 and 40, respectively, communicate.
[0028] First and second inductors 42 and 44, respectively, form a coupled inductor circuit 46. A first end of the first inductor 46 communicates with the source of the third transistor 38 and the drain of the fourth transistor 40. A first end of the second inductor 44 communicates with the source of the first transistor 34 and the drain of the second transistor 36. Second ends of the first and second inductors 42 and 44, respectively, communicate. A first end of a capacitor 48 communicates with the second ends of the first and second inductors 42 and 44, respectively.
[0029] A second end of the capacitor 48 communicates with the sources of the second and fourth transistors 36 and 40, respectively. A first end of a current source 50 communicates with the first end of the capacitor 48 and the second ends of the first and second inductors 42 and 44, respectively. A second end of the current source 50 communicates with the sources of the second and fourth transistors 36 and 40, respectively, and the second end of the capacitor 48. A input DC voltage 52 (Vin) of the DC/DC converter 30 communicates with the drains of the first and third transistors 34 and 38, respectively. An output DC voltage 54 (Vout) of the DC/DC converter 30 in referenced from the second ends of the first and second inductors 42 and 44, respectively, the first end of the capacitor 48, and the first end of the current source 50.
[0030] The control module 32 generates first, second, third, and fourth control signals U2, D2, U1, and D1 that communicate with gates (or control terminals) of the first, second, third, and fourth transistors 34, 36, 38, and 40, respectively. The control module 32 charges the first inductor 42 by setting the third and fourth control signals U1 and D1, respectively, high (or low) and discharges the first inductor 42 by setting the third and fourth control signals U1 and D1, respectively, low (or high).
[0031] The control module 32 charges the second inductor 44 by setting the first and second control signals U2 and D2, respectively, high (or low) and discharges the second inductor 44 by setting the first and second control signals U2 and D2, respectively, low (or high). Based on a frequency and duty cycle of the control signals, the DC/DC converter 30 transforms the input DC voltage 52 into the output DC voltage 54, which is at a different level than the input DC voltage 52.
[0032] Referring now to FIG. 3 , signal waveforms of the third and fourth control signals U1 and D1, respectively, indicated by 62, and of the first and second control signals U2 and D2, respectively, indicated by 64, are shown as square waveforms. The control module 32 maintains the signal waveforms for the first, second, third, and fourth control signals U2, D2, U1, and D1, respectively, at a predetermined frequency and duty cycle so that the DC/DC converter 30 generates a desired voltage. Signal waveforms 62 of the third and fourth control signals U1 and D1, respectively, are complementary (or 180 degrees out-of-phase) to the signal waveforms 64 of the first and second control signals U2 and D2, respectively. Therefore, when the first inductor 42 charges, the second inductor 44 discharges. Likewise, when the first inductor 42 discharges, the second inductor 44 charges.
[0033] An advantage of the open-loop control system 28 of FIG. 2 is that the DC/DC converter 30 has a high efficiency and generates a small voltage ripple. The DC/DC converter 30 also has a relatively fast response, which allows the capacitor 48 to be smaller in size. Additionally, the control module 32 maintains the signal waveforms of the first, second, third, and fourth control signals U2, D2, U1, and D1, respectively, at a fixed frequency and duty cycle. Therefore, no additional control is required for the open-loop control system 28 during normal operations.
[0034] However, there are advantages to allowing the phases of the signal waveforms for the third and fourth control signals U1, and D1, respectively, and the first and second control signals U2 and D2, respectively, to overlap for a controlled period of time. For example, allowing same-phase operation of the control signals for a controlled period of time reduces the size of the effective inductor and produces a much faster response in the DC/DC converter 30. This allows the capacitor 48 to be even smaller in size. However, if same-phase operation of the control signals continues for too long, too much current may be charged in the first and second inductors 42 and 44, respectively, which adversely affects performance of the DC/DC converter 30. Therefore, it is necessary to determine under which conditions same-phase operation of the control signals is initiated and for how long.
[0035] Referring now to FIG. 4 , a closed-loop control system 72 for the DC/DC converter 30 according to the present invention is shown. An input of the control module 32 receives the output DC voltage 54 of the DC/DC converter 30. The control module 32 also optionally receives voltage signals Vx1 and Vx2 from the first and second inductors 42 and 44, respectively. For example, the control module 32 may perform a current estimation based on voltage signals Vx1 and Vx2 to sense a balance of the first and second inductors 42 and 44, respectively.
[0036] The control module 32 ensures that the phases of the signal waveforms for the third and fourth control signals U1 and D1, respectively, are complementary to the phases of the signal waveforms for the first and second control signals U2 and D2, respectively, during normal operations. The control module 32 initiates same-phase operation of the control signals when a large voltage or current transient is detected in the DC/DC converter 30 based on the output DC voltage 54.
[0037] In an exemplary embodiment, the control module 32 initiates same-phase operation of the control signals when a value of the output DC voltage 54 is outside of a predetermined range. For example, the control module 32 sets the signal waveforms of the control signals low (or high) when the value of the output DC voltage 54 is greater than a first predetermined voltage. This allows both the first and second inductors 42 and 44, respectively, to discharge. The control module 32 sets the signal waveforms of the control signals high (or low) when the value of the output DC voltage 54 is less than a second predetermined voltage. This allows both the first and second inductors 42 and 44, respectively, to charge.
[0038] The control module 32 may revert back to complementary operation of the control signals when the value of the output DC voltage 54 is back within the predetermined range. Alternatively, the control module 32 may revert back to complementary operation of the control signals after a predetermined time period. In an exemplary embodiment, the predetermined time period is a function of one or more circuit conditions such as a current or voltage magnitude within the DC/DC converter 30.
[0039] In the event that the output DC voltage 54 is within the predetermined range, the current, Ic, flowing through the capacitor 48 may still be too high or too low. Therefore, in another exemplary embodiment, the control module 32 initiates same-phase operation of the control signals when a value of the current flowing through the capacitor 48 is outside of a predetermined range. For example, the control module 32 sets the signal waveforms of the control signals low (or high) when the current flowing through the capacitor 48 is greater than a first predetermined current. This allows both the first and second inductors 42 and 44, respectively, to discharge.
[0040] The control module 32 sets the signal waveforms of the control signals high (or low) when the current flowing through the capacitor 48 is less than a second predetermined current. This allows both the first and second inductors 42 and 44, respectively, to charge. As in the case of the voltage threshold, the control module 32 may revert back to complementary operation of the control signals when the current flowing through the capacitor 48 is back within the predetermined range. Alternatively, the control module 32 may revert back to complementary operation of the control signals after a predetermined time period.
[0041] Referring now to FIG. 5 , the control module 32 estimates the current, Ic, flowing through the capacitor 48 based on the output DC voltage 54, Vout. The current flowing through the capacitor 48 is proportional to the rate of change of the output DC voltage 54. Therefore, the control module 32 computes the amount of time, Tcross, that it takes for the output DC voltage 54, indicated by 80, to increase or decrease from a first predetermined voltage (VL2 or VL1 ) to a second predetermined voltage (VL1 or VL2 ). In the exemplary embodiment illustrated in FIG. 5 , the output DC voltage 54 decreases from a first predetermined voltage (VL1 ), indicated by 82, to a second predetermined voltage (VL2 ), indicated by 84.
[0042] As the value of Tcross decreases, the slope of Vout increases, which corresponds to an increase in the current flowing through the capacitor 48. Likewise, as the value of Tcross increases, the slope of Vout decreases, which corresponds to a decrease in the current flowing through the capacitor 48. Therefore, by comparing Tcross to a predetermined time period, the control module 32 determines when the current flowing through the capacitor 48 is outside of the predetermined range. Alternatively, the control module 32 may estimate the current flowing through the capacitor 48 based on an average value of Vout during a predetermined time period.
[0043] Referring now to FIG. 6 , the phase of the signal waveforms for the third and fourth control signals U1 and D1, respectively, indicated at 92, overlaps the phase of the signal waveforms for the first and second control signals U2 and D2, respectively, indicated at 94, for a controlled period of time, Toverlap. The Toverlap period identifies when the control module 32 maintains same-phase operation of the control signals. Before and after the Toverlap period, the control module 32 maintains complementary operation of the control signals.
[0044] Referring now to FIG. 7 , the control module 32 and the DC/DC converter 30 are illustrated in further detail. Similar reference numbers are used to identify elements as in FIG. 2 . The control module 32 includes a voltage compare module 102 and a control signal generator 104. The control module 32 also optionally includes a current detection module 106. A first input of the voltage compare module 102 receives the output DC voltage 54 from the DC/DC converter 30. A second input of the voltage compare module 102 receives a predetermined voltage. The voltage compare module 102 compares the output DC voltage 54 and the predetermined voltage to determine when the output DC voltage 54 is greater than or less than the predetermined voltage.
[0045] The voltage compare module 102 outputs the result to the control signal generator 104. Inputs of the optional current detection module 106 receive the voltage signals Vx1 and Vx2 from the first and second inductors 42 and 44, respectively. The current detection module 106 computes the difference between Vx1 and Vx2 and transmits the difference to the control signal generator 104. The control signal generator 104 generates the first, second, third, and fourth control signals U2, D2, U1 and D1, respectively, based on values of the control signals from the voltage compare module 102 and/or the current detection module 106. The control signal generator 104 transmits the first, second, third, and fourth control signals U2, D2, U1 and D1, respectively, to the gates of the first, second, third, and fourth transistors 34, 36, 38, and 40, respectively, in the DC/DC converter 30.
[0046] Referring now to FIG. 8 , a first closed-loop control algorithm begins in step 114. In step 116, control reads the value of the output DC voltage 54 from the DC/DC converter 30. In step 118, control determines whether the output DC voltage 54 is greater than a first predetermined voltage plus a threshold. If true, control proceeds to step 120. If false, control proceeds to step 122. In step 120, control initiates same-phase operation of the control signals by setting the signal waveforms of the control signals low (or high). In step 124, control resets a timer. In step 126, control determines whether the timer has expired. If false, control loops to step 126. If true, control proceeds to step 128.
[0047] In step 128, the control module 32 reverts back to complementary operation of the control signals and control ends. In step 122, control determines whether the output DC voltage 54 is less than a second predetermined voltage minus a threshold. For example, the thresholds in steps 118 and 122 may be equal and/or the first and second predetermined voltages may be equal. If true, control proceeds to step 130. If false, control proceeds to step 132. In step 130, the control module 32 initiates same-phase operation of the control signals by setting the signal waveforms of the control signals high (or low) and control proceeds to step 124.
[0048] In step 132, the control module 32 estimates the current flowing through the capacitor 48 in the DC/DC converter 30. In step 134, control determines whether the current flowing through the capacitor 48 is greater than a first predetermined current. If true, control proceeds to step 120. If false, control proceeds to step 136. In step 136, control determines whether the current flowing through the capacitor 48 is less than a second predetermined current. For example, the second predetermined current may be equal in magnitude to the first predetermined current and have an opposite polarity. If true, control proceeds to step 130. If false, control ends.
[0049] Referring now to FIG. 9 , a second closed-loop control algorithm begins in step 144. In step 146, control reads the value of the output DC voltage 54 from the DC/DC converter 30. In step 148, control determines whether the output DC voltage 54 is greater than a first predetermined voltage plus a threshold. If true, control proceeds to step 150. If false, control proceeds to step 152. In step 150, the control module 32 initiates same-phase operation of the control signals by setting the signal waveforms of the control signals low (or high). In step 154, control determines whether the output DC voltage 54 is less than the first predetermined voltage plus the threshold. Is false, control loops to step 154. If true, control proceeds to step 156. In step 156, the control module 32 reverts back to complementary operation of the control signals and control ends.
[0050] In step 152, control determines whether the output DC voltage 54 is less than a second predetermined voltage minus a threshold. For example, the thresholds in steps 148 and 152 may be equal and/or the first and second predetermined voltages may be equal. If true, control proceeds to step 158. If false, control proceeds to step 160. In step 158, the control module 32 initiates same-phase operation of the control signals by setting the signal waveforms of the control signals high (or low). In step 162, control determines whether the output DC voltage 54 is greater than the second predetermined voltage minus the threshold. If false, control loops to step 162. If true, control proceeds to step 156. In step 160, the control module 32 estimates the current flowing through the capacitor 48 in the DC/DC converter 30.
[0051] In step 164, control determines whether the current flowing through the capacitor 48 is greater than a first predetermined current. If true, control proceeds to step 166. If false, control proceeds to step 168. In step 166, the control module 32 initiates same-phase operation of the control signals by setting the signal waveforms of the control signals low (or high). In step 170, control determines whether the current flowing through the capacitor 48 is less than the first predetermined current. If false, control loops to step 170. If true, control proceeds to step 156.
[0052] In step 168, control determines whether the current flowing through the capacitor 48 is less than a second predetermined current. For example, the second predetermined current may be equal in magnitude to the first predetermined current and have an opposite polarity. If false, control ends. If true, control proceeds to step 172. In step 172, the control module 32 initiates same-phase operation of the control signals by setting the signal waveforms of the control signals high (or low). In step 174, control determines whether the current flowing through the capacitor 48 is greater than the second predetermined current. If false, control loops to step 174. If true, control proceeds to step 156.
[0053] The present invention allows for closed-loop digital control of a coupled-inductor DC/DC converter 30. However, the methods of the present invention may also be employed to control other electronic circuits of a similar nature. By utilizing an output voltage feedback path, the control module 32 is capable of detecting large voltage or current transients in the circuitry of the DC/DC converter 30. Therefore, the previous constraint of constant complementary operation of the control signals is relaxed. This allows the DC/DC converter 30 to achieve an even faster response and requires an even smaller output capacitor 48 than DC/DC converters that employ open-loop control systems.
[0054] Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and the following claims.
Claims
What is claimed is:
1. A control system comprising:
a DC/DC converter that includes a first inductance and a second inductance, that receives a first DC voltage, and that generates a second DC voltage;
a control module that:
charges said first inductance while discharging said second inductance during a first mode; and
one of charges and discharges both of said first and second inductances during a second mode; and
an output capacitance,
wherein said control module selects said second mode based on a transient condition and current through said output capacitance, and detects said transient condition when said current through said output capacitance is one of greater than a first predetermined current and less than a second predetermined current.
2. The control system of claim 1 wherein said control module detects said transient condition when said second DC voltage is one of greater than a first predetermined voltage or less than a second predetermined voltage.
3. The control system of claim 2 wherein, during said second mode, said control module selects said first mode when said second DC voltage is both less than said first predetermined voltage and greater than said second predetermined voltage.
4. The control system of claim 2 wherein said control module discharges both of said first and second inductances when said second voltage is greater than said first predetermined voltage.
5. The control system of claim 2 wherein said control module charges both of said first and second inductances when said second DC voltage is less than said second predetermined voltage.
6. The control system of claim 1 wherein, during said second mode, said control module initiates said first mode when said current is less than said first predetermined current and greater than said second predetermined current.
7. The control system of claim 1 wherein said control module charges both of said first and second inductances when said current is less than said second predetermined current.
8. The control system of claim 1 wherein said control module discharges both of said first and second inductances when said current is greater than said first predetermined current.
9. The control system of claim 1 wherein said control module determines said current based on a rate of change of said second DC voltage.
10. The control system of claim 9 wherein said current is one of greater than said first predetermined current or less than said second predetermined current when said rate of change is greater than a predetermined rate of change.
11. The control system of claim 1 wherein said control module determines said current based on an average value of said second DC voltage during a predetermined period.
12. The control system of claim 1 wherein, during said second mode, said control module selects said first mode after a predetermined period.
13. The control system of claim 1 wherein said DC/DC converter includes an output capacitance and wherein said output capacitance discharges when said control module discharges both of said first and second inductances.
14. The control system of claim 1 wherein said DC/DC converter includes an output capacitance and wherein said output capacitance charges when said control module charges both of said first and second inductances.
15. The control system of claim 1 wherein said DC/DC converter includes:
first, second, third, and fourth switches,
wherein second terminals of said first and third switches communicate with first terminals of said second and fourth switches, respectively, first terminals of said first and third switches communicate, second terminals of said second and fourth switches communicate, a first end of said first inductance communicates with said second terminal of said third switch and said first terminal of said fourth switch, a first end of said second inductance communicates with said second terminal of said first switch and said first terminal of said second switch, and second ends of said first and second inductances communicate; and
said output capacitance having a first end that communicates with said second ends of said first and second inductances and a second end that communicates with said second terminals of said second and fourth switches.
16. The control system of claim 15 wherein said first, second, third, and fourth switches comprise transistors.
17. The control system of claim 15 wherein said control module generates first, second, third, and fourth control signals that communicate with control terminals of said first, second, third, and fourth switches, respectively.
18. The control system of claim 17 wherein said control module asserts said third and fourth control signals to charge said first inductance and said first and second control signals to charge said second inductance.
19. The control system of claim 15 wherein said first DC voltage is input to said first terminals of said first and third switches.
20. The control system of claim 15 wherein said second DC voltage is referenced from said first end of said output capacitance.
21. The control system of claim 15 wherein said DC/DC converter includes a current source and wherein a first end of said current source communicates with said second end of said first and second inductances and said first end of said output capacitance and a second end of said current source communicates with said second terminals of said second and fourth switches and said second end of said output capacitance.
Patent Citations (130)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3529233(A) | 1970-09-01 | Podell | Applicant |
| US3579214(A) | 1971-05-01 | Solyst | Applicant |
| US3851375(A) | 1974-12-01 | Koomeef | Applicant |
| US4020439(A) | 1977-04-01 | Thiessens et al. | Applicant |
| US4040174(A) | 1977-08-01 | Tsuda | Applicant |
| US4203081(A) | 1980-05-01 | Braeckelmann | Applicant |
| US4214198(A) | 1980-07-01 | Schneider | Applicant |
| US4273051(A) | 1981-06-01 | Stratton | Applicant |
| US4384321(A) | 1983-05-01 | Rippel et al. | Applicant |
| US4430609(A) | 1984-02-01 | Van Kessel et al. | Applicant |
| US4475143(A) | 1984-10-01 | Hernandez | Applicant |
| US4527032(A) | 1985-07-01 | Young et al. | Applicant |
| US4536733(A) | 1985-08-01 | Shelly et al. | Applicant |
| US4578664(A) | 1986-03-01 | Kinzler et al. | Applicant |
| US4583068(A) | 1986-04-01 | Dickens et al. | Applicant |
| US4616142(A) | 1986-10-01 | Upadhyay et al. | Applicant |
| US4675629(A) | 1987-06-01 | Sakamoto et al. | Applicant |
| US4801912(A) | 1989-01-01 | McElheny et al. | Applicant |
| US4803609(A) | 1989-02-01 | Gillett et al. | Applicant |
| US4897773(A) | 1990-01-01 | Bilczo | Applicant |
| US5006782(A) | 1991-04-01 | Pelly | Applicant |
| US5010261(A) | 1991-04-01 | Steigerwald | Applicant |
| US5079498(A) | 1992-01-01 | Cleasby et al. | Applicant |
| US5132888(A) | 1992-07-01 | Lo et al. | Examiner |
| US5186647(A) | 1993-02-01 | Denkmann et al. | Applicant |
| US5204809(A) | 1993-04-01 | Andresen | Applicant |
| US5276603(A) | 1994-01-01 | Stanley | Applicant |
| US5303115(A) | 1994-04-01 | Nayar et al. | Applicant |
| US5363035(A) | 1994-11-01 | Hutchison et al. | Applicant |
| US5402329(A) | 1995-03-01 | Wittenbreder, Jr. | Applicant |
| US5442317(A) | 1995-08-01 | Stengel et al. | Applicant |
| US5444600(A) | 1995-08-01 | Dobkin et al. | Applicant |
| US5475296(A) | 1995-12-01 | Vinsant et al. | Applicant |
| US5481238(A) | 1996-01-01 | Carsten et al. | Applicant |
| US5500629(A) | 1996-03-01 | Meyer | Applicant |
| US5509691(A) | 1996-04-01 | Kaule et al. | Applicant |
| US5583460(A) | 1996-12-01 | Dohi et al. | Applicant |
| US5610807(A) | 1997-03-01 | Kanda et al. | Applicant |
| US5636107(A) | 1997-06-01 | Lu et al. | Applicant |
| US5654881(A) | 1997-08-01 | Albrecht et al. | Applicant |
| US5687067(A) | 1997-11-01 | Majid et al. | Applicant |
| US5802709(A) | 1998-09-01 | Hogge et al. | Applicant |
| US5808537(A) | 1998-09-01 | Kondo et al. | Applicant |
| US5821832(A) | 1998-10-01 | Moreau | Applicant |
| US5875103(A) | 1999-02-01 | Bhagwat et al. | Applicant |
| US5889373(A) | 1999-03-01 | Fisher et al. | Applicant |
| US5999417(A) | 1999-12-01 | Schlecht | Applicant |
| US6049264(A) | 2000-04-01 | Sailer et al. | Applicant |
| US6054764(A) | 2000-04-01 | Howser et al. | Applicant |
| US6057665(A) | 2000-05-01 | Herniter et al. | Applicant |
| US6084790(A) | 2000-07-01 | Wong | Applicant |
| US6137389(A) | 2000-10-01 | Uchikoba | Applicant |
| US6144269(A) | 2000-11-01 | Okamoto et al. | Applicant |
| US6144565(A) | 2000-11-01 | Lethellier | Applicant |
| US6147886(A) | 2000-11-01 | Wittenbreder | Examiner |
| US6150798(A) | 2000-11-01 | Ferry et al. | Applicant |
| US6166527(A) | 2000-12-01 | Dwelley et al. | Applicant |
| US6184666(B1) | 2001-02-01 | Boeckmann et al. | Applicant |
| US6191673(B1) | 2001-02-01 | Ogura et al. | Applicant |
| US6229289(B1) | 2001-05-01 | Piovaccari et al. | Applicant |
| US6246592(B1) | 2001-06-01 | Balogh et al. | Applicant |
| US6255804(B1) | 2001-07-01 | Herniter et al. | Applicant |
| US6259235(B1) | 2001-07-01 | Fraidlin et al. | Applicant |
| US6272023(B1) | 2001-08-01 | Wittenbreder | Examiner |
| US6282103(B1) | 2001-08-01 | Naito et al. | Applicant |
| US6294882(B1) | 2001-09-01 | Blom | Applicant |
| US6310534(B1) | 2001-10-01 | Brunner | Applicant |
| US6356179(B1) | 2002-03-01 | Yamada | Applicant |
| US6362608(B1) | 2002-03-01 | Ashburn et al. | Applicant |
| US6362986(B1) | 2002-03-01 | Schultz et al. | Applicant |
| US6392902(B1) | 2002-05-01 | Jang et al. | Examiner |
| USRE37738(E) | 2002-06-01 | Brkovic | Applicant |
| US6404175(B1) | 2002-06-01 | Yang et al. | Applicant |
| US6430066(B2) | 2002-08-01 | Emori et al. | Applicant |
| US6459349(B1) | 2002-10-01 | Giday et al. | Applicant |
| US6462962(B1) | 2002-10-01 | Cuk | Applicant |
| US6483623(B1) | 2002-11-01 | Maruyama | Applicant |
| US6489756(B2) | 2002-12-01 | Kanouda et al. | Applicant |
| US6493242(B1) | 2002-12-01 | Riggio et al. | Applicant |
| US6512352(B2) | 2003-01-01 | Qian | Applicant |
| US6512437(B2) | 2003-01-01 | Jin et al. | Applicant |
| US6538905(B2) | 2003-03-01 | Greenfeld et al. | Applicant |
| US6628106(B1) | 2003-09-01 | Batarseh et al. | Applicant |
| US6683522(B2) | 2004-01-01 | Walsh | Applicant |
| US6686823(B2) | 2004-02-01 | Arntz et al. | Applicant |
| US6703815(B2) | 2004-03-01 | Biagi | Applicant |
| US6738274(B2) | 2004-05-01 | Prasad et al. | Applicant |
| US6798177(B1) | 2004-09-01 | Liu et al. | Applicant |
| US6820321(B2) | 2004-11-01 | Harding | Applicant |
| US6822427(B2) | 2004-11-01 | Wittenbreder | Applicant |
| US6853568(B2) | 2005-02-01 | Li et al. | Applicant |
| US6853588(B2) | 2005-02-01 | Kim et al. | Applicant |
| US6967553(B2) | 2005-11-01 | Jitaru | Applicant |
| US6995685(B2) | 2006-02-01 | Randall | Applicant |
| US7023313(B2) | 2006-04-01 | Sutardja | Applicant |
| US7161342(B2) | 2007-01-01 | Sutardja | Applicant |
| US7190152(B2) | 2007-03-01 | He et al. | Examiner |
| US2001/0052837(A1) | 2001-12-01 | Walsh | Applicant |
| US2002/0039061(A1) | 2002-04-01 | Timashov | Applicant |
| US2002/0080631(A1) | 2002-06-01 | Kanouda et al. | Applicant |
| US2002/0118000(A1) | 2002-08-01 | Xu et al. | Applicant |
| US2002/0136029(A1) | 2002-09-01 | Ledenev et al. | Applicant |
| US2003/0155898(A1) | 2003-08-01 | Olsen et al. | Applicant |
| US2003/0227366(A1) | 2003-12-01 | Lin | Applicant |
| US2006/0116623(A1) | 2006-06-01 | Han et al. | Applicant |
| DE3622190(A) | 1988-01-01 | Applicant | |
| DE19837639 | 2000-03-01 | Applicant | |
| EP484074(A) | 1992-05-01 | Applicant | |
| EP503715 | 1992-09-01 | Applicant | |
| EP632571(A) | 1995-01-01 | Applicant | |
| EP895257(A) | 1999-02-01 | Applicant | |
| EP929143 | 1999-07-01 | Applicant | |
| EP1239574(A2) | 2002-09-01 | Applicant | |
| GB2318691(A) | 1998-04-01 | Applicant | |
| JP57193007 | 1982-11-01 | Applicant | |
| JP58224420(A) | 1983-12-01 | Applicant | |
| JP61078111(A) | 1986-04-01 | Applicant | |
| JP6006195 | 1994-01-01 | Applicant | |
| JP10-023743 | 1998-01-01 | Applicant | |
| JP10-075164 | 1998-03-01 | Applicant | |
| JP11008123 | 1999-01-01 | Applicant | |
| JP11074125(A) | 1999-03-01 | Applicant | |
| JP11146638(A) | 1999-05-01 | Applicant | |
| JP11204354(A) | 1999-07-01 | Applicant | |
| JP2001-352748 | 2001-12-01 | Applicant | |
| JP2002-199708 | 2002-07-01 | Applicant | |
| JP2003332141(A) | 2003-11-01 | Applicant | |
| WO/74089(A1) | 2000-12-01 | Applicant | |
| WO1/43276 | 2001-06-01 | Applicant | |
| WO2/095775(A1) | 2002-11-01 | Applicant |
Non-Patent Literature (20)
- U.S. Appl. No. 10/621,058, filed Jul. 15, 2003, entitled, “Low Loss DC/DC Converter”.Applicant
- U.S. Appl. No. 10/693,787, filed Oct. 24, 2003, entitled, “Voltage Regulator”.Applicant
- U.S. Appl. No. 10/754,187, filed Jan. 8, 2004, entitled, “Digital Low Dropout Regulator”.Applicant
- U.S. Appl. No. 10/810,452, filed Mar. 26, 2004, entitled, “Voltage Regulator”.Applicant
- “Understanding Ferrite Bead Inductors”, http://www.murata.com, pp. 23-25 (Sep. 2005).Applicant
- “Using Ferrite Beads to Keep RF Out Of TV Sets, Telephones, VCR's, Burglar Alarms and Other Electronic Equipment,” http://www.antennex.com, pp. 1-4 (Sep. 27, 2005).Applicant
- Communication and partial European Search Report from the European Patent Office dated Oct. 6, 2006 for Application No. 04019981.2—1242.Applicant
- Communication from European Patent Office dated Aug. 6, 2007 for Application No. 07 004 458.1-1242; 5 pages.Applicant
- Communication from the European Patent Office dated Oct. 6, 2006 with the European Search Report for Application No. 04019978.8—1242; 3 pages.Applicant
- European Search Report for Application No. 04010841; 2 pages.Applicant
- European Search Report for Application No. 04011558.6, 2 pages.Applicant
- European Search Report for Application No. 04020568.4, 3 pages.Applicant
- European Search Report for Application No. 04020571.8, 3 pages.Applicant
- European Search Report for Application No. 05012809.9, 7 pages.Applicant
- Hayt and Kemmerly, “Engineering Circuit Analysis”, 1986, Mcgraw-Hill Book Company, Fourth Edition, pp. 442-443.Applicant
- Power Converter Topologies, How to Choose the Right One for Your Design; Dennis L. Feucht; Innovatia Laboratories; 2002; 4 Pages.Applicant
- Sanchis-Kilders E. et al; “New very low power, high efficiency, DC/DC power supply for LEO satellite constellation”; Power Electronics Specialists Conferences, 1999; pp. 1146-1151.Applicant
- U.S. Appl. No. 10/621,128, filed Jul. 16, 2003, entitled, “Power Inductor With Reduced DC Current Saturation”, pp. 1-33, and 6 sheets of drawings.Applicant
- U.S. Appl. No. 10/744,416, filed Dec. 22, 2003, entitled, “Power Inductor With Reduced DC Current Saturation”, pp. 1-39, and 9 sheets of drawings.Applicant
- Wei, Chen et al.; “Dual-loop feedback for fast low dropout regulators”; 32nd Annual IEEE Power Electronics Specialists Conference; 2001; pp. 1265-1269.Applicant