Signal Transfer Device Having a Transfer Characteristic Which Is Adjustable in Steps

The invention relates to a signal transfer device having a transfer characteristic which is adjustable in steps, which device comprises at least one group of controllable switches for transferring a signal from different inputs to an output, control means being provided for each time turning on one of said switches, which switches can be turned on and off by means of a control signal.

Such devices may be used for volume or tone control in audio amplifiers, such a volume control being, for example, known from Netherlands Patent Application No. 7811229, which has been laid open to public inspection. Electronic switches frequently exhibit an error voltage. If the device is changed over, a varying d.c. signal is produced, which d.c. signal comprises the successive different error voltages. In audio equipment the transitions between these different error voltages are reproduced as switching clicks, which are experienced as very annoying, particularly in the absence of a signal.

It is an object of the invention to provide a device of the type mentioned in the opening paragraph which does not have this drawback, and to this end the device is characterized in that there is provided a control-signal generator for generating a first control signal which gradually varies in time for gradually turning on a specific switch of said group, and for generating a second control signal, which is complementary to the first control signal, for at the same time gradually turning off another switch of said group.

Owing to the step in accordance with the invention the error voltages smoothly change into each other upon turn-on and hardly give rise to audible switching clicks.

The signal transfer device in accordance with the invention may further be characterized in that the group of switches is constituted by a group of differential pairs, each pair comprising a first and a second transistor whose collector output circuits lead to the output. The base electrode of the first transistors each individually lead to said different inputs, the base electrodes of the second transistors lead to a common terminal, and the emitter electrodes of the first and second transistors of each pair are connected to a control-signal input for receiving said control signals as a control current. This embodiment may further be characterized in that said common terminal is connected to the output so as to obtain a negative feedback. In this respect it is very advantageous that the switches can be switched on and off in a specific sequence and that the control signal inputs, in said sequence, are alternately connected to a first and a second output of the signal generator via transistor switches which can be controlled in such a way that each time only the emitter side of the transistor pair to be switched on and off is connected to the control signal generator.

With respect to the control signal generator, the signal transfer device may further be characterized in that the signal generator comprises a digital-to-analog converter synchronized by the control means for generating the control signals.

It is then advantageous that the control signal generator comprises a digital up/down counter which is controlled by a clock signal, which clock signal also synchronizes the control means. The count of said counter is applied to the digital-to-analog converter as an input signal.

The invention will now be described in more detail with reference to the drawing, which shows a preferred embodiment of a signal-transfer device in accordance with the invention and in which:

FIG. 1 represents the principle of the signal transfer device,

FIG. 2 is a table to explain the operation of the device shown in FIG. 1,

FIG. 3 shows an example of switchable amplifiers employed in the device shown in FIG. 1,

FIG. 4 is a signal diagram to explain the operation of the switchable amplifier shown in FIG. 3,

FIG. 5 shows an example of the control logic for controlling the device shown in FIG. 1, and

FIG. 6 is a time diagram of a number of signal generated by the control logic shown in FIG. 5.

FIG. 1 shows an embodiment of a step-controlled volume control circuit using the principle in accordance with the invention. The volume control comprises a signal input 1, which is connected to an amplifier 2, arranged as a voltage follower, having an output 3. Via a resistive divider network 4 the output 3 is connected to ground. The resistive divider network 4 is a so-called R-2R ladder network which provides an attenuation of 6 dB per step and which has 16 tappings L.sub.1 to L.sub.16. The tapping L.sub.1 supplies the full output voltage of the follower 2 and tapping 16 is connected to ground. The tappings L.sub.1, L.sub.3, L.sub.5, L.sub.7, L.sub.9, L.sub.11, L.sub.13 and L.sub.15 lead to a switching amplifier 5, which upon command of switching signals at inputs S.sub.1, S.sub.3, S.sub.5, S.sub.7, S.sub.9, S.sub.11, S.sub.13 and S.sub.15 connects one of said tappings to an output 6. The other tappings L.sub.2, L.sub.4, L.sub.6 , L.sub.8, L.sub.10, L.sub.12, L.sub.14 and L.sub.16 of the resistive divider network 4 lead to a switching amplifier 7, which on command of switching signals at inputs S.sub.2, S.sub.4, S.sub.6, S.sub.8, S.sub.10, S.sub.12, S.sub.14 and S.sub.16 connects one of said tappings to an output 8. The two switching amplifiers 5 and 7 are controlled in such a way that the outputs 6 and 8 each time carry the signals on two successive tappings, namely in such a way that each time one of the two switching amplifiers is switched to a following switching position. At the smallest attenuation the amplifier 5 connects tapping L.sub.1 to output 6 and amplifier 7 connects tapping L.sub.2 to output 8. The next attenuation step is obtained by turning on amplifier 5 so that tapping L.sub.3 is connected to output 6. Subsequently, amplifier 7 is switched over so that tapping L.sub.4 is connected to output 8. In this way the entire network 4 can be covered, outputs 6 and 8 always being connected to two successive tappings of the network 4 in such a way that outputs 6 and 8 alternately carry the highest signal level. This has the advantage that each time only one of the two amplifiers 5 and 7 is switched over. Between outputs 6 and 8 a linear attenuation network 9 is connected with tappings D.sub.1, D.sub.2, D.sub.3, D.sub.4, D.sub.5, D.sub.6 and D.sub.7. The tappings D.sub.1 and D.sub.7 respectively carry the voltages at outputs 6 and 8. The tappings D.sub.1 to D.sub.7 can each in turn be connected to an output 11 by means of a switching amplifier 10 on command of switching signals S.sub.21 to S.sub.27. The switching sequence of the tappings D.sub.1 to D.sub.7 is each time changed depending on the switching position of the switching amplifiers 5 and 7. If the amplifier 5 is in a position in which the tapping L.sub.1 is connected-through and amplifier 7 is in a position in which tapping L.sub.2 is connected-through, the switching amplifier 10 successively connects the tappings D.sub.1 to D.sub.7 to the output 11 with increasing attenuation. If subsequently at increasing attenuation the amplifier 5 is switched over so that it connects tapping L.sub.3 to output 6, then switching amplifier 10 successively connects tappings D.sub.7 to D.sub.1 to output 11 with increasing attenuation. The complete switching sequence is diagrammatically represented in FIG. 2, in which the two left-hand columns represent the relevant tapping of the resistive divider network 4 which is switched by the relevant amplifiers 5 and 7, the vertical arrows indicating the switching sequence, and in which the right-hand column represents the switching direction of the amplifier 10. It can be seen that the switching amplifiers 5 and 7 are each time changed over when the switching amplifier 10 has connected the respective tappings D.sub.7 and D.sub.1, which are connected to the respective non-switching amplifier 7 and 5, to output 11, which has the important advantage that switching clicks, caused by the switching amplifiers 5 and 7, cannot reach output 11.

In the control circuit of FIG. 1, the switching amplifiers 5, 7 and 10 are constructed as differential amplifiers having alternately switchable non-inverting inputs (A.sub.1, A.sub.3, A.sub.5, A.sub.7, A.sub.9, A.sub.11, A.sub.13, A.sub.15), (A.sub.2, A.sub.4, A.sub.6, A.sub.8, A.sub.10, A.sub.12, A.sub.14, A.sub.16) and (A.sub.21, A.sub.22, A.sub.23, A.sub.24, A.sub.25, A.sub.26, A.sub.27) respectively, which can be switched by a signal at the control inputs S of a corresponding sequence number. A signal at control input S.sub.21, for example, activates input A.sub.21. The switching amplifiers have an inverting input (-) connected to the relevant output so that the amplifiers act as voltage followers for the signal on at the switched input.

FIG. 3 shows an example of such a switching amplifier, namely the switching amplifier 10. It comprises 7 differential transistor pairs (T.sub.11, T.sub.12), (T.sub.21, T.sub.22), (T.sub.31, T.sub.32), (T.sub.41, T.sub.42), (T.sub.51, T.sub.52), (T.sub.61, T.sub.62) and (T.sub.71, T.sub.72). The base electrodes of the transistors T.sub.11, T.sub.21, T.sub.31, T.sub.41, T.sub.51, T.sub.61 and T.sub.71 are individually connected to the corresponding inputs A.sub.21, A.sub.22, A.sub.23, A.sub.24, A.sub.25, A.sub.26 and A.sub.27, the emitter electrodes each being connected to the emitter electrodes of the corresponding other transistor of the pair T.sub.12, T.sub.22, T.sub.32, T.sub.42, T.sub.52, T.sub.62 and T.sub.72 and the collector electrodes being jointly connected to positive power supply terminal (+) via a collector load 12. The base electrodes of the other transistors of the pairs are jointly connected to the inverting input (-) and the collector electrodes are jointly connected to the positive supply terminal via a collector load 13. As a result of this, the transistors--as is shown--may be constituted by multi-emitter transistors. The collector signals appearing across the loads 12 and 13 are amplified to an output 11 via a differential amplifier 14 and an output amplifier 15 and are then fed back to the inverting input (-).

In order to enable the inputs A.sub.21 to A.sub.27 to be activated individually, the emitter electrodes of the respective transistor pairs (T.sub.11, T.sub.12) to (T.sub.71, T.sub.72) are connected to emitter-current sources via the respective isolating transistors T.sub.1 to T.sub.7, whose base electrodes are connected to a source of reference voltage V.sub.ref, and via the respective switching transistors B.sub.21 to B.sub.27, whose base electrodes are each connected to the respective control inputs S.sub.21 to S.sub.27, which emitter-current sources may for example be resistors, so that by turning on the relevant switch an emitter current is produced which is determined by the reference voltage V.sub.ref and the value of the relevant resistor, as a result of which emitter current the corresponding input is activated and the signal present on said input appears on output 11. The amplifiers 5 and 7 may be constructed in a corresponding manner.

As already stated, the switching clicks produced in amplifiers 5 and 7 do not appear at output 11 in the control circuit shown in FIG. 1. However, the switching clocks produced in the amplifier 10 do appear at said output. These switching clicks are caused by each other pair exhibiting a specific error voltage so that this error voltage appears at output 11 as a low-frequency ripple as the various switching positions are passed through. FIG. 4 (continuous line) represents such a signal. In the case of suitably dimensioned integrated amplifiers this signal may still have a peak-to-peak value of .+-.2 mV. Although the switching signal itself is of comparatively low frequency, this switching signal, especially in the absence of an audio signal, will be reproduced as switching clicks, which switching clicks are determined by the higher harmonics associated with the steep edges of an error signal. These audible switching clicks can be avoided by not abruptly changing from the one to the other transistor pair (FIG. 3), but by simultaneously causing the emitter current of the turned-on pair to decrease and causing the emitter current of the pair to be switched to increase, so that a gradual transition from the one to the other error signal at output 11 is obtained, which is represented by the broken line in FIG. 4. As the present embodiment of the control circuit employs a fixed switching sequence, in which consecutively the switching transistors B.sub.21, B.sub.22, B.sub.23, B.sub.24, B.sub.25, B.sub.26 and B.sub.27 are turned off and on, it suffices to use two currents I.sub.1 and I.sub.2 which increase and decrease in phase opposition. Via the relevant switches--of which only one switch conducts at a time--the current I.sub.1 is applied to the transistor pairs corresponding to inputs A.sub.21, A.sub.23, A.sub.25 and A.sub.27 and the current I.sub.2 to the other transistor pair. The currents I.sub.1 and I.sub.2 can for example be obtained by means of a digital-to-analog converter controlled by a binary up/down counter.

FIG. 5 shows an example of a control device for generating the signals I.sub.1 and I.sub.2 and the control signals S.sub.1 to S.sub.16 and S.sub.21 to S.sub.27. FIG. 6 represent a number of signals to explain the operation.

This device comprises a clock generator 16, which via a gate circuit 17 produces a clock signal c (FIG. 6). This clock signal controls a 5-bit counter 18, whose first four (1 to 4) bits are employed as a binary input signal for the digital-to-analog converter. The fifth (5) and most significant bit is employed for changing over an inverting gate circuit, which inverts the first four bits. In this way the first four bits pass through a cycle from 0000 to 1111 and subsequently through the same cycle, but inverted, so that the four bits appearing at the outputs Q.sub.1 to Q.sub.4 of the inverting circuit 19 each time pass through an up-down cycle (0000.fwdarw.1111.fwdarw.0000). The inverting circuit 19 is assumed to be a so-called "open-collector" logic circuit, that is, the relevant output is connected to ground or is floating. Digital-to-analog conversion is then effected by arranging binary weighted resistors 20 with the values 8R, 4R, 2R and R at said outputs, so that in conjunction with the reference voltage V.sub.ref applied via transistors T.sub.1 to T.sub.7 (FIG. 3) the desired current I.sub.1 (FIG. 6) is obtained. The inverse current I.sub.2 (FIG. 6) is obtained in a corresponding manner by producing the inverse of the four bits in the inverting circuit 19 at outputs Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 and by also connecting said outputs to binary weighted resistors.

After each cycle of the digital-to-analog converter, for example at the instants t.sub.1 and t.sub.2 (FIG. 6) switching amplifier 10 should be switched one step further. For this purpose, the switching signals S.sub.21 to S.sub.27 (shown in FIG. 6) are generated by means of a 12-position counter 21, whose output signals are combined by means of the gate circuit 22, so that the desired sequence of switching signals S.sub.21 to S.sub.27 is obtained. These switching signals should each time overlap each other for half the time because each time two consecutive ones of the switching transistors B.sub.21 to B.sub.27 should conduct for the said emitter current cross-over (I.sub.1 and I.sub.2 in FIG. 6). The counter 21 is controlled by the fourth bit (4) from counter 18 so that the switching signals S.sub.21 to S.sub.27 are generated synchronously with the alternation of the currents I.sub.1 and I.sub.2 (as is illustraed in the timing diagram of FIG. 6).

Each time that switching amplifier 10 connects input A.sub.21 to output 11, switching amplifier 7 should make one switching step (in accordance with the table of FIG. 2) and each time that the switching amplifier (10) connects input A.sub.27 to output 11, the switching amplifier 5 should perform one switching step. For this purpose the signal S.sub.27 controls, via an AND-gate 35, an 8-position counter 23 which supplies the switching signals S.sub.1, S.sub.3, S.sub.5, S.sub.7, S.sub.9, S.sub.11, S.sub.13 and S.sub.15 in accordance with the timing diagram of FIG. 6. The signal S.sub.21 controls, via an AND-gate 36, and 8-position counter 24 which supplies the switching signals S.sub.2, S.sub.4, S.sub.6, S.sub.8, S.sub.10, S.sub.12, S.sub.14 and S.sub.16 in accordance with the timing diagram of FIG. 6. Both AND-gates 35 and 36, whose other inputs are connected to output 5 of counter 18, are needed so that the counters 23 and 24 are clocked at the centres of the pulses S.sub.27 and S.sub.21 respectively.

The progressive attenuation is activated by depressing a button 25 so that, via the gate circuit 17' the clock signal c is applied to counter 18. The gate switch 17 is such that it allows the clock signal to be transferred after release of the button 25 until the counter 18 has completed a current change via the digital-to-analog converter, which is effected by applying the 4.sup.th bit (4) of the counter 18 to the gate circuit 17, the start signal from the button 25 being prevalent.

In order to allow an increase in volume, the counters 21, 23 and 24 are provided with a counting sequence reversing input R. By means of a signal at this input the counting sequence can be reversed in a manner known per se. The counter 18 need not be reversed because the counters 21, 23 and 24 can only perform one counting step upon each completion of a change of the currents I.sub.1 and I.sub.2 and because the changing pattern of the currents I.sub.1 and I.sub.2 does not depend on the switching direction. A volume increase is initiated by pressing the push-button 28, after which a circuit 29 generates the signals for the counting sequence reversing input R and after which the gate circuit 17 transfers the clock signal. When the button 25 is depressed, the volume of the signal being produced decreases to zero, after which, if all counters would keep on counting, the maximum volume would be reproduced again all of a sudden, which is very annoying. In order to preclude this, the maximum attenuation position is decoded by combining the control signals S.sub.27 and S.sub. 16 by means of the NAND-gate 30. Via the AND-gate 31 the output of this NAND-gate 30 blocks the signal from the push-button 25 when the maximum attenuation is reached. In a corresponding manner, by combining the signals S.sub.21 and S.sub.1 by means of a NAND-gate 32 and, as a function thereof, blocking the signals from push-button 28, the clock signal is blocked by the gate circuit 17 when the minimum attenuation is reached.

The use of a digital-to-analog converter for generating the currents I.sub.1 and I.sub.2 makes it possible, by a non-linear choice of the amplitude of I.sub.1 and I.sub.2 as a function of time, to minimize the harmonics associated with the error voltage (FIG. 4). In this respect it is to be noted that the control logic shown in FIG. 5 is particularly suitable to be realized by means of a programmable control unit.