Voltage Generating System

This invention relates to voltage generating systems used for electronic tuners and digital-to-analog converter circuits etc., and it provides a system which permits a number of different voltages to be obtained with a simple construction.

In the commonly termed electronic tuner using a voltage variable capacitance diode as a tuning element, a number of channels are tuned in by switching the magnitude of the channel selection voltage applied to the variable capacitance diode,; therefore, it is necessary to be able to steadily obtain a number of voltages of different values. Heretofore, use has been made of a number of variable resistors for generating the different voltages. Therefore, the construction of the device has been mechanical and complicated, and this trend has been the more notable as the number of different voltages to generate increases. Besides, the stability of the voltage generated has depended on the stability of the source voltage and resistors.

Various digital and analog converters for converting a digital input to an analog output are used. Conventionally a digital-to-analog converter has been used in which a row of resistors, which are switched by switching means driven by individual bits of a digital signal input is used. In these prior-art digital-to-analog converters, the construction becomes complicated when the number of different available voltages is increased. Also, the stability of the output voltage has depended on the stability of the resistors. Further, since accurate fine adjustment of the resistances of the number of resistors is needed, incorporation of this structure into monalithic integrated circuits has been difficult. A further inconvenience is due to the fact that the step ratio of the analog output voltage has been restricted to a constant ratio.

The above various inconveniences have also been encountered with various other voltage generating means.

An object of the invention, accordingly, is to provide a volage generating system, which can be extensively used for electronic tuners (varactor tuners), digital-to-analog converters and other circuits, permits a number of different voltages to be obtained with a comparatively simple construction switches these voltages with simple means, and is further capable of incorporation into integrated circuits.

The above and other objects, features and advantages of the invention will become more apparent from the following description when the same is read with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram showing a prior-art voltage generating system;

FIG. 2 is a circuit diagram showing an embodiment of the voltage generating system according to the invention;

FIGS. 3 to 6 are waveform charts for illustrating the operating mode of the same system;

FIGS. 7a and 7b show a chart illustrating the operating mode of the same system;

FIGS. 8 to 10 are circuit diagrams showing respective logic circuits required for producing switching pulse signals for controlling the same system;

FIG. 11 is a circuit diagram showing a means for producing a clock pulse signal necessary for the operation of the same system;

FIG. 12 is a waveform chart to illustrate the operation of the circuit of FIG. 11;

FIG. 13 is a chart illustrating the operating mode of another embodiment of the voltage generating system according to the invention;

FIG. 14 is a schematic of the same system;

FIG. 15 is a circuit diagram showing part of the same system;

FIG. 16 is a waveform chart to illustrate the operation of the same system;

FIG. 17 is a waveform chart to illustrate the operational principles of a further embodiment of the invention applied to a digital-to-analog converter;

FIG. 18 is a schematic of the same digital-to-analogue converter;

FIG. 19 is a waveform chart to illustrate the operation of the same digital-to-analog converter; and

FIG. 20 is a circuit diagram showing a different example of an averaging circuit used in the same digital-to-analog converter.

A prior-art voltage generating system will first be described with reference to FIG. 1. In the figure, 1a, 1b, . . . , 1n designate voltage presetting variable resistors which are commonly connected at their one end to a power supply 2. These variable resistors 1a, 1b, . . . , 1n are on-off switched by respective switching transistors 3a, 3b, . . . , 3n connected to their other ends. When one of the transistors 3a, 3b, . . . , 3n, for instance transistor 3b, is rendered "on" and other transistors are all "off", only a diode 4b connected to the tap of the variable resistor 1b connected to the transistor 3b is made conductive since the tap voltage on the other variable resistors is constituted by the source voltage. Thus, the tap voltage on the variable resistor 1b alone is taken out as an output voltage from an output terminal 6 through a transistor 5 connected as an emitter follow.

With this arrangement, the number of different output voltages that can be obtained from the output terminal 6 is identical with the number of the voltage presetting variable resistors 1a, 1b . . . , 1n. Therefore, to increase the number of available voltages with different values a corresponding increased number of variable resistors is required and more space becomes necessary. Also, this increases the rate of occurrence of failure due to contact failure etc. of the variable resistors. In addition, the preset voltages are subject to fluctuations due to such causes as temperature and relative humidity changes. Further, complicated construction is required for the circuit for selecting a desired one of these many variable resistors.

A first embodiment of the invention will now be described with reference to FIGS. 2 to 10.

FIG. 2 shows an example of the voltage producing circuit using a plurality of variable resistors. Here, a plurality of variable resistors for voltage presetting, 7a, 7b, . . . , 7n, as means for producing a plurality of reference voltages are commonly connected at their one end to a power supply 8. These variable resistors are on-off switched by respective switching transistors 9a, 9b, . . . , 9n, which are connected to the other ends of the variable resistors and serve as means to select a desired one or more of the plurality of reference voltages. The taps of the variable resistors 7a, 7b, . . . , 7n are connected through respective diodes 10a, 10b, . . . , 10n to a common juncture connected through a resistor 11 to the power supply 8. Thus, when any of the transistors 9a, 9b, . . . , 9n is rendered on, for instance transistor 9b, it is possible to take out only the tap voltage on the associated variable resistor 7b. This tapped voltage is smoothed by a low-pass filter 12 consisting of an integrating circuit serving as a smoothing circuit and then coupled to a transistor 13 for impedance conversion to take out from an output terminal 14 the tapped voltage as an output voltage.

The transistors 9a, 9b, . . . , 9n here are switched with a special interval to vary the output voltage.

More particularly, the waveform of a switching pulse signal coupled to the bases of the transistors from respective terminals 15a, 15b, . . . , 15n is varied to vary the magnitude of the output voltage. This will now be discussed in detail.

Table 1 below shows a relation between an input switching pulse signal coupled to the terminals 15a and 15b and the output voltage when the duty ratio of the waveform of the input switching pulse signal is 1/2 as shown in a and b of FIG. 3.

Table 1 shows that not only voltages V.sub.A and V.sub.B which are reference voltages specified by the respective variable resistors 7a and 7b, but also a voltage of a level in the middle of V.sub.A and V.sub.B can be obtained as the output voltage.

Table 2 below shows a case with input switching pulse signals with respective duty ratios of 1/3 and 2/3 as shown in a and b of FIG. 4.

In this case, voltages at levels trisecting the interval between V.sub.A and V.sub.B and be obtained as the output voltage in addition to V.sub.A and V.sub.B.

Likewise, Tables 3 and 4 below respectively show a case with input switching pulse signals with respective duty ratios of 1/4, 1/2 and 3/4 as shown in a to d of FIG. 5 and a case with input switching signals with respective duty ratios of 1/5, 2/5, 3/5 and 4/5 as shown in a to d of FIG. 6.

In this way, voltages of levels intermediate two fixed voltages can be obtained by varying the duty ratio of two opposite-phase input switching pulse signals. Further, it is of course possible to use three reference voltages with three-phase pulse signals or four reference voltages with four-phase pulse signals.

FIGS. 7a and 7b show a chart of an example of the operating mode of producing station selection preset voltages on the basis of the principles underlying the invention applied to an electronic tuner for U.S.A. standard television receivers. Here, a total of 82 channels are covered, with channels No. 2 to No. 6 being LOW VHF channels, channels No. 7 to No. 13 being HIGH VHF channels and channels No. 14 to No. 83 being UHF channels. The numbers indicated at the top row of the chart are ones of preset volume for generating 29 reference voltages. This chart indicates that to the transistors, connected respectively to the corresponding preset variable resistors, are applied the reference voltages, each capable of selecting a channel whose number is indicated by one of the transistors.

The logic means for coupling a switching pulse signal to some of these variable resistors, namely VR.sub."XO.sub." (with the subscript representing the channel number and X being 2, 3, 4, . . . ) is, in general, as shown in FIG. 8, although there is some difference at each boundary between bands, as all the channels are roughly divided into three bands. For example, for VR.sub."+", with X = 3, the output at the output terminal of the reference voltage from VR.sub."XO" is ".phi..sub.1 " for channel No. 27, ".phi..sub.` " for channel No. 28, ".phi..sub.1 " for channel No. 29, "1" for channel No. 30 and ".phi..sub.2 " for channel No. 31 and is "0" for the other channels. This conforms to the chart of FIGS. 7a and 7b, and in general this is so except at the boundaries of the three bands, namely HIGH VHF, LOW VHF and UHF bands, into which all the channels fall. FIG. 9 shows a logic means for applying a switching pulse signal to the switching transistor connected to the variable resistor VR.sub."X2" for the channel "X2" (with X being 2, 3, 4, . . . ), and FIG. 10 shows a logic means for coupling a switching pulse signal to the switching transistor connected to the variable resistor VR.sub."X6" (with X being 2, 3, 4, . . . ). In FIGS. 8 to 10, symbols "1", "2", "3", . . . at respective input terminals designate signals representing the first digit of the channel number; for example, the signal "1" is "1" (i.e., at high level) if the first digit of the channel number of the channel to be tuned in is 1 and "0" (i.e., at low level) in the other cases. On the other hand, symbols "1", "2", "3" designate signals which are "0"(low level) if a channel of a channel number of the corresponding first digit is to tuned in and "1" in the other cases. The waveforms of the signals .phi.".sub.1 ", .phi.".sub.1 ", ".phi..sub.2 " and ".phi..sub.2 " are as shown in FIG. 5.

The signals ".phi..sub.1 ", ".phi..sub.1 ", ".phi..sub.2 " and ".phi..sub.2 " can be produced in a simple way, for instance by coupling a suitable clock pulse input to an input terminal 16 of the circuit shown in FIG. 11, which circuit is a combination of a divider circuit in which T-type flip-flops 17 and 18 are connected in cascade and a gate 19. Their waveforms are shown in FIG. 12. The duty ratio of the waveforms thus formed will not change with voltage or frequency, therefore, the afore-mentioned voltage division ratio is very steady. The waveform of the input to the terminal 16 is shown at a in FIG. 12, and the waveforms of the outputs Q.sub.1 and Q.sub.2 of the flip-flops 17 and 18 are shown at b and c respectively.

By adopting these logic systems the number of reference voltages can be reduced toward the number of different voltage outputs that are obtainable; in the example of the afore-mentioned U.S.A. channel 82 kinds of different channel selection voltages are obtainable from 29 different reference voltages and two switching pulse signals with a very simple circuit construction. Also, if the voltage output from the variable resistor 7b in the circuit of FIG. 2 is always greater than that from the variable resistor 7a, it is possible to hold the transistor for the variable resistor of the greater voltage value in the "on" state and switch the transistor for the variable resistor of the smaller voltage value.

As mentioned above, the voltage generating system according to the invention permits a number of different voltages to be obtained with less reference voltages, so that it is very convenient for use in electronic tuners for television receivers.

With reference to FIGS. 13 to 16 there will be described a second embodiment of the invention applied to an electonic tuner for a television receiver, and in which 31 different channel selection voltages for channels No. 30 to No. 60 are made available by the use of only seven different reference voltages from seven variable resistors a to g. FIG. 13 shows a chart for the operation of this embodiment. Here, seven variable resistors 7a to 7g are provided as shown in FIG. 14, which resistors are for generating reference voltages at every 5 channels, and it is so constructed as to generate channel selection voltages for channels No. 30, No. 35, No. 40, No. 45, No. 50, No. 55 and No. 60. In FIG. 13, symbols ".phi..sub.1 ", ".phi..sub.1 ", ".phi..sub.2 " and ".phi..sub.2 " in each column represent that each of the variable resistors 7a to 7g is operated with the duty ratios of ".phi..sub.1 ", ".phi..sub.1 ", ".phi..sub.2 " and ".phi..sub.2 " shown in Table 4 and FIG. 6, the symbol "on" represents that it remains "on" or conductive, and blank portions represent that it remains non-conductive.

FIG. 14 shows a specific circuit construction for realizing the above operation. In this embodiment, a channel number is keyed in by a keyboard 15 and is memorized, and according to this memorized number the duty ratio of switching pulse signals applied to the switching transistors 9a to 9g for the respective variable resistors 7a to 7g is varied. Also, in this system the section for memorizing the keyed-in channel number and the section for varying the duty ratio of the input switching pulse signals to the switching transistors 9a to 9g for the variable resistors 7a to 7g can be made with a simple circuit construction. This embodiment will be described in detail as follows.

In this system, in the switching pulse signals of different duty ratios to be applied to the variable resistors 7a to 7g the signals ".phi..sub.1 " and ".phi..sub.2 " can be obtained by inverting the respective signals 37.phi..sub.1 " and ".phi..sub.2 " as is apparent from Table 4 and FIG. 13. Thus, the pulses to be produced by a pulse generating circuit 16a may be basically either signals ".phi..sub.1 " and ".phi..sub.2 " or signals ".phi..sub.1 " and ".phi..sub.2 ". A specific example of this circuit is shown in FIG. 15. This circuit is a counter where a clock pulse signal from a clock oscillator 17a is frequency divided to 1/5 through flip-flops 18a 19a and 20 and AND gate 21, and ".phi..sub.2 " (and ".phi..sub.2 ") can be obtained from the flip-flop 19a and ".phi..sub.1 " (and ".phi..sub.1 ") from the flip-flop 20.

The section for memorizing a keyed-in channel number will now be described. In this section, 10 key switches 22 in the keyboard 15, corresponding to the respective digits "0" to "9", are combined in five pairs of digits "0" and "5", "1" and "9", "2" and "8", "3" and "7", and "4" and "6", and for every pair, when any one of the numbers is keyed in by the keyboard 15, the numbers are memorized by the flip-flops 23a to 23e. This combination of digits in pairs is, as it is apparent from Table 4 and FIG. 13, based on the fact that the operating mode of each of the variable resistors 7a to 7g is the same irrespective of which one of paired digits "0" and "5", "1" and "9", "2" and "8", "3" and "7" or "4" and .-+.6" is keyed in. With this arrangement, the circuit processing can be simplified. In this case, however, additional flip-flops 23f and 24f are provided for discriminating whether the keyed-in digit belongs to the group of digits "0" to "4" or the group of digits "5" to "9". More particularly, the key switches 22 in the keyboard 15 are divided into two groups, and when an input representing a digit in one of the groups, namely the group of digits "0" to "4", is keyed-in, it is detected by a detecting circuit 25 and memorized in the flip-flop, 23f indicating that a number in the group has been inputted.

A channel number is keyed in by operating the keyboard 15 either once (in case of a one-digit channel number) or twice (in case of a two-digit channel number). Accordingly, a memory control circuit 26 is provided to control the flip-flops 23a to 23f and further flip-flops 24a to 24f. When the keyboard is operated for the first time, the control circuit delivers a reset pulse to reset the flip-flops 23a to 23f and 24a to 24f so as to register the keyed-in digit in the flip-flops 23a to 23f. When and only when the keyboard is operated once again within a predetermined interval of time (of about 2 to 3 seconds), the control circuit delivers a shift pulse to open shift gates 27a 27f so as to transfer the memorized content of flip-flops 23a to 23f to the flip-flops 24a to 24f and delivers a new reset pulse to the flip-flops 23a to 23f to register the newly keyed-in digit therein. If the second operation of the keyboard is not made within the predetermined time interval, the memoriying operation is ended by concluding that the keyed-in channel number is a one-digit channel number. FIG. 16 shows a timing chart of he memorizing operation. In the Figure, there is indicated at a the timing of the operation of the keyboard 15, at b the reset pulses delivered to the flip-flops 23a to 23f, at c the transfer pulse delivered to the transfer gates 27a to 27f, and at d the reset pulse delivered to the flip-flops 24a to 24f. In effect, a memory unit 28 is constituted by the flip-flops 23a to 23f, which eventually memorize the unit's place digit, and the flip-flops 24a to 24f, which memorize the ten's place digit.

Now, a section for producing a required voltage from the afore-mentioned switching pulse signals ".phi..sub.1 ", ".phi..sub.1 "; ".phi..sub.2 " and ".phi..sub.2 " and the memorized channel number will be described. This section includes a pulse selecting circuit 29, a "5" discriminating circuit 31, a "Y" and "Y" generating circuit 33 and a variable resistor drive circuit 35. In the pulse selecting circuit 29, the pulse signals ".phi..sub.1 ", ".phi..sub.2 "; ".phi..sub.1 " and ".phi..sub.2 " are coupled to respective NAND e 30b to 30e to which the memory content of the unit's place digit of the channel number from the flip-lops 23b to 23e is also coupled, whereby ".phi..sub.1 " is taken out as output ".phi." when the unit's place digit of the channel number is either "1" or "9", ".phi..sub.2 " when the digit is either "2" or "8", ".phi..sub.2 " when the digit is either "3" or "7", and ".phi..sub.1 " when the digit is either "4 or 6". When the digit is either "0" or "5", the output ".phi."remains at a high level. In the "5" discriminating circuit 31, the outputs of the flip-flops 23a and 23f are coupled to a NAND gate 32a to produce an output which is at high level when the unit's place digit is "0". This output is coupled together with a signal ".phi." from an inverter 32b inverting the output ".phi." to a NAND gate 32c to obtain an output ".phi.'", which is at a low lever when the unit's place digit of the channel number is "0", is at high level when the digit is "5", and is the same as the output ".phi." in the other cases. In the pulse separation circuit 33, the output ".phi.'" and the output of the flip-flop 23f are coupled to a NAND gate 34a, while the output ".phi." and an inversion output obtained from the output of the flip-flop 23f are coupled to a NAND gate 34b whereby outputs "Y" and "Y'" are separately obtained, the former being provided when the unit's place digit of the channel number belongs to the group of digits "0" to "4" and the latter provided when the digit belongs to the group of digits "6" to "9". Thus, the output "Y" is at low level for digit "0", ".phi..sub.1 " for digit "1", ".phi..sub.2 " for digit ".phi..sub.2 ", , for digit "3" and ".phi..sub.2 " for digit "4", while the output "Y'" is ".phi..sub.1 " for digit "6", ".phi..sub.2 " for digit "7", ".phi..sub.2 " for digit "8" and ".phi..sub.1 " for digit "9".

In the variable resistor drive circuit 35, the variable resistor to be operated is selected from the variable 7a to 7g in correspondence to the keyed-in channel number. Here, NOR gates 36a, 36c, 36e, 36g, 37a, 37c, 37e, 37g, 38b, 38d and 38f are provided. The output "Y'" is coupled to the NOR gates 36a, 36c, 36e and 36g, the output "Y" is coupled to the NOR gates 37a 37c, 37e and 37g, and the output ".phi."is coupled to the NOR gates 38b, 38d and 38f. NAND gates 39a to 39e are also provided to detect the ten's place digit of the keyed-in channel number, and their ouptuts are coupled to the corresponding NOR gates respectively. The outputs of the NOR gates 36a and 37a are coupled in OR and are connected to a switching transistor 9a. Similarly, the outputs of the NOR gates 36c and 37c, 36e and 37e, and 36g and 37g are coupled in OR and are connected to respective switching transistors 9c, 9e and 9g.

With the above construction, the variable resistors 7a to 7g are operated in the mode as shown in FIG. 13 to obtain a required voltage.

As has been shown, in the proceding embodiment 31 different voltages for channels No. 30 to No. 60 can be obtained by means of 7 variable resistors 7a to 7g, and the structure therefor can be made simple.

In the preceding embodiment the variable resistors are provided at every five steps, however, according to the invention it is of course possible to divide them into any number of steps and to carry out the generation of the voltage. In this case, one may use adequate pulse signals with duty ratios corresponding to the division. In the preceding embodiment the key switches in the channel number input signal memorizing section are divided into two groups, one for digits "0" to "4" and the other for digits "5" to "9", and arranged into five pairs for digits "0" and "5", "1" and "9", "2" and "8", "3" and "7", and "4" and "6", however, one may memorize the number by dividing the numbers into any group and making any kind of combination, with the provision of memorizing means for memorizing which group the specified digit belongs to. For example, where there are (n + 1) specific input signals from m to (m + n) they may be divided into two groups, one consisting of signals m to ##EQU1## and the other consisting of signals ##EQU2## to (m + n), and arranged in pairs m and ##EQU3## (m + 1) and (m + n - 1), (m + 2) and (m + n - 2), . . . . , and means for memorizing which group the keyed input signal belongs to may be provided. In this case, the duty ratio for taking out a voltage from the reference voltage generating means such as variable resistors may be adapted to be varied at a step of With such arrangement, the output voltage may be readily varied in a simple manner as in the preceding embodiment.

As has been shown, the present voltage generating system is featured by providing a first memorizing means for dividing a plurality of specific input signals, such as channel number signals which are inputted from the input means such as a keyboard, into a plurality of groups, for combining these input signals into sets, the signals in each set taken out being one signal from every one of the divided groups, and for memorizing input signals for every set which is arranged as mentioned above, a second memorizing means for memorizing to which group the input signal belongs, means for generating a plurality of reference voltages, switching means for taking out any one or any plurality of the reference voltages at any duty ratio and means for taking the average value of the taken-out voltage as the output voltage. The duty ratio of the switching means is controlled by the output of both said memorizing means so as to produce an output voltage corresponding to the keyed-in input signal. Thus, it is possible to produce a great number of voltages of different values with less number of reference voltage generating means and also simplify the construction for switching the different voltages.

With reference to FIGS. 17 to 20 there will be described a further embodiment of the invention applied to a four-bit digitial-to-analog converter. The principles underlying this system will first be described with reference to FIG. 17. In this system, four different pulse signals, whose duty ratios are respectively 1/16, 2/16, 4/14 and 8/16, in which pulse periods do not overlap with one another, as shown at a, b, c and d in FIG. 17, are produced. Denoting the amplitude of these pulse signals a, b, c, and d by 1, their average values obtainable by smoothing them are respectively 1/16, 2/16, 4/16 and 8/16. These pulse signals a, b, c and d are made to correspond to respective bits in the 4-bit input digital signal, that is, it is so made that 2.sup.0 selects the pulse a, 2.sup.1 the pulse b, 2.sup.2 the pulse c, and 2.sup.3 the pulse d. In accordance with the input digital signal one or more of these pulse signals are selected, and the total pulse output of the selected signals is averaged, whereby a 15-step analog output voltage can be taken out in accordance with a 4-bit digital input signal.

A specific circuit for executing such function will now be described with reference to FIGS. 18 to 20. In FIG. 18, designated at 40 is a pulse generating circuit for generating the aforementioned pulse signals a, b, c, and d. In this circuit, a clock pulse as shown at e in FIG. 19 produced from a non-stable multi-vibrator 41 is supplied to a hexadecimal counter 42 to produce four frequency divided outputs as shown in f, g, h and i of FIG. 19 at their respective bit output terminals. These frequency divided output are combined through NAND gates 43, 44 and 45, NOR gates 46 and 47 and inverters 48, 49 and 50 to obtain the prescribed pulse signals a, b, c, and d shown in FIG. 17. FIG. 19 shows waveforms appearing at various parts of the pulse generating circuit 40. It will be seen that the prescribed pulse signals are obtained in the inverted form, namely q = a, n = b, k = c and j =d. Designated at 51 in FIG. 18 is an input specifying circuit for specifying a 4-bit digital input signal. Its 2.sup.0 -, 2.sup.1 -, 2.sup.2 - and 2.sup.3 -bit outputs are fed to a pulse selecting circuit 52. In this circuit, the individual bit signals are inverted through respective inverters 53 to 56 and then applied to respective NOR gates 57 to 60, to which the pulse outputs q, n, k and j from the pulse generating circuit 40 are also applied at their other input terminals. In this way, the switching pulse signals a, b, c, and d selected in correspondence to the input digital signal are taken out from the output side of the NOR gates 57 to 60. These switching pulses a, b, c and d are coupled to the bases of switching transistors 62 and 65 of a switching circuit 61 for switching reference voltages according to the selected switching pulse signals. Thus, a pulse output having a duty ratio corresponding to the input digital signal is obtained at the output terminal of the switching circuit 61, and this output is smoothed through a smoothing circuit 70 consisting of resistors 66 and 67 and capacitors 68 and 69 to take an average value, which is taken out through an output circuit 71. In this way, a 16-step analog output voltage corresponding to the input digital signal can be obtained from an output terminal 72. Designated at 73 is an input terminal for coupling a control signal for on and off control of the operation.

In this way, a digital-to-analog conversion can be carried out without using a number of resistor rows. Also, since there is no need of adjusting resistances, it becomes easy to incorporate the system into a monolythic integrated circuit. Further, the step of the analog output voltage can be readily varied by varying the duty ratio of the pulse signals produced by the pulse generating circuit.

In addition, the pulse generating circuit 40 and pulse selecting circuit 52 may be replaced with other suitable logic means. Also, the switching transistors 62 to 65 in the switching circuit 61 may be dispensed with by arranging such that the gates also take their role. Alternatively, it is possible to use other switching means than the transistors. Further, it is possible to use as the averaging circuit a Miller integrating circuit using an operational amplifier 73 as shown in FIG. 20.

Moreover, the number of steps of the analog output voltage may be increased by increasing the bit number of the input digital signal and the kind of the switching pulses, i.e., the kind of duty ratios. Alternatively, a plurality of source voltages for switching may be provided to increase the step number of the analog output voltage.

As has been shown, with the system of this invention the digital-to-analog conversion can be carried out without using a row of resistors, and also incorporation of the system into an integrated circuit and variation of magnitude, number of steps and step ratio of the analog output voltage can be readily accomplished.