Charge-coupled device having multiple readout paths for multiple outputs

[0001] The invention relates generally to the field of charge-coupled devices and, more particularly, to such charge-coupled devices having four readout devices for permitting efficient readout of the image signal.

[0002] Typically, prior art charge coupled devices, such as that disclosed in EPO Patent EP0866502, discloses a sub-array of pixels respectively coupled to 4 intermediate registers. The four intermediate registers are respectively coupled to four horizontal register segments each of which is coupled to an output node structure.

[0003] Although the presently known charge-coupled devices are satisfactory, improvements are always desirable. A variety of multiple output designs permit design choices during manufacturing which is always desirable due to flexibility in layout, cost efficiencies and spatial considerations.

[0004] Consequently, a need exists for an image sensor with four readouts that permits alternative design choices.

[0005] The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in an image sensor comprising a plurality of pixels arranged in at least two sub-arrays; first and second delay areas respectively connected to each sub-array for respectively receiving charge from the sub-array; wherein a pitch of the first delay area is different from the second delay area; and at least two readout mechanisms for respectively receiving the charge from the delay areas, wherein a same line from the first and second sub-arrays is received by each delay area at substantially the same time.

[0006] These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.

[0007] The present invention has the following advantage of an image sensor with four readout devices that consumes less surface area than the prior art and consequently has lower associated costs.

[0012] Referring to FIG. 1, there is shown a top view of the image sensor 10 of the present invention, preferably a charge-coupled device. The image sensor 10 includes a plurality of pixels 20 arranged in a plurality of rows and columns which, in turn, is arranged into a plurality of sub-arrays 30a, 30b, 30c and 30d, four sub-arrays in the preferred embodiment. A delay area 40a, 40b, 40c and 40d is respectively connected to each sub-array 30a, 30b, 30c and 30d for receiving charge from the sub-arrays. A horizontal readout 50 is respectively connected to each delay area 40a, 40b, 40c and 40d for receiving the charge from the delay areas 40a, 40b, 40c and 40d for further processing.

[0013] Referring to FIGS. 1 and 2, the outer delay areas 40a and 40d preferably include the same pitch as the sub-array 30a and 30d to which it is respectively connected. The inner delay areas 40b and 40c preferably include a pitch, which is a multiple of two longer than the outer delay area 40a and 40d. In essence, the pitch of the outer delay areas 40a and 40d should be different from the inner delay areas 40b and 40c. It is noted that the outer and inner delay areas 40a, 40b, 40c and 40d preferably include the same number of delay elements 60. This enables the same line from the outer and inner delay areas to be received by each horizontal readout 50 at substantially the same time. It is also instructive to note that the outer and inner delay areas 40a, 40b, 40c and 40d are operated at the same clock cycle in this embodiment. The clock cycles could be different if the number of delay areas is correspondingly altered. A light shield 70 spans and covers the delay areas 4a-d for prohibiting light from being disposed on the delay areas 40a, 40b, 40c and 40d. (FIG. 1 discloses only the light shield 70 covering the delay areas 40c and 40d for clarity of illustrating the light shield.)

[0014] Referring to FIG. 3, there is shown an alternative embodiment of the present invention. In this embodiment, the number of delay elements 60 in the outer 40a and inner delay 40b areas are different, for example by a factor of 2. (Delay area 40b includes twice as many delay elements as delay area 40a) The clock cycles would be corresponding different so that the same line from the sub-arrays is received by the horizontal readout at substantially the same time. For example, the clock cycle of the delay area with the greater number of delay elements would be operated at twice as fast as the delay area with the lesser number of delay elements.

[0015] Referring to FIG. 4, there is shown a digital camera 80 for illustrating a typical commercial embodiment for the image sensor 10 of the present invention. As is well known in the art, the image sensor 10 is disposed in the camera 80 for capturing incident light that is converted into electrons for forming an electronic representation of an image.

[0016] The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.

• [0017] 10 image sensor
• [0018] 20 pixels
• [0019] 30a sub-array of pixels
• [0020] 30b sub-array of pixels
• [0021] 30c sub-array of pixels
• [0022] 30d sub-array of pixels
• [0023] 40a delay areas
• [0024] 40b delay areas
• [0025] 40c delay areas
• [0026] 40d delay areas
• [0027] 50 horizontal readout outputs
• [0028] 60 delay elements
• [0029] 70 light shield
• [0030] 80 digital camera