Phase-locked loop with tunable-transfer function

[0001] Phase-locked loops are generally implemented using integrated circuits and may be utilized for a variety of purposes. For example, phase-locked loops may be utilized for clock recovery, frequency synthesis, and so on. The different uses of the phase-locked loops, however, may have differing requirements that may make a phase-locked loop that is optimized for a particular application less suitable (and even unsuitable) for use in a different application. Therefore, traditional techniques that were utilized to design phase-locked loops were tailored to the particular applications, in which, the respective phase-locked loop was to be utilized.

[0007] The same reference numbers are utilized in instances in the discussion to reference like structures and components.

[0008] In the following discussion, exemplary devices are described which may provide and/or utilize tuning for a phase-locked loops. Exemplary procedures are then described which may be employed by the exemplary devices, as well as by other devices.

[0009] Exemplary Devices

[0010] FIG. 1 illustrates an exemplary implementation 100 of a computing device 102 that is operable to employ tuning techniques for phase-locked loops. The computing device 102 may be configured in a variety of ways. For example, the computing device 102 may be configured as a desktop personal computer (PC), a notebook computer, a wireless phone, a server, a wireless base station, as local area network (LAN) equipment, a network access device (e.g., a broadband access device), a personal digital assistant (PDA), and so on.

[0011] The computing device 102 is illustrated as including one or more integrated circuit(s) 104, at least a portion of which are configured to provide a phase-locked loop 106. The phase-locked loop (PLL) 106 may be utilized for a variety of purposes, such as clock recovery, frequency synthesis, and so on. For example, the PLL 106 may be configured to phase align a reference clock source 108 (i.e., a signal source) with a clock signal destination 110, such as to align an internal core clock with a bus clock. The integrated circuit(s) 104, for instance, may include circuits which operate at a frequency that is “higher” relative to a frequency, at which, other circuits of the integrated circuit(s) 104 operate. Therefore, the PLL 106 is operable to enable data to be exchanged between these circuits by phase synchronizing respective clocks. A variety of other examples are also contemplated.

[0012] The PLL 106 has a transfer function, which may be thought of as a mathematical representation of a relationship between an input and an output of the PLL 106. Accordingly, the transfer function of the PLL 106 may play an important role in the computing system's performance. For example, as previously described PLLs may be optimized for different applications. Therefore, these different PLLs may have different respective transfer functions which have different respective “trade-offs” in the operation of the PLL 106. For instance, relatively higher bandwidth of the PLL 106 may better suppress thermal noise and supply noise, but relatively lower bandwidth may better suppress phase noise of a reference clock. In another instance, increasing the damping factor may reduce the peaking of the transfer function and thereby reduce phase noise on the peaking frequency, however, it may also increase cycle-to-cycle jitter resulting from the techniques used to increase the damping factor. A variety of other instances are also contemplated.

[0013] As illustrated in FIG. 1, the PLL 106 includes a tunable-transfer function 112 that, accordingly, provides adjustability of the transfer function of the PLL 106. Therefore, the PLL 106 may be employed in a variety of environments and may be tuned to be optimal for the respective environment, in which, it is employed, further discussion of which may be found in relation to FIG. 2.

[0014] The integrated circuit(s) 104 of the computing device 102 are further illustrated as including a feedback divider 114. The feedback divider 114 is operable to further control operation of the PLL 106. For example, the feedback divider 114 divides the output of the PLL 106, a result of which is then provided back to the PLL 106 for further comparison. By dividing the result, the PLL 106 may be used to generate a frequency that is greater than the reference frequency, further discussion of which may be found in relation to the following figure.

[0015] FIG. 2 illustrates an exemplary implementation of a system 200 showing the PLL 106 of FIG. 1 in greater detail. The PLL 106 is implemented as a negative feedback system that includes a phase frequency detector (PFD) 202; one or more charge pumps (illustrated as first and second charge pumps (CP1, CP2) 204, 206); one or more capacitors (illustrated as first and second capacitors (C1, C2) 208, 210); a bias generator 212 (Bias Gen); a replica 214; and a voltage controlled oscillator (VCO) 216.

[0016] The PFD 202 compares two input frequencies (illustrated as “refclk” and “fbk” in FIG. 2) that denote, respectively, a reference signal and a feedback signal. The illustrated PFD 202 is operable to generate an output that is a measure of a phase difference of the two input frequencies, which are illustrated as “up” and “down” to represent differences in respective edges of the input signals. The differences in the relative numbers of “up” or “down” pulses output by the PFD 202 indicate whether the reference signal has a frequency that is higher or lower than the feedback frequency provided by the feedback divider 114.

[0017] The PLL 106 may also include one or more multipulse generators. The outputs of the PFD 202 are provided, for example, through respective multipulse generators 218, 220, to respective charge pumps (CP1, CP2) 204, 206 which charge respective capacitors (C1, C2) 208, 210 according to the pulses. The bias generator 212 (which may also be referred to as an “Nbias generator”) and the replica 214 (which may also be referred to as a “Pbias” generator”) may then use the charge from these capacitors (C1, C2) 208, 210 to control voltage provided to the VCO 216, and therefore control the output frequency of the VCO 216. The output of the VCO 216 is provided to the clock signal destination 110, as well as the feedback divider 114 as previously described. The clock signal destination may then provide an output to an input/output (I/O) device 116, such as a wireless interface.

[0018] The feedback divider 114, in the illustrated system 200 of FIG. 2, divides the output of the VCO 216 by a feedback divider ratio (illustrated as “fbkdivratio”), a result of which is then provided back to the PFD 202 for further comparison. For example, the feedback divider ratio may be set at 10 to 1 where the VCO 216 generates a frequency that is ten times greater than the reference signal of the reference clock source 108, i.e., “refclk” in FIG. 2. A variety of other ratios are also contemplated. Thus, the PLL 106 provides a closed-loop system that can “lock” to a difference in frequencies and compensate for this difference accordingly.

[0019] As previously described, however, the PLL 106 may be used in a variety of different applications, each of which may have a different optimal transfer function. Accordingly, the PLL 106 includes a tunable-transfer function 112 which is implemented in FIG. 2 via the multipulse generators 218, 220 (MPGs) and respective activity factors 222, 224 (AF₁, AF₂). The MPGs 218, 220 accept as an input the up and down pulses output by the PFD 202 and multiplies the pulses according to a respective activity factor 222, 224 (AF₁, AF₂) on its input. The outputs of the MPGs 218, 220 are then provided to the respective charge pumps 204, 206 to charge the respective capacitors 208, 210 as previously described to control the VCO 216.

[0020] In this way, the reference clock frequency may be increased (i.e., more edges are added in a cycle) to generate more up/down pulses, which may therefore average a correction supplied by the PLL 106 and thereby decrease feed-through jitter. Additionally, by providing a MPG 218, 220 for each respective charge pump 204, 206, bandwidth and peaking of the PLL 106 may be controlled independently. Thus, a single PLL may be provided for use in a variety of applications and accordingly conserve effort traditionally needed to design a particular PLL for each application. Yet further, the PLL may improve jitter performance of existing PLLs by tuning the respective PLLs in silicon tests, further discussion of which may be found in relation to the exemplary procedure 500 of FIG. 5.

[0021] FIG. 3 illustrates an exemplary implementation 300 of the multipulse generator 218 of FIG. 2 that is configured to provide multiple “up” pulses and may include one or more delay cells. The multipulse generator 218 includes a plurality of logic gates 302, 304, 306. Logic gate 302 accepts, as inputs, an activity factor (AF_a) 308 and an “Up” 310 signal from the PFD 202 of FIG. 2. Logic gate 304 accepts, as inputs, another activity factor (AF_b) 312 and another “Up′” 314 signal from the PFD 202 of FIG. 2 that is delayed through use of a delay cell 316. Likewise, logic gate 306 accepts, as inputs, yet another activity factor (AF_c) 318 and yet another “Up″” 320 signal from the PFD 202 of FIG. 2, this one being delayed through use of delay cell 316 and another delay cell 322. The delay cells 316, 322 may be implemented in a variety of ways, such as through use of an inverter chain.

[0022] In an implementation, each of the activity factors (i.e., AF_a 308, AF_b 312 and AF_c 318) may be set separately to arrive at a desired transfer function. For example, the activity factor of the MPG 218 in the illustrated example may be set anywhere from zero to three and may be generated using a counter that uses the reference clock as a clock. For instance, if an overall activity factor of “2.5” is desired, AF_a 308 may be set to one, AF_b 312 may be set to one, and AF_c 318 may be set to 0.5 to a result 324 of “2.5”.

[0023] FIG. 4 illustrates a timing diagram 400 that further depicts the activity factor of “2.5” being set in this way. In this implementation, the reference clock 402 signal provides the up 310 signal and is also processed by the delay cells 316, 322 of FIG. 3 to provide respective up signals, i.e., Up′ 314 and Up″ 320.

[0024] AF_a 308 is set to one, AF_b 312 is set to one, and AF_c 318 is set to 0.5. Therefore, the AF 324 of the overall MPG 218 in this instance is output as alternating groups 404-408 of three pulses and two pulses. Although the MPG 218 of FIGS. 3 and 4 has been described for “up” pulses, it should be apparent that this circuit may also be utilized for “down” pulses as well, i.e., the illustrated MPG may also implement the MPG 220 of FIG. 2 to provide the tunable-transfer function 112 of FIG. 1.

[0025] In a second order model (when ignoring capacitor C₂), the following equations may be observed for bandwidth and peaking, respectively:

[0026] ${\omega }_n=\sqrt{\frac{I_1{K}_1}{{\mathrm{NC}}_1}}$ $\zeta ={\omega }_n\frac{{\mathrm{RC}}_1}{2}\frac{I_2{K}_2}{I_1{K}_1}$
where:

[0027] K₁ is the VCO gain from nbias to VCO output frequency;

[0028] K₂ is the VCO gain from pbias to VCO output frequency;

[0029] I₁ is the CP₁ (charge pump 1) current;

[0030] I₂ is the CP₂ current;

[0031] N is the feedback divider value;

[0032] R is the replica's output resistance; and

[0033] C₁ is the capacitance of the main low-pass filter (LPF) capacitor.

[0034] When multiplying the up & down pulses, I₁ and I₂ currents are effectively changed as follows:
I_1eff=I₁·AF₁
I_2eff=i₂·AF₂
Substituting this into the second order equation the following is observed:

[0035] ${\omega }_{n,\mathrm{eff}}={\omega }_n\sqrt{{\mathrm{AF}}_1}$ ${\zeta }_{\mathrm{eff}}=\zeta \frac{{\mathrm{AF}}_2}{\sqrt{{\mathrm{AF}}_1}}$
It should be noted that “ω_n” is correlated with the PLL and that “ζ_eff” is correlated with the peaking. From the equations above, it is apparent that the bandwidth and peaking may be controlled independently.

[0036] Exemplary Procedures

[0037] The following discussion describes phase-locked loop tuning techniques that may be implemented utilizing the previously described systems and devices. The procedures are shown as a set of blocks that specify operations performed by one or more devices and are not necessarily limited to the orders shown for performing the operations by the respective blocks.

[0038] FIG. 5 depicts a procedure 500 in an exemplary implementation in which a phase-locked loop is formed and tuned. An integrated circuit is formed that is configured to implement a phase-locked loop having a transfer function (block 502). For example, a variety of semiconductor processes may be utilized to form the PLL 106 on a “chip”.

[0039] Once formed, the transfer function of the phase-locked loop is tuned (block 504). Continuing with the previous example, the PLL 106 may include a tunable-transfer function 112 implemented via a plurality of multipulse generators 218, 220. Activity factors 222, 224 provided as inputs to the respective multipulse generators 218, 220 may then be adjusted (block 506) to “tune” the transfer function. A variety of other examples are also contemplated.

[0040] Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claimed invention.