Phase locked loop based on a charge pump

[0002] The present invention relates to a method for balancing the output current of a charge pump according to the appended claim 1. Also, the invention relates to a charge pump structure according to the appended claim 5. Furthermore, the invention relates to a wireless communication device according to the appended claim 10.

[0003] Particularly in wireless communication devices, phase-locked loops (PLL) are used as oscillators in frequency synthesis, and in the generation of clock signals. Phase-locked loops are generally implemented as integrated circuits, and the charge-pump technique is used in them. Appended FIG. 1 shows a phase-locked loop according to prior art, comprising a phase detector PD, a charge pump CHP with two current sources CS1, CS2 (FIG. 2), a loop filter LF which is typically implemented as a low pass filter, and a voltage-controlled oscillator VCO. FIG. 2 shows a charge pump CHP according to prior art. The phase detector PD receives two clock signals: a reference signal and a clock signal generated by the voltage-controlled oscillator. The phase detector PD comprises two output lines: UP and DOWN, the first output line DOWN being used for controlling the charging current source CS1 of the charge pump CHP, and the second output line UP being used for controlling the discharging current source CS2. In a situation in which the frequency of the reference signal is greater than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal leads the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in the UP line, wherein a second switch SW2 in the charge pump is turned off. Thus, the charging current source CS1 is allowed to supply current to the output of the charge pump. This current i_sourcefrom the charging current source CS1 is supplied to the loop filter LF to increase the charge of a capacitor therein. This increase in the charge of the capacitor causes an increase in the voltage at the input of the voltage-controlled oscillator VCO. Consequently, the frequency of the clock signal generated by the voltage-controlled oscillator is increased. Correspondingly, in a situation where the frequency of the reference signal is smaller than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal lags the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in its first output, i.e. the output line DOWN, wherein a first switch SW1 in the charge pump is turned off. Thus, the discharging current source CS2 is allowed to drain current from the output of the charge pump, wherein the charge of the capacitor of the loop filter is discharged by the current i_sinkof this discharging current source. This reduction in the current is manifested as a reduction in the voltage at the input of the voltage-controlled oscillator. Thus, the frequency of the clock signal generated by the voltage-controlled oscillator VCO is reduced.

[0004] The above description applies to a charge pump structure in which the switches SW1, SW2 are normally closed. It is also possible for the switches SW1, SW2 to be in a normally open condition. In that case the operation of the switches SW1, SW2 is slightly different. The UP line being used for controlling switch SW1 and the DOWN line being used for controlling switch SW2. In a situation in which the frequency of the reference signal is greater than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal leads the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in the UP line, wherein a first switch SW1 in the charge pump is turned on and the second switch SW2 remains open. Correspondingly, in a situation where the frequency of the reference signal is smaller than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal lags the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in its first output, i.e. the output line DOWN, wherein a second switch SW2 in the charge pump is turned on and the first switch SW1 remains open.

[0005] It is also possible to operate the voltage-controlled oscillator VCO to operate in the opposite way—i.e. a decrease in voltage produces an increase in frequency and vice versa.

[0006] In a situation in which the reference signal and the signal generated by the voltage-controlled oscillator have the same frequency and the same phase, i.e. the phase-locked loop is in locked condition, there is no pulse in the phase detector outputs UP and DOWN. Thus, the current sources CS1, CS2 of the charge pump are either switched off or both current sources CS1, CS2 of the charge pump are connected to the output of the charge pump. Ideally charging current i_sourceand discharging current i_sinkare designed to be the same. In an ideal situation, there should thus be no current in the output of the charge pump, and the charge of the capacitor of the loop filter should remain constant and also the frequency of the clock signal generated by the voltage-controlled oscillator VCO should remain substantially constant. In practical applications, however, the structures of the current sources CS1, CS2 of the charge pump cannot be made fully identical, e.g. for the reason that the charging current source CS1 is implemented by using a transistor of the P type or a P channel transistor, and the discharging current source CS2 is implemented with a transistor of the N type or an N channel transistor, which cannot be made identical in practice. This results in a current mismatch of typically in the order of 5 to 20% in the currents i_source, i_sinkof the current sources. As an example of such a known phase-locked loop, the integrated circuit LMX2335 by National Semiconductor company can be mentioned, in which the structures of the current sources are aimed at being made as identical as possible. However, also in this circuit, the current mismatch is of the order presented above.

[0007] In a situation where the phase-locked loop is in the locked condition and both current sources CS1, CS2 are connected to the output of the charge pump CHP, the current mismatch leads to the capacitor of the loop filter LF being discharged or charged, depending on which current source CS1, CS2 generates a current with a greater absolute value. This results in a change in the frequency of the clock signal generated by the voltage-controlled oscillator VCO. This change causes a need for correcting the phase-locked loop PLL. Thus, the frequency generated by the phase-locked loop is not constant, but it has slight variations which are manifested as an interfering signal on the other stages of the wireless communication device.

[0008] The difference in the currents i_source, i_sinkgenerated by the current sources CS1 and CS2 is also manifested in that the frequency of the clock signal generated by the voltage-controlled oscillator VCO increases faster, if the current i_sourcesupplied by the charging current source CS1 is greater, or decreases faster, if the current i_sinkdrained by the discharging current source CS2 is greater. As a result, the length of the pulses in the outputs UP and DOWN of the phase detector are not the same. This, in turn, causes interfering frequencies in the output of the phase-locked loop PLL and other spurious signals. One possibility to reduce this interference is to reduce the bandwidth of the loop filter, but this will slow down the operation of the phase-locked loop. Particularly in the next generation mobile communication systems, which are currently under development, such as the general packet radio service (GPRS), high requirements are set for the rate of frequency synthesis in the receiving and transmitting channel, because of an increasing need for channel switching during wireless communication.

[0009] It is an aim of the present invention to provide a method for reducing the unwanted effects caused by the non-ideal properties of a charge pump, as well as a charge pump structure in which the effects caused by the non-ideal properties of the charge pump are eliminated to a major extent. The invention is based on the idea of providing a second charge pump which is identical with the first charge pump and in which deviations caused by non-ideal properties are used to compensate for the effect of non-ideal properties of the first charge pump. The method according to the present invention is characterized in what is presented in the characterizing part of the appended claim 1. The charge pump structure of the present invention is characterized in what will be presented in the characterizing part of the appended claim 5. Furthermore, a wireless communication device according to the present invention is characterized in what will be presented in the characterizing part of the appended claim 10.

[0010] The present invention gives significant advantages in comparison with the solutions of prior art. To implement two substantially identical charge pumps is considerably easier than to balance the charging and discharging current sources of a charge pump. Particularly, in connection with the manufacture of integrated circuits, it is easy to copy a charge pump by geometrical copying of the charge pump section. Thus, the properties of both charge pumps are very similar to each other. In the charge pump structure of the invention, the second charge pump is used for providing reference information to the first charge pump. This reference information, which is advantageously information about the mismatch current, is used for correcting the output current generated by the first charge pump. The charge pump structure of the invention can also be advantageously implemented with separate components, wherein the mutual balancing of the current generators (source and sink) in each charge pump is not critical. Instead, it is easier to select the corresponding components in the charge pumps to have substantially identical properties, wherein the reference information corresponds to the non-ideal properties of the first charge pump as well as possible. The frequency synthesis implemented with the charge pump structure of the invention is considerably less prone to interference and does not contain such a high proportion to spurious frequencies as occur in solutions of prior art. Moreover, the frequency formed in the frequency synthesis does not fluctuate as strongly as in frequency synthesis using a phase-locked loop of prior art.

[0011] In the following, the invention will be described in more detail with reference to the appended drawings, in which

[0012] FIG. 1 shows a phase-locked loop of prior art in a reduced block chart,

[0013] FIG. 2 shows a charge pump of prior art in a reduced block chart,

[0014] FIG. 3ashows a charge pump structure according to an advantageous embodiment of the invention, in a reduced block chart,

[0015] FIG. 3bshows a charge pump structure according to another advantageous embodiment of the invention, in a reduced block chart,

[0016] FIG. 4 shows a transmitter-receiver structure, in which the invention can be advantageously applied, and

[0017] FIGS. 5a-5cshows as timing charts on the operation of a phase comparator.

[0018] FIG. 3ashows, in a reduced block chart, a charge pump structure according to an advantageous embodiment of the invention. It comprises two charge pumps CHP1, CHP2. Further, the charge pump structure comprises means CM for copying the reference information generated by the second charge pump CHP2 to the output of the first charge pump CHP1. The first charge pump CHP1 comprises two current sources CS1, CS2 as well as two switch means SW1, SW2. The charging current source CS1 is implemented e.g. with a transistor of the P type, as already disclosed above in this specification. In a corresponding manner, the discharging current source CS2 is implemented e.g. with a transistor of the N type. The aim is to select or fabricate the components of the current charges CS1, CS2 so that the current strengths i_source1, i_sink1are substantially the same. In practice, it is possible to achieve the accuracy of a few per cent. The charging current source CS1 is coupled, at one end, e.g. to an operating voltage source V_CCand, at the other end, to the first switch means SW1. The discharging current source is coupled, at one end, advantageously to the ground potential and, at the other end, to the second switch means SW2. These switch means SW1, SW2 are controlled in the phase-locked loop application by signals generated by the phase detector PD (FIG. 4). The switch means SW1, SW2 are advantageously solid state switches or other electrically controllable switch solutions known as such. It is obvious that the switch means SW1, SW2 can also be implemented in another way, known as such, so that the current strength supplied by the respective current source CS1, CS2 in the output of the charge pump CHP1 is substantially zero.

[0019] With respect to the current sources CS1, CS2, the second charge pump CHP2 is implemented in such a way that it is as identical to the first charge pump CHP1 as possible. Thus, the charging current source of the second charge pump, which is indicated with the reference numeral CS3, is implemented in such a manner that it is as identical to the current source CS1 of the first charge pump as possible. Also, the discharging current source CS4 of the second charge pump is implemented in such a manner that it is as identical to the discharging current source CS2 of the first charge pump as possible. Thus, the current strengths supplied by the first charging current source CS1 and the second charging current source CS3 (indicated as i₁and i₃in FIG. 3a) are substantially identical. Also the current strengths drained by the first discharging current source CS2 and the second discharging current source CS4 (indicated as i₂and i₄in FIG. 3a) are substantially identical to each other.

[0020] In the following, the operation of a charge pump structure according to an advantageous embodiment of the invention will be described, with reference to FIG. 3a. It is assumed that the switch means SW1, SW2 are first closed. Thus, the current i₁supplied by the first charging current source CS1 passes through the first switch means SW1 to the output OUT1 of the first charge pump. The first discharging current source CS2 drains a current strength i₂from the output OUT1 via the second switch means SW2 to ground. Thus, the first charging current source CS1 and the first discharging current source CS2 generate a leakage current i_Δ1at the output OUT1 of the first charge pump. According to Kirchhoff's current law, the algebraic sum of currents toward any point in a network is zero. In the markings of FIG. 3a, the direction arrows of currents represent the direction of a positive current, wherein when the current strength is less than 0, the direction of the current is opposite to that indicated in the figure, which is known as such. Thus, the quantity of the leakage current i_Δ1is the difference between the current drained by the first discharging current source CS2 and the current supplied by the first charging current source CS1, and is represented by the formula:

[0021] i_Δ1=i₁−i₂  (Formula 1)

[0022] The operation of the second charge pump CHP2 is substantially identical to the operation of the first charge pump CHP1. In this advantageous embodiment of the invention the switch means SW1 and SW4 are both controlled simultaneously so that when the switch means SW1 is closed, the switch means SW4 is closed, too and vice versa. Also the switch means SW2 and SW3 are both controlled simultaneously so that when the switch means SW2 is closed, the switch means SW3 is closed, too and vice versa. In a situation where the switch means SW3, SW4 are closed, the current i₃supplied by the second charging current source CS3 passes through the switch means SW3 to the output OUT2 of the second charge pump. The second discharging current source CS4 drains a current strength i₄from the output OUT2 via the fourth switch means SW4 to ground. Consequently, the second charge pump CHP2 generates a reference current strength i_Δ2at its output OUT2. The quantity of this reference current can be calculated, according to the markings of FIG. 3a, by the formula:

[0023] i_Δ2=i₃−i₄  (Formula 2)

[0024] Now, referring to the markings of FIGS. 3aand 3b, especially to the arrows, which represent (positive) directions of the currents of the charge pump structure, the means CM for copying are arranged to generate a current i₅whose strenght is proportional by a factor k to the reference current i_Δ2and the direction is reversed. The reference current i_Δ2is conveyed to means CM for copying which generates, in its output line C, a current whose strength is proportional, preferably directly proportional, to the reference current i_Δ2supplied by the second charge pump CHP2, i.e. the amplification of the means CM for copying in this advantageous embodiment is ca. 1. This means that the factor k is approximately 1. The amplification of the means CM for copying can also be variable or tunable. This variability/tunability can be extended to other blocks of the charge pump structure. For example, the current ratio between the currents generated by the first charging current source CS1 and the second charging current source CS3 and respectively the current ratio between the currents generated by the first discharging current source CS2 and the second discharging current source CS4 can be greater than one or less than one. The means CM for copying is for example a current mirror or any current conveyor structure, any current or voltage sampler or the like. The current i₅supplied by the means CM for copying is conveyed to the output OUT1 of the first charge pump. Thus, the output current (indicated i_OUT) of the charge pump structure of FIG. 3ais the difference between the leakage current i_Δ1and the current i₅supplied by the means CM for copying. Consequently, the output current i_OUTcan be calculated using the formula:

[0025] i_OUT=i₅+i_Δ1  (Formula 3)

[0026] By replacing in the formula 3 the current supplied by the copying means i₅=−k*i_Δ2, the output current obtained is

[0027] i_OUT=i_Δ1−k*i_Δ2  (Formula 4)

[0028] By substituting formulae 1 and 2 in to formula 4, the equation obtained for the output current i_OUTis (k=1):

[0029] i_OUT=(i₁−i₂)−(i₃−i₄)=i₁−i₂−i₃+i₄  (Formula 5)

[0030] In the situation presented above, the output current i_OUTis very close to zero, due to the substantially identical nature of charge pumps CHP1, CHP2.

[0031] In a situation where the first switch means SW1 is open (i_i≈0), the output current i_OUTof the charge pump structure is influenced by the current strength i₂drained by the first discharging current source CS2 as well as by the reference current i_Δ2supplied by the second charge pump CHP2. Because in this situation also the fourth switch means SW4 is open (i₄≈0), the output current i_Δ2of the second charge pump is the current i₃supplied by the second charging means CS3. This is conveyed to the means CM for copying, wherein according to Formula 5, the output current i_OUTobtained for the charge pump structure is minus the sum of the current strength of the first discharging current source CS2 and the current strength of the second charging current source CS3, i.e. −(i₂+i₃). On the other hand, the strength of the current i₃supplied by the second charging current source CS3 is substantially equal to the strength of the current supplied by the first charging current source CS1, wherein the output current of the charge pump can be presented also in the form

[0032] i_OUT=−(i₁+i₂)  (Formula 6a)

[0033] i.e. as minus the sum of the currents drained by the first discharging current source CS2 and the first charging current source CS1.

[0034] Correspondingly, in a situation where the first switch means SW1 is closed and the second switch means SW2 is open (i₂≈0), wherein also the third switch means SW3 is open (i₃≈0) and the fourth switch means SW4 is closed, the output current i_OUTof the charge pump structure can be calculated by following the principles presented above. Thus, the output current obtained is the sum of the current strength i₁supplied by the first charging current source CS1 and the current strength i₄drained by the second discharging current source CS4. Since the strength of the current i₄drained by the second discharging current source CS4 is substantially identical to the strength of the current i₂drained by the first discharging current source CS2, the output current i_OUTof the charge pump structure in this situation can be presented as the sum of the currents i₁, i₂supplied by the current sources CS1, CS2 of the first charge pump.

[0035] i_out=i₁+i₂  (Formula 6b)

[0036] From the description above, it can be stated that in the charge pump structure according to the invention, the differences in the strengths of the currents supplied by the charging CS1, CS3 and drained by discharging current sources CS2, CS4 are not significant as such. Also the absolute directions of the currents i₁-i₄, i_Δ1, i_Δ2, i_OUTin practical implementations need not be the same as presented in the figures. They are presented as an example, only. What is relevant is that the ratio of the currents i₁, i₃supplied by the charging current sources CS1, CS3 is substantially equal to the ratio of the currents i₂, i₄drained by the discharging current sources CS2, CS4, i.e. the absolute strength of the currents in the second charge pump CHP2 could be some constant multiplied by the strength of the current in the first charge pump CHP1. As was mentioned above the ratio of the currents i₁, i₃; i₂, i₄in an advantageous embodiment is ca. 1. The factor k prefarably equals the ratio i₁/i₃(or i₂/i₄).

[0037] FIG. 3bshows, in a reduced block chart, a charge pump structure according to another advantageous embodiment of the invention. It also comprises two charge pumps CHP1, CHP2. Further, the charge pump structure comprises means CM for copying the reference information generated by the second charge pump CHP2 to the output of the first charge pump CHP1. The first charge pump CHP1 comprises two current sources CS1, CS2 as well as two switch means SW1, SW2.

[0038] The second charge pump CHP2 is implemented in such a way that it has the current sources CS3, CS4 as identical to the current sources CS1, CS2 of the first charge pump CHP1 as possible. The current i₃supplied by the second charging current source CS3 is allowed to flow continuously to the output OUT2 of the second charge pump CHP2. Also the second discharging current source CS4 is allowed to drain current i₄continuously from the output OUT2 of the second charge pump CHP2. Therefore the switch means SW3, SW4 can be replaced by wires or the like. The reference current i_Δ2generated by the second charge pump CHP2 at its output OUT2 is continuously injected by the means CM for copying into the output OUT1 of the first charge pump CHP1 to compensate the mismatch between the current i₁supplied by the first current source CS1 and the current i₂drained by the first discharging current source CS2.

[0039] Furthermore, the following is a description of the operation of the charge pump structure according to the invention in a high-frequency block of a wireless communication device such as that shown in FIG. 4, with reference to the timing charts of FIGS. 5a-5c.FIG. 4 shows only some functional features of the high-frequency block. The high-frequency block consists of a receiver block RX, a transmitter block TX, a reference oscillator LO1, as well as a phase-locked loop PLL. For practical reasons, the frequency of the reference oscillator LO1 is lower than local oscillator frequencies f_RX, f_TXrequired by the receiver block RX and the transmitter block TX. In the phase-locked loop PLL, this is taken into account e.g. so that the signal generated by the voltage-controlled oscillator VCO is conveyed to a first frequency divider DIV1 in which a desired divider value can be set with a control line TUNE. Thus, the output of the first divider DIV1 contains the frequency generated by the voltage-controlled oscillator VCO divided by the set divider value. In the embodiment of FIG. 4, the frequency of the signal generated by the reference oscillator LO1 is also divided in a second divider DIV2 before conveying it to the phase detector PD. The frequency of the reference oscillator LO1 as well as the divider values of the first divider DIV1 and the second divider DIV2 are selected so that when the voltage-controlled oscillator VCO is tuned to a desired frequency, the signals in the input lines of the phase detector PD have substantially the same frequency and the same phase. The frequency generated by the voltage-controlled oscillator VCO is used as a local oscillator frequency f_TXfor the transmitter block TX. The local oscillator frequency for the receiver block RX is generated by mixing in the mixer MIX the frequency generated by the voltage-controlled oscillator VCO and the frequency generated by the duplex oscillator LO2, which is known as such. Another alternative is that the local oscillator frequency for the transmitter block TX is generated by mixing in the mixer MIX the frequency generated by the voltage-controlled oscillator VCO and the frequency generated by the duplex oscillator LO2 and the frequency generated by the voltage-controlled oscillator VCO is used as a local oscillator frequency f_RXfor the receiver block RX. The duplex oscillator LO2 can also be omitted in some implementations.

[0040] A high frequency signal is received by the antenna and band bass filtered in the high frequency filter block HF so that the correct high frequency signals are sent to the receiver block RX. The high frequency signals are converted to intermediate frequencies or into base band frequencies and demodulated in the receiver block RX.

[0041] The signals to be transmitted are modulated and converted to high frequency signals in the transmitter block TX. The modulated, high frequency signal is low pass filtered in the high frequency filter block HF and transmitted via the antenna.

[0042] The phase detector PD comprises two outputs: UP and DOWN. The outputs UP, DOWN of the phase detector are used to control the operation of the charge pump according to the invention advantageously in the following way: When the phase-locked loop PLL is in locked condition, the outputs UP, DOWN of the phase detector PD are e.g. in the logical 0 state. In this advantageous example, this means that the switch means SW1-SW4 of the charge pumps CHP1, CHP2 are closed. As stated above in the description of the example of FIG. 3a, the current strength in the output of the charge pump structure CHP is substantially zero, wherein the charge of the capacitor of the loop filter LF is not changed significantly. This also keeps the frequency of the voltage-controlled oscillator VCO substantially unchanged. The timing chart corresponding to this situation is presented in FIG. 5a. It shows the output signal of the dividers DIV1, DIV2 for two cycles as well as the state of the outputs UP, DOWN of the phase detector PD.

[0043] In a situation in which e.g. the channel is changed, a new divider value is set in the first divider DIV1. If the channel change requires an increase in the frequency, the divider value is increased, wherein the frequency of the signal in the first input IN1 is lower than the frequency of the signal in the second input IN2. Apparently there exists a phase difference between the phase of the signal in the first input IN1 of the phase detector PD and the phase of the signal in the second input IN2. Thus, the phase detector PD generates pulses in the first output UP, until the input signals of the phase detector PD are substantially in the same frequency and phase. This situation is presented in the timing chart of FIG. 5b.These pulses make the switch means SW2 and SW3 of the charge pump CHP open for the time of the pulses. Thus, during each pulse, the output of the charge pump CHP has a current strength which causes charging of the capacitor in the loop filter, wherein the output voltage of the loop filter LF is increased. This will result in an increase in the frequency of the voltage-controlled oscillator. When the frequency of the voltage-controlled oscillator VCO corresponds to the set channel frequency, the phase-locked loop PLL is thus locked and the switch means SW1-SW4 of the charge pump CHP are closed.

[0044] In a corresponding manner, in a situation where the frequency of the voltage-controlled oscillator VCO is to be reduced, the divider value of the first divider is decreased, wherein the frequency of the signal in the first input IN1 is greater than the frequency of the signal in the second input IN2. Apparently there exists a phase difference between the phase of the signal in the first input IN1 of the phase detector PD and the phase of the signal in the second input IN2. Thus, the phase detector PD generates pulses in the second output DOWN, until the input signals of the phase detector PD are substantially in the same frequency and phase. This situation is presented in the timing chart of FIG. 5c. These pulses make the switch means SW1 and SW4 in the charge pump CHP open for the time of the pulses. Thus, during each pulse, the output of the charge pump CHP contains a current strength which causes discharging of the capacitor of the loop filter, wherein the output voltage of the loop filter LF decreases. This results in a reduction in the frequency of the voltage-controlled oscillator VCO, until the frequency of the voltage-controlled oscillator VCO corresponds to the set frequency.

[0045] The description above assumes that an increase in voltage produces an increase in frequency. As was mentioned earlier in the description, the voltage controlled oscillator may also operate in the opposite way, wherein the operation of the phase-locked loop PLL should be modified accordingly, which is known as such.

[0046] With the charge pump structure of the invention, the above-presented changes in the frequency take place at a substantially equal rate, irrespective of the direction of the change in the frequency. However, in the solutions of prior art, the charging and discharging current strengths are not equal because in practical applications the structures of the current sources CS1, CS2 of the charge pump cannot be made fully identical. This results in a current mismatch, wherein the change rate is affected also by the direction of the change.

[0047] The high-frequency block of FIG. 4 can be applied for example in wireless communication devices, base transceiver stations, satellite stations, etc.

[0048] In the charge pump structure according to the invention, the first charge pump CHP1 is in the signal path; i.e., the output signals of the phase detector PD are conveyed to the first charge pump CHP1, as in the solutions of prior art, but the second charge pump is separated from the signal path.

[0049] It is obvious that the invention can also be applied in a way that when the phase-locked loop PLL is in locked condition, the switch means SW1-SW4 of the charge pump CHP are open, which means in practice that there is substantially no current in the output of the charge pump CHP.

[0050] A simulation was conducted on a charge pump structure of the invention, using the following test values: First charge pump CHP1: charging current i₁=1.001 mA and discharging current i₂=988.8 μA; matching accuracy of charge pumps 2% which means a maximum error of 20 μA at a current of 1 mA. The simulation results indicated that in the charge pump structure of the invention, the output current was clearly less than 1 μA in a situation where all the current sources were connected.

[0051] The charge pump structure of the invention can also be applied in other connections than in phase-locked loops. The present invention is not limited only to the embodiments presented above, but it can be modified within the scope of the appended claims.