US 7,244,677 B2Grant
Method for filling recessed micro-structures with metallization in the production of a microelectronic device
Issue Date:2007-07-17
•80 Claims
•6 Drawing Sheets
Abstract
A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.
Metadata
Assignee
- Semitool. Inc.
Inventors
- Thomas L. Ritzdorf
- Lyndon W. Graham
Application Information
Application Number:US 09/018,783
Filing Date:1998-02-04
Priority Date:1998-02-04
Art Unit:2823
Classifications
IPC:
H01L21/44H01L21/4763
Patent Drawings (6 sheets)
Description
Cross-Reference to Related Applications
[0001] Not Applicable
Statement Regarding Federally Sponsored Research or Development
[0002] Not Applicable
Background of the Invention
[0003] In the production of semiconductor integrated circuits and other microelectronic articles from semiconductor wafers, it is often necessary to provide multiple metal layers on a substrate to serve as interconnect metallization which electrically connects the various devices on the integrated circuit to one another. Traditionally, aluminum has been used for such interconnects, however, it is now recognized that copper metallization may be preferable.
[0004] Modern semiconductor manufacturing processes, especially those used for advanced logic devices, make use of multiple layers of metal interconnects. As the length of metal interconnects increases and the cross-sectional area and spacing between them decreases, the RC delay caused by the interconnect wiring also increases. With the drive toward decreasing interconnect size and the increasing demands placed on the interconnects, the current aluminum interconnect technology becomes deficient. Copper interconnects can help alleviate many of the problems experienced in connection with the current aluminum technology.
[0005] In view of the limitations of aluminum interconnect technology, the industry has sought to use copper as the interconnect metallization by using a damascene and/or patterned plating electroplating process where holes, more commonly called vias, trenches and other recesses are used to produce the desired copper patterns. In the damascene process, the wafer is first provided with a metallic seed layer and barrier/adhesion layer which are disposed over a dielectric layer into which trenches are formed. The seed layer is used to conduct electrical current during a subsequent metal electroplating step. Preferably, the seed layer is a very thin layer of metal which can be applied using one of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick. The seed layer can also be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface which is convoluted by the presence of the trenches, or other device features, which are recessed into the dielectric substrate.
[0006] In single damascene processes using electroplating, a process employing two electroplating operations is generally employed. First, a copper layer is electroplated onto the seed layer in the form of a blanket layer. The blanket layer is plated to an extent which forms an overlying layer, with the goal of completely providing a copper layer that fills the trenches that are used to form the horizontal interconnect wiring in the dielectric substrate. The first blanket layer is then subject, for example, to a chemical mechanical polish step in which the portions of the layer extending above the trenches are removed, leaving only the trenches filled with copper. A further dielectric layer is then provided to cover the wafer surface and recessed vias are formed in the further dielectric layer. The recessed vias are disposed to overlie certain of the filled trenches. A further seed layer is applied and a further electroplated copper blanket layer is provided that extends over the surface of the further dielectric layer and fills the vias. Again, copper extending above the level of the vias is removed using, for example, chemical mechanical polishing techniques. The vias thus provide a vertical connection between the original horizontal interconnect layer and a subsequently applied horizontal interconnect layer. Electrochemical deposition of copper films has thus become an important process step in the manufacturing of high-performance microelectronic products.
[0007] Alternatively, the trenches and vias may be etched in the dielectric at the same time in what is commonly called a “dual damascene” process. These features are then processed, as above, with barrier layer, seed layer and fill/blanket layer which fills the trenches and vias disposed at the bottoms of the trenches at the same time. The excess material is then polished, as above, to produce inlaid conductors.
[0008] The electrical properties of the copper metallization are important to the performance of the associated microelectronic device. Such devices may fail if the copper metallization exhibits excessive electromigration that ultimately results in an open circuit condition in one or more of the metallization structures. One factor that has a very large influence on the electromigration resistance of sub-micron metal lines is the grain size of the deposited metal. This is because grain boundary migration occurs with a much lower activation energy than trans-granular migration.
[0009] To achieve the desired electrical characteristics for the copper metallization, the grain structure of each deposited blanket layer is altered through an annealing process. This annealing process is traditionally thought to require the performance of a separate processing step at which the semiconductor wafer is subject to an elevated temperature of about 400 degrees Celsius.
[0010] The present inventors have recognized substantial improvements over the foregoing processes employing the elevated temperature annealing. To this end, the present inventors have disclosed herein a process for filling vias, trenches, and the like using an electrochemical metal deposition process that does not require a subsequent elevated temperature annealing step or, in the alternative, that uses a subsequent elevated temperature annealing process that takes place at temperatures that are traditionally used in the copper metallization process and are compatible with low temperature semiconductor processing.
Brief Summary of the Invention
[0011] A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a layer is deposited into the micro-structures with a process, such as an electroplating process, that generates grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature.
[0012] One embodiment of the method comprises providing a semiconductor wafer with a feature that is to be connected with copper metallization. At least one dielectric layer is applied over a surface of the semiconductor wafer including the feature. Recessed micro-structures are then provided in the at least one dielectric layer. A surface of the wafer, including the recessed micro-structures, is provided with barrier/adhesion layer and a seed layer for subsequent electrochemical copper deposition. Copper metallization is electrochemically deposited on the surface of the wafer to substantially fill the recessed micro-structures. The present inventors have found that such an electrochemically deposited layer may be annealed at temperatures that are substantially lower than the temperatures typically thought necessary for such annealing. Various methods are set forth that take advantage of this finding.
[0013] In a further embodiment of the disclosed method, the electrochemically deposited copper layer is allowed to self-anneal at ambient room temperature for a predetermined period of time before removing copper metallization from the surface of the wafer that extends beyond the recessed features.
[0014] In accordance with a still further embodiment of the disclosed method, subsequent wafer processing, including removal of selected areas of the copper metallization, takes place without an intermediate elevated temperature annealing step and may, for example, take place before self-annealing is allowed to occur.
[0015] In accordance with a still further embodiment of the method, the electrochemically deposited copper is subject to an elevated temperature annealing process. However, that annealing process takes place at a temperature below about 100 degrees Celsius or at a temperature below which an applied low-K dielectric layer suffers degradation in its mechanical and electrical properties
Brief Description of the Several Views of the Drawings
[0016] FIG. 1 illustrates one embodiment of a plating apparatus that may be used to apply an electrochemically deposited copper metallization layer to the surface of a semiconductor wafer in accordance with the disclosed methods.
[0017] FIGS. 2A-2G illustrate the various steps used in one embodiment of the disclosed method.
[0018] FIG. 3 is a graph showing the sheet resistance of an electrochemically deposited layer that has been deposited in accordance with the disclosed method as a function of time.
[0019] FIGS. 4 and 5 are graphs of various x-ray scanning parameters associated with an electrochemically deposited layer that has been deposited in accordance with the disclosed method.
Detailed Description of the Invention
[0020] FIG. 1 shows various components of a processing station 10 suitable for electroplating a metal, such as copper, onto a semiconductor wafer in accordance with the disclosed method. The two principal parts of processing station 10 are a processing head, shown generally at 15, and an electroplating bowl assembly 20. It will be recognized, however, that a wide variety of processing station configurations may be used to implement the disclosed method and that the specific construction of the station 10 is merely exemplary. To this end, such a processing station may merely comprise an anode, one or more wafer contacts to render the wafer a cathode, a plating chamber having a plating bath that contacts both the wafer and the anode, and a source of plating power. Various configurations of these elements may be employed.
[0021] As shown in FIG. 1 , the electroplating bowl assembly 20 includes a cup assembly 25 which is disposed within a reservoir container 30. Cup assembly 25 includes a fluid cup portion 35 holding the chemistry for the electroplating process. The cup assembly of the illustrated embodiment also has a depending skirt 40 which extends below the cup bottom 45 and may have flutes open therethrough for fluid communication and release of any gas that might collect as the chamber of the reservoir assembly below fills with liquid. The cup is preferably made from polypropylene or other suitable material.
[0022] A lower opening in the bottom wall of the cup assembly 25 is connected to a polypropylene riser tube 50 which, for example, is adjustable in height relative thereto by a threaded connection. A first end of the riser tube 50 is secured to the rear portion of an anode shield 55 which supports anode 60. A fluid inlet line 165 is disposed within the riser tube 50. Both the riser tube 50 and the fluid inlet line are secured with the processing bowl assembly 20 by a fitting 70. The fitting 70 can accommodate height adjustment of both the riser tube and line 65. As such, the connection between the fitting 70 and the riser tube 50 facilitates vertical adjustment of the anode position. The inlet line 65 is preferably made from a conductive material, such as titanium, and is used to conduct electrical current to the anode 60, as well as supply fluid to the cup.
[0023] Process fluid is provided to the cup through fluid inlet line 65 and proceeds therefrom through fluid inlet openings 75. Plating fluid then fills the chamber 35 through openings 75 as supplied by a plating fluid pump (not shown) or other suitable supply.
[0024] The upper edge of the cup sidewall 80 forms a weir which limits the level of electroplating solution within the cup. This level is chosen so that only the bottom surface of wafer W is contacted by the electroplating solution. Excess solution pours over this top edge surface into an overflow chamber 85.
[0025] The outflow liquid from chamber 85 is preferably returned to a suitable reservoir. The liquid can then be treated with additional plating chemicals or other constituents of the plating or other process liquid and used again.
[0026] In preferred use of the apparatus for electroplating, the anode 60 is a consumable anode used in connection with the plating of copper or other metals onto semiconductor materials. The specific anode may alternatively be an inert anode, the anode used in station 10 varying depending upon the specifics of the plating liquid and process being used.
[0027] The embodiment of the station shown in FIG. 1 also employs a diffuser plate 90 which is disposed above the anode 60 for providing a more even distribution of the flow of the fluid plating bath across the surface of wafer W. Fluid passages are provided over all or a portion of the diffuser plate 90 to allow fluid communication therethrough. The height of the diffuser plate within the cup assembly may be adjustable using height adjustment mechanisms 95.
[0028] The anode shield 55 is secured to the underside of the consumable anode 60 using anode shield fasteners 100 to prevent direct impingement by the plating solution as the solution passes into the processing chamber 35. The anode shield 55 and anode shield fasteners 100 are preferably made from a dielectric material, such as polyvinylidene fluoride or polypropylene. The anode shield serves to electrically isolate and physically protect the backside of the anode.
[0029] The processing head 15 holds a wafer W within the processing chamber 35. In the disclosed embodiment of station 10, the head 15 is constructed to rotate the wafer W within chamber 35. To this end, the processing head 15 includes a rotor assembly 150 having a plurality of wafer-engaging contact fingers 105 that hold the wafer against features of the rotor. Fingers 105 are preferably adapted to conduct current between the wafer and a plating electrical power supply and may be constructed in accordance with various configurations.
[0030] The processing head 15 is supported by an head operator 115. Head operator 115 includes an upper portion 120 which is adjustable in elevation to allow height adjustment of the processing head. Head operator 115 also has a head connection shaft 125 which is operable to pivot about a horizontal pivot axis 130. Pivotal action of the processing head using operator 115 allows the processing head to be placed in an open or face-up position (not shown) for loading and unloading wafer W. FIG. 1 illustrates the processing head pivoted into a face-down position in preparation for processing. It will be recognized that such flipping of the wafer is not necessary to the performance of the disclosed methods.
[0031] FIGS. 2A-2G illustrate one method of filling a trench and via formed on the surface of a semiconductor wafer wherein the electrochemically deposited copper layer may be applied using the apparatus described in connection with FIG. 1. FIG. 2A illustrates a base 400 having an area 405 which is to be connected by copper metallization. In FIG. 2B a layer 410 of dielectric material, such as silicon dioxide or a low-K dielectric material, is deposited over the base 400 including over area 405. Through a photoresist process and reactive ion etch or the like, selective portions of layer 410 are removed to form, for example, a trench 415 and via 420 into which copper metallization is to be deposited. The end structure is shown in the perspective view of FIG. 2C wherein the via 420 overlies connection area 405 and trench 415 overlies via 420. Connection area 405 may be, for example, a metallization feature above the substrate.
[0032] As shown in FIG. 2D , a barrier layer 423 and seed layer 425 may be disposed on the surface of dielectric layer 410. The barrier layer may be, for example, tantalum or titanium nitride. The barrier layer 423 is typically used when the structure 405 is susceptible to contamination from copper or the seed layer metal, and/or when the seed layer metal or copper may readily migrate through the dielectric layer 410 and contaminate other portions of the microelectronic circuit. As such, barrier layer 423 should be sufficiently thick along the contour of the trenches and vias to act as a diffusion barrier. Layer 423 may also function as an adhesion layer to facilitate binding between the seed layer 425 and the dielectric 410. If, however, the structure 405 is not susceptible to such contamination, there is sufficient adhesion, and the dielectric layer 410 itself acts as a barrier layer, then a separate barrier layer 423 may not be necessary. The seed layer 425 may, for example, be a copper layer or other conductive metal layer and is preferably at least 200 Angstroms thick at its thinnest point. Sidewalls 430 of the trench 415 and via 420 as well as the bottom of via 420 should be covered by the seed layer 425 and barrier layer 423 to facilitate a subsequent electrochemical copper deposition step. The seed layer 425 may be deposited through, for example, a CVD or PVD process.
[0033] The semiconductor wafer with the seed layer 425 is subject to a subsequent electrochemical copper deposition process. The electrochemical copper deposition process is executed so as to form numerous nucleation sites for the copper deposition to thereby form grain sizes that are substantially smaller than the characteristic dimensions of the via 420 and trench 415. An exemplary structure having such characteristics is illustrated in FIG. 2E wherein layer 440 is a layer of copper metallization that has been deposited using an electrochemical deposition process.
[0034] As shown in FIG. 2E , the copper metallization 440 formed in the electrochemical deposition process is deposited over the seed layer 425 and extends a distance above the surface of dielectric layer 410. Since the only features that are to contain the metallization are the via 420 and trench 415, excess copper above the dielectric layer 410 must be removed. Removal of the excess copper above the upper surface of the dielectric layer 410 may be executed using a chemical mechanical polish technique. An exemplary structure in which such removal has taken place is illustrated in FIG. 2F. After such removal, a capping barrier layer 445 may be disposed, for example, over the entire surface of the wafer, or the processes set forth in FIGS. 2A-2F may be repeated without a capping barrier layer 445 whereby the trench 415, now filled with copper metallization, corresponds to the structure 405 that further copper metallization is to contact.
[0035] A comparison between FIGS. 2E and 2F reveals that an increase in the grain size of the copper layer 440 has taken place. Traditionally, the change in the grain size has been forced through an annealing process. In such an annealing process, the wafer is subject to an elevated temperature that is substantially above the ambient temperature conditions normally found in a clean room. For example, such annealing usually takes place in a furnace having a temperature generally around or slightly below 400 degrees Celsius, or about half of the melting temperature of the electrodeposited copper. Annealing steps are normally performed at a temperature of at least 25 percent of the melting point temperature of the material as measured on an absolute temperature scale. As such, a separate annealing step is performed on the wafer using a separate piece of capital equipment. Such an annealing step is usually performed for each layer of metallization that is deposited on the wafer. These additional steps increase the cost of manufacturing devices from the wafer and, further, provide yet another step in which the wafer may be mishandled, contaminated, or otherwise damaged.
[0036] Absent such an annealing step, the traditional view is that the substantial number of grains per given volume in such sub-micron structures significantly decreases the electromigration resistance of the metal lines that are produced and gives the material a higher resistivity. This is due to the fact that grain boundary migration occurs with a much lower activation energy than trans-granular migration. As such, conventional wisdom dictates that a separate annealing step is required.
[0037] The present inventors have found that such a separate annealing step in which the electrochemically deposited copper is subject to a subsequent high temperature annealing process (e.g., at about 400 degrees Celsius) is not, in fact, necessary. Rather, electrochemically deposited copper metallization having grain sizes substantially smaller than the sub-micron structures that they fill may be subject to an annealing process in which the annealing of the copper metallization takes place at, for example, room temperature or at temperatures substantially below 400 degrees Celsius where the annealing process is more easily controlled and throughput is increased.
[0038] In accordance with one embodiment of the disclosed method, the electrochemical deposition of the copper layer 440 takes place in the apparatus set forth in FIG. 1. The processing chamber 110 is configured so that the top of the diffuser 90 is approximately between 0.5 cm-5 cm (preferably 2.0 cm) from the top of the cup 25. The distance between the top of the diffuser 90 and the top of the anode 60 is between 0.5 cm-10 cm (preferably 1.6 cm) but always greater than the diffuser to cup distance.
[0039] The electrochemical plating solution may be Enthone-OMI Cu Bath M Make-up Solution having 67 g/l of CuSO4, 170 g/l of H2SO4, and 70 ppm of HCl. The additive solutions utilized may be Enthone-OMI Cu Bath M-D (6.4 ml/l—make-up) and Enthone-OMI Cu Bath M LO 70/30 Special (1.6 ml/l make—up). The flow rate through the cup 25 of this solution may be approximately 1.0-10 GPM (preferably 5.5 GPM) and the plating temperature may be between about 10-40 degrees Celsius (preferably 25 degrees Celsius). The plating bath could alternatively contain any of a number of additives from manufacturers such as Shipley (Electroposit 1100), Lea Ronal (Copper Gleam PPR), or polyethylene glycol (PEG). An alkaline plating bath suitable for electroplating microelectronic components is set forth in co-pending provisional patent application U.S.S.N. 60/085,675, filed May 15, 1998 and entitled “Process and Plating Solution For Electroplating a Copper Metallization Layer Onto a Workpiece” which is hereby incorporated by reference.
[0040] The electrochemical process of the disclosed embodiment may be used to electroplate a copper metallization layer onto the wafer at a thickness sufficient to at least fill the trenches and/or vias. Generally stated, the embodiment disclosed herein may be divided into five sub-processes. A dwell (pre-plate) sub-process takes place when the wafer is first introduced to the electroplating bath. At that time, no plating current is provided. Rather, the surface of the wafer that is to be plated is exposed to the plating bath for a predetermined period of time without plating power, such as for five seconds.
[0041] After the dwell cycle, a low current initiation sub-process may ensue. During the low current initiation sub-process, a low plating current is provided between the anode and the wafer. In accordance with the disclosed embodiment, a direct current with a current density of approximately 3.2 mA/cm2 is utilized. The low current process may proceed, for example, for a predetermined period of time such as 30 seconds.
[0042] After the low current initiation sub-process is completed, a high current plating sub-process is initiated. It is during this sub-process that a majority of the copper is plated onto the wafer. During this step, a high plating current is provided for the electroplating operations. The plating waveform may be a constant voltage or current, a forward-only pulsed voltage or current, or a forward and reverse voltage or current. In accordance with the disclosed embodiment, and average cathode current density of approximately 20 mA/cm2 is used with a current waveform that is direct current, forward pulsed, or reverse pulsed. Preferably a direct current or forward only pulsed current is utilized with a frequency between 1 and 1000 Hz. More preferably, the frequency is between 5 and 20 Hz, with a duty cycle between 50 percent and 95 percent. More preferably, the duty cycle is between 65 percent and 85 percent. The time duration of the high current plating sub-process is dependent on the nominal thickness of the copper metallization layer that is to be applied to the wafer. For a copper metallization layer having a nominal thickness of 1.5 microns, the high current sub-process proceeds for approximately three minutes and 40 seconds. During both the low current initiation and high current plating sub-processes, the wafer is preferably spun on the rotor at a rate of between about 1-100 rpm (preferably 20 rpm).
[0043] Once the desired amount of copper has been plated onto the wafer, the wafer is lifted from contact with the plating solution. This process takes approximately two seconds, after which the wafer is spun on the rotor to remove the plating solution. For example, the wafer may be spun at 200-2000 rpm (preferably 500 rpm) for a time period of five seconds to remove the majority of the electroplating solution from the surface of the wafer. Subsequent rinsing and drying steps may be executed on the wafer in, for example, other processing chambers dedicated to such functions.
[0044] The foregoing process generates nucleation sites, grain growth mechanisms, and copper grain sizes that are sufficiently small so as to fill trenches and vias with widths as low or less than 0.3 micron and aspect ratios greater than 4-to-1. Initial grain size may be varied depending upon the plating waveform used and/or the additives used in the plating solution. Despite the small copper grain size that results from these processes, the resulting copper metallization layer may be annealed at substantially lower temperatures than traditionally suggested to form substantially larger copper grains thereby providing the copper with enhanced electrical characteristics when compared to copper deposition processes that do not promote self-annealing.
[0045] FIGS. 3-5 are derived from experimental data obtained by the present inventors on two different wafers showing that copper metallization deposited in a process in which the initial grain size of the copper crystals is sufficiently small so as to fill sub-micron dimension trenches and vias undergoes a self-annealing process at room temperature. FIG. 3 is a graph of the sheet resistance, Rs, over time of a 1.5 micron copper film deposited in the manner stated above. As illustrated, the sheet resistance begins to decrease approximately eight hours after the copper metallization has been electrochemically deposited on the wafer. After about 20 hours, a substantial decrease in the sheet resistance takes place until, ultimately, the sheet resistance is stabilized at a time between 40 and 80 hours after the deposition. Such measurements were made using a 4-point probe such as a Prometrix RS30.
[0046] FIGS. 4 and 5 relate to x-ray diffraction scanning of the electrochemically deposited copper layer. With respect to FIG. 4 , the area under each curve is proportional to the volume of the copper film with crystals having their [111] crystal plane directions perpendicular to the plane of the exposed surface of the copper layer. As illustrated, line 510 represents the measurements taken immediately after the copper metallization layer was deposited onto the wafer. Line 520 represents the measurements taken hours after the metallization layer was deposited. A comparison between the curves represented by lines 510 and 520 indicates that the number of re-oriented crystals has increased over time.
[0047] In the Rocking Curves of FIG. 5 , line 530 represents the Rocking Curve of the copper metallization layer immediately after it has been deposited on the wafer, while line 540 represents the Rocking Curve of the copper metallization layer hours after it has been deposited. The width of the curve designated by line 530 at half its height, when compared to that of the curve designated by line 540, indicates that the copper crystals are becoming more aligned and that the grain sizes of the copper crystals have increased.
[0048] Pursuant to the foregoing findings, one embodiment of the present method requires that the copper metallization be allowed to self-anneal for a predetermined period of time prior to chemical mechanical planarization thereof. At room temperatures, this predetermined period of time may range, for example, between 20 and 80 hours. In accordance with a further embodiment of the method, chemical mechanical planarization may take place before the self-annealing is completed (e.g., before the end of the predetermined period) and, further, may enhance the self-annealing process by imparting activation energy to the metallization layer during the process.
[0049] In accordance with a still further embodiment of the method, the copper metallization layer may be annealed before or after chemical mechanical polishing at an elevated temperature which is substantially below the temperature used in the annealing processes that have been traditionally employed. To this end, the wafer having the metallization layer may be placed in an oven having a temperature that is substantially below the 400 degrees Celsius traditionally thought to be necessary to promote the annealing process of copper having such small grain sizes. At a low temperature of about 60 degrees Celsius, the annealing process may be completed in about 15 minutes. At temperatures above 100 degrees Celsius, the annealing times become so short (<1 minute) so as to make annealing at higher temperatures unwarranted and wasteful.
[0050] Each of the disclosed embodiments of the method is particularly suitable for providing a copper metallization layer in combination with a low-K dielectric material. Many low-K dielectric materials become unstable if subject to temperatures greater than about 250-300 degrees Celsius. As such, annealing at the traditional temperatures close to about 400 degrees Celsius may destroy these dielectrics. Since the method of the present invention suggests the annealing of the copper metallization layer at temperatures substantially below 400 degrees Celsius (even ambient room temperatures typically found in clean room environments), the method is particularly suitable for use in manufacturing semiconductor devices using both copper metallization and low-K dielectric materials. With respect to the first and second embodiments of the method noted above, the wafer is not subject to any elevated temperature process to anneal the copper layer. With respect to the third embodiment discussed above, the copper metallization may be annealed at an elevated temperature that is high enough to substantially accelerate the self-annealing process while being low enough so as not to corrupt the low-K dielectric material. Low-K dielectric materials suitable for use with such copper metallization layers include, but are not limited to, fluorinated silicon dioxide, polyimides, fluorinated polyimides, siloxanes, parylenes, Teflon AF, nanofoams, aerogels, xerogels. Such low-K dielectrics include commercially available organic polymer dielectrics such as: Avatrel (B.F. Goodrich); BCB and PFCB (Dow Chemical); Flare 1.0 and Flare 1.5 (Allied Signal); PAE2 (Schumacher); and PQ100 and PQ600 (Hitachi). In such instances, the annealing process may also be combined with the baking process required for the low-K dielectric.
[0051] The process illustrated in FIGS. 2A-2G indicate that the via 420 and trench 415 are formed together. However, it will be recognized that the structures may be generally formed and filled separately in accordance with the single-damascene process described above. In such instances, the via 420 is first plated in accordance with the steps set forth in FIGS. 2A-2F while the trench 415 is subsequently plated in accordance with the steps set forth in FIGS. 2A-2F after plating of the via 420 has been completed. In effect, the via 420 corresponds to the structure 405 during plating of the trench 415. The methods disclosed herein are suitable for both the single-damascene and dual-damascene processes described herein.
[0052] It is also possible to plate micro recessed structures other than those set forth above and employ the foregoing low temperature annealing processes. For example, recessed structures forming a pattern in a photoresist layer may be plated pursuant to other processes used to form copper micro-metallization layers and structures. In such processes, the seed/barrier layer is preferably only provided at the bottoms of the micro-structures and does not cover the photoresist sidewalls. After the plating of the recessed micro-structures, the copper is subject to annealing at room temperature or at an elevated temperature below about 100, substantially below the 400 degrees typically employed.
[0053] Numerous modifications may be made to the foregoing system without departing from the basic teachings thereof. Although the present invention has been described in substantial detail with reference to one or more specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the scope and spirit of the invention as set forth in the appended claims.
Claims
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What is claimed is:
1. A method for filling recessed microstructures at a surface of a semiconductor workpiece having a barrier layer with a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:
depositing copper into contact with the seed layer to form continuous copper in the recessed micro-structures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and
subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature above an ambient temperature and below about 100 degrees Celsius for a time period that is sufficient to increase the grain size of the deposited copper.
2. A method as claimed in claim 1 wherein an electroplating waveform is used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.
3. A method as claimed in claim 1 wherein an electroplating solution additive is used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.
4. A method for filling recessed microstructures at a surface of a semiconductor workpiece having a barrier layer with a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:
depositing copper into contactwith the seed layer to form ocntinuous copper in the recessed microstructures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and
subjecting the surface of the semiconductor workpiece and the deposited copper to an elevated temperature annealing process at a temperature above an ambient temperature and at or below about 250 degrees Celsius for a time period of no longer than 15 minutes, which time period is sufficient to increase the grain size of the deposited copper.
5. A method as claimed in claim 4 wherein an electroplating waveform is used, at least in part, to ensure the sufficiently small metal grain size.
6. A method as claimed in claim 4 wherein an electroplating solution additive is used, at least in part, to ensure the sufficiently small metal grain size.
7. A method for filling recessed microstructures at a surface of a semiconductor workpiece, the workpiece including at least one low-K dielectric layer, a barrier layer on the dielectric layer and a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:
depositing copper into contact with the seed layer to form continuous copper in the recessed micro-structures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and
subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature selected to be above an ambient temperture and below a predetermined temperature at which the low-K dielectric layer would suffer substantial degradation.
8. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:
providing a semiconductor workpiece with a feature that is to be connected with copper metallization;
applying at least one low-K dielectric layer over a surface of the semiconductor workpiece including the feature;
providing recessed microstructures in the at least one dielectric layer;
preparing a surface of the workpiece including the recessed microstructures with a barrier layer and a non-alloyed continuous copper seed layer for subsequent electrochemical copper deposition;
electrochemically plating a copper layer onto the seed layer to form continuous copper in the recessed microstructures with copper grains that are sufficiently small to substantially fill the recessed microstructures;
annealing the electrochemically deposited copper for a predetermined period of time at an elevated temperature selected to be above an ambient temperature and below a predetermined temperature at which the low-K dielectric layer would substantially degrade; and
removing copper metallization from the surface of the workpiece except from the recessed microstructures, after the annealing of the copper.
9. A method as claimed in claim 8 wherein the step of preparing a surface of the workpiece comprises:
applying at least one barrier layer over the dielectric layer; and applying a metal seed layer over the barrier layer.
10. A method as claimed in claim 9 wherein the step of applying the seed layer is defined by applying the seed layer using a chemical vapor deposition process.
11. A method as claimed in claim 9 wherein the step of applying the seed layer is defined by applying the seed layer using a physical vapor deposition process.
12. A method as claimed in claim 8 wherein the step of preparing a surface of the workpiece comprises:
applying at least one adhesion layer over the dielectric layer; and
applying a metal seed layer over the adhesion layer.
13. A method as claimed in claim 8 wherein the step of removing the copper metallization is defined by removing the copper metallization using a chemical mechanical polish technique.
14. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:
providing a semiconductor workpiece with a feature that is to be connected with copper metallization;
applying at least one dielectric layer over a surface of the semiconductor workpiece including the feature;
providing recessed microstructures in the at least one dielectric layer;
preparing a surface of the workpiece, including the recessed microstructures, with a barrier layer and a continuous non-alloyed copper seed layer for subsequent electrolytic copper deposition;
electrolytically depositing copper onto the continuous copper seed layer to form continuous copper within the microstructures with copper grains that are sufficiently small to substantially fill the recessed microstructures; and
subjecting the electrolytically deposited copper layer to an annealing process at a temperature above an ambient temperature and at or below about 250 to 300 degrees Celsius to increase the copper grain size.
15. A method as claimed in claim 14 wherein the step of preparing a surface of the workpiece comprises:
applying at least one adhesion layer over the dielectric layer; and
applying a seed layer over the adhesion layer.
16. A method as claimed in claim 14 wherein the step of preparing a surface of the workpiece comprises:
applying at least one barrier layer over the dielectric layer; and
applying a seed layer over the barrier layer.
17. A method as claimed in claim 16 wherein the step of applying the seed layer is defined by applying the seed layer using a chemical vapor deposition process.
18. A method as claimed in claim 16 wherein the step of applying the seed layer is defined by applying the seed layer using a physical vapor deposition process.
19. A method as claimed in claim 14 wherein the step of removing the copper metallization is defined by removing the copper metallization using a chemical mechanical polish technique.
20. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:
providing a semiconductor workpiece with a feature that is to be connected with copper metallization;
applying at least one low-K dielectric layer over a surface of the semiconductor workpiece including the feature;
providing recessed microstructures in the at least one low-K dielectric layer;
preparing a surface of the workpiece, including the recessed microstructures, with a barrier layer and a continuous non-alloyed copper seed layer on the barrier layer for subsequent electrolytic copper deposition;
electrolytically depositing copper onto the seed layer to form continuous copper in the recessed microstructures using an electrolytic plating process that. generates copper grains having a size sufficiently small to substantially fill the recessed microstructures; and
subjecting the electrolytically deposited copper layer to an annealing process at a temperature above an ambient temperature and below which the low-K dielectric layer substantially degrades.
21. A method as claimed in claim 20 wherein the annealing step takes place at a temperature corresponding to a baking temperature of the low-K dielectric.
22. The method of claim 20 wherein the temperature of the elevated temperature annealing process is between about 60 degrees Celsius and about 100 degrees Celsius.
23. The method of claim 20 wherein the surface of the semiconductor workpiece is subjected to the elevated temperature annealing process for no longer than 15 minutes.
24. The method of claim 20 wherein the surface of the semiconductor workpiece is subjected to the elevated temperature annealing process for less than one minute.
25. The method of claim 20 wherein the predetermined temperature is at or below about 300 degrees Celsius.
26. The method of claim 20 wherein the predetermined temperature is at or below about 250 degrees Celsius.
27. The method of claim 20 wherein the predetermined temperature is at or below about 100 degrees Celsius.
28. The method of claim 20 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time.
29. The method of claim 20 wherein the surface of the workpiece is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.
32. The method of claim 31 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.
33. The method of claim 31 wherein the workpiece is spun while electroplating power is applied.
34. The method of claim 20 wherein the copper is deposited via electroplating for a period of time sufficient to deposit excess copper which extends above the surface of the workpiece.
35. The method of claim 34 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing.
36. The method of claim 35 wherein the excess copper is removed via chemical mechanical polishing.
37. A method of processing a semiconductor workpiece having a surface including a sub-micron recessed microstructure, comprising:
forming a continuous non-alloyed copper seed layer over a barrier layer in the recessed microstructure;
thereafter, electroplating copper to form continuous copper within the recessed microstructure and to deposit excess copper which extends above the surface of the workpiece;
thereafter, thermally treating the electroplated copper at a temperature of about 60 degrees Celsius to about 100 degrees Celsius for no longer than 15 minutes, thereby reducing resistivity of the copper; and
thereafter, removing the excess copper.
38. The method of claim 37 wherein the excess copper is removed via chemical mechanical polishing.
39. The method of claim 37 wherein an electroplating waveform is used, at least in part, to ensure sufficiently small grain size in the electroplated copper to substantially fill the recessed microstructure.
40. The method of claim 37 wherein an electroplating solution additive is used, at least in part, to ensure sufficiently small grain size in the electroplated copper to substantially fill the recessed microstructure.
41. The method of claim 37 wherein the recessed microstructure is defined, at least in part, as a recess in a dielectric layer, the method further comprising applying a barrier over the dielectric layer before depositing the seed layer.
42. The method of claim 41 wherein the seed layer is deposited on the barrier layer using a physical vapor deposition process.
43. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, and recessed sub-micron structures formed in the dielectric layer, comprising:
forming a continuous non-alloyed copper seed layer on a barrier layer over the dielectric layer and in the recessed sub-micron structures;
contacting the seed layer with a copper-containing electroplating solution;
after a predetermined dwell time, applying electroplating power to the seed layer to electrolytically deposit copper metal from the electroplating solution onto the seed layer to fill the recessed sub-micron structures with continuous copper and to deposit excess copper metal which extends above a surface of the dielectric layer; then
reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.
44. The method of claim 43 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.
45. The method of claim 43 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.
46. The method of claim 43 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.
47. The method of claim 43 wherein the workpiece is subjected to the annealing process for less than one minute.
48. The method of claim 43 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.
49. The method of claim 43 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.
50. The method of claim 43 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time.
51. The method of claim 43 wherein the electroplating power is applied as a direct current.
52. The method of claim 43 wherein the electroplating power is applied as a forward pulsed waveform at a frequency of between 1 and 1000 Hz.
53. The method of claim 52 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.
54. The method of claim 43 wherein the workpiece is spun while electroplating power is applied.
55. The method of claim 43 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.
56. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, recessed sub-micron structures formed in the dielectric layer, and a barrier layer on the dielectric layer, comprising:
forming a continuous non-alloyed copper seed layer on the barrier layer and in the recessed sub-micron structures;
contacting the seed layer with a copper-containing electroplating solution; applying electroplating power to the seed layer a first power level for a predetermined first period of time, then applying electroplating power to the seed layer a higher second power level for a time sufficient to electrolytically fill the recessed sub-micron structures with continuous copper metal and to deposit excess copper metal which extends above a surface of the dielectric layer; then
reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.
57. The method of claim 56 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.
58. The method of claim 56 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.
59. The method of claim 56 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.
60. The method of claim 56 wherein the workpiece is subjected to the annealing process for less than one minute.
61. The method of claim 56 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.
62. The method of claim 56 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.
63. The method of claim 56 wherein the seed layer is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.
64. The method of claim 56 wherein the electroplating power is applied as a direct current.
65. The method of claim 56 wherein the electroplating power is applied at the second power level as a forward pulsed waveform at a frequency of between 1 and 1000 Hz.
66. The method of claim 65 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.
67. The method of claim 56 wherein the workpiece is spun while electroplating power is applied.
68. The method of claim 56 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.
69. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, recessed sub-micron structures formed in the dielectric layer, and a barrier layer on the dielectric layer, comprising:
forming a continuous non-alloyed copper seed layer on the barrier layer and in the recessed sub-micron structures;
contacting the seed layer with a copper-containing electroplating solution; applying electroplating power to the seed layer in a forward pulsed waveform at a frequency of between 1 and 1000 Hz to electrolytically fill the recessed sub-micron structures with continuous copper metal and to deposit excess copper metal which extends above a surface of the dielectric layer; then
reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.
70. The method of claim 69 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.
71. The method of claim 69 wherein the forward pulsed waveform has a duty cycle of 50-95 percent.
72. The method of claim 69 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.
73. The method of claim 69 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.
74. The method of claim 69 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.
75. The method of claim 69 wherein the workpiece is subjected to the annealing process for less than one minute.
76. The method of claim 69 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.
77. The method of claim 69 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.
78. The method of claim 69 wherein the seed layer is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.
79. The method of claim 69 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time, the second current comprising the forward pulsed waveform.
80. The method of claim 69 wherein the workpiece is spun while electroplating power is applied.
81. The method of claim 69 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.
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- Stoychev, D.S., and Aroyo, M.S., On the Influence of Pulse Frequency on the Hardness of Bright Copper Electrodeposits, (citation unknown but believed to be published more than one year before the date of this patent application).Applicant
- Stein. B., “A Practical Guide to Understanding, Measuring and Controlling Stress in Electroformed Metals,” presented at the AESF Electroforming Sysposium, Las Vegas, NV (Mar. 1996).Applicant
- Sanchev, J. Jr., Besser, P.R., and Field, D.P., “Microstructure of Damascene Processed Al-Cu Interconnects for Integrated Circuit Application,” presented at the fourth International Workshop on Stress Induced Phenomena in Metallizations, Tokyo, Japan (Jun. 1997).Applicant
- Sanchez, J. Jr. and Besser, P.R. “Modelling Microstructure Development in Trench-Interconnect Structures,” submitted to International Interconnect Technology Conference, Sunnyvale, CA. (Jun. 1998).Applicant
- Field D P., Sanchez, J. Jr., Besser, P.R. Dingley, D.J., “Analysis of Grain-Boundary Structure in Al-Cu Interconnects,” J. Appl. Phys., 82(5) (Sep. 1, 1997).Applicant
- Gupta. D., “Comparative Cu Diffusion Studies in Advanced Metallizations of Cu and Al-Cu Based Tir Films.” Materials Research Society Symposium Proceedings, San Francisco, Ca (Apr. 1994).Applicant
- Megaw. H.D and Stokes. A.R., “Breadths of X-Ray Diffraction Lines and Mechanical Properties of Some Cold-Worked Metals,” J. Inst. Metals, vol. LXXI. pp. 279-289 (1944).Applicant
- Thompson C.V., and Knowlton. B.D., “Designing Circuits and Processes to Optimize Performance and Reliability, Melallurgy Meets Tead,” Microelectronics and Reliability, 36. p. 1683 (1996).Applicant
- Carel. R., Thompson. C.V., Frost, H.J., Material Research Society Symposium, vol. 343, Materials Research Society (1994).Applicant
- Floro, J.A. Carel. R. and Thompson, C.V., “Energy Minimization During Epitaxial Grain Growth Strain vs. Interfacial Energy,” Material Research Society Symposium, vol. 317, Material Research Society (1994).Applicant
- Plotner M., Urbansky, N., Preusz, A. and Wenzel, C., “Control of Mechanical Stresses and their Temperature Dependence in PVD CU Films,” presented at Adv. Metalliz. & Inerconn. Syst. ULSI Applic. San Diego (1997).Applicant
- Wong Chee C., Smith, H.I., and Thompson, C.V., “Secondary Grain Growth and Graphoepitaxy in Thin Au Films on Submicrometer-Period Gratings,” Material Research Society Symposium Proc, vol. 47, Material Research Society (1985).Applicant
- Thompson, C.V., and Smith. H.I., “Secondary Grain Growth in Thin Films,” Material Research Society Symposium Pro., vol. 57, Materials Research (1987).Applicant
- Wong, C.C., Smith, H.I., and Thompson, C.V., Room Temperature Grain Growth in Thin Au Films from Grain Boundary Structure and Related Phenomena, Supplement to Transactions of Japanese Institute of Metals, 27, p. 641 91986).Applicant
- Thompson, C.V., “Observations of Grain Growth in Thin Films,” from Microstructural Science for Thin Film Metalizations in Electronics Applications, eds. J. Sanchez, D.A. Smith and N. DeLanerolle, The Minerals, Metals & Materials Society (1988).Applicant
- Frost. H.J., Thompson, C.V., and Walton, D.T., “Abnormal Grain Growth in Thin Films Due to Anisotropy of Free-Surface Energies,” Materials Science Forum, vols. 94-96, pp. 543-550, Trans Tech Publications. Switzerland (1992).Applicant
- Frost. H.J. and Thompson, C.V., “Microstructural Evolution in Thin Films,” presented at the Symposium on Computer Simulation of Microstructural Evolution, Toronto, Canada, Oct. 15 (1985).Applicant
- Frost. H.J. Thompson, C.V., and Walton, D.T., “Grain Growth Stagnation and Abnormal Grain Growth in Thin Films,” presented at TMS-AIME Fall Meeting, Indianapolis, IN (1989).Applicant
- Reed-Hall et al., “Physical Metallurgy Principles,” pp. 270, 286 and 287, 83rd Ed. (1991).Applicant
- Stoychev. D.S., and Aroyo, M.S., “On the Influence of Pulse Frequency upon the Hardness of Bright Copper Electrodeposits,” (citation unknown but believed to be published more than one year before the date of this patent application).Applicant
- Frost, H.J. and Thompson, C.V., “Modeling of Optical Thin Films,” reprint from Proccedings of Spie (International Society for Optical Engineering, San Diego, CA 1987, printed by the Society of Photo-Optical Instrumentation Engineers (1988).Applicant
- Walton. D.T., Frost, H.J. and Thompson, C.V. “Computer Simulation of Grain Growth in Thin-Film Interconnect Lines,” Mat. Res. Soc. Symp. Proc., vol. 225 (1991).Applicant