Multilevel Electronic Structures Containing Copper Layer and Copper-Semiconductor Layers

1. Field of the Invention

The invention relates to the production and use of copper-semiconductor compounds and more particularly to the use of copper in VLSI technology as interconnection metallization in silicon (Si), germanium (Ge), and Si.sub.x Ge.sub.1-x electronic devices.

2. Prior Art and Problem Solved

The metal copper (Cu) has very good electrical conductivity and as a result there is currently a wide interest in and effort toward developing Cu as interconnection metallization in future silicon (Si), germanium (Ge), and Si.sub.x Ge.sub.1-x electronic devices. However, it is known that Cu diffuses into Si, producing deep energy levels in the Si energy gap which can act as efficient recombination centers thus effecting minority-carrier lifetime. This, in turn, results in severe degradation of the electrical characteristics of such devices as metal-Si Schottky-barrier and p-n junctions. Also, it is known that Cu in Ge introduces several acceptor energy levels in the energy band gap of Ge. Such energy levels similarly can act as recombination centers or as traps giving rise to excess current which causes severe degradation of the electrical characteristics of such devices as p-n and metal-Ge Schottky-barrier junctions.

Following from the experience and belief in the art that Cu always diffuses in Si and other single crystalline semiconductor materials, a problem has existed in the art to create Cu-semiconductor interfaces in VLSI devices while avoiding degradation of current-voltage characteristics in such devices. The process and system of the present invention offer a solution to this problem as well as offering other advantageous applications.

In accordance with the present invention, it has been found that Cu may be combined with a single crystalline semiconductor to form Cu-semiconductor compounds at room temperature, and in the preferred VLSI embodiment junctions formed by the deposition of Cu on a single crystalline semiconductor substrate, e.g., Si, at room temperature, are treated, such as by maintaining them at room temperature for extended periods or accelerating the process by annealing, e.g., at 200.degree. C. for 30 min., to convert the as-deposited Cu/Si interface into a well-reacted silicide (Cu.sub.3 Si)/Si interface. In the as-deposited state, these junctions display highly nonideal current-voltage characteristics, that is, they exhibit large excess current under forward and reverse bias conditions; but, it has been found that, remarkably, simple treatment, e.g., by low-temperature annealing, results in junctions which exhibit ideal current-voltage characteristics. Characterization of these junctions using techniques such as deep-level transient spectroscopy reveals that such low-temperature annealing causes the disappearance of the deep energy levels which are believed to be acting as efficient recombination centers giving rise to large excess current under forward and reverse bias conditions. Moreover, the ideal current-voltage characteristics displayed by the comparatively low-temperature, 200.degree. C.--annealed junctions are found to remain unaffected by further annealing of the junctions at higher temperatures such as 600.degree. C. for 30 min. These findings are very significant in that they show that copper, through the vehicle of the resulting silicide interface, can be used as an "electrically" stable interconnection metallization in future VLSI devices, e.g., as a high temperature (600.degree.-800.degree. C.) stability Ohmic/Schottky contact to Si or as a Cu diffusion barrier.

Similarly, as in the case of Cu on Si, it has been found that annealing junctions formed by the deposition of Cu on Ge, at temperatures as low as 150.degree. C. to 200.degree. C., to form Cu.sub.x Ge.sub.1-x compounds results in junctions which exhibit ideal current-voltage characteristics. Also, the ideal current-voltage characteristics displayed by junctions annealed at such low temperatures are found to remain unaffected by further annealing the junctions Up to 600.degree. C. This demonstrates the feasibility of using Cu.sub.x Ge.sub.1-x as electrically stable contact and interconnection metallization in future Ge and Ge.sub.x Si.sub.1-x devices.

Additional embodiments can include a Cu layer oil a Ge layer on a Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a Si substrate, and the use of an intermediate layer of a refactory metal such as tungsten (W). The various embodiments can be applied in advantageous ways in the production of FET, CMOS, NMOS and like devices as described in detail below.

Consequently, it has been found that Cu can be readily combined with semiconductor materials and that a Cu interconnection metallization for integrated circuits can be formed by depositing a Cu film on a single crystalline semiconductor substrate held at room temperature, and treating the Cu coated substrate to form a Cu-semiconductor compound interface junction which has ideal current-voltage characteristics.

FIG. 1 is a diagrammatic cross-sectional view of a VLSI device with an upper Cu layer deposited on a Si layer in accordance with one embodiment of the present invention wherein the layer of Si is first deposited on top of a W layer which is currently used to contact p-n junctions in bipolar technology.

FIG. 2 is a view as in FIG. 1 of the device after heating to form a copper silicide (Cu.sub.3 Si) layer in keeping with the invention.

FIG. 3 is a diagrammatic cross-sectional view showing a device in accordance with an alternative embodiment of the invention wherein a layer of Si is first deposited over the entire Si substrate (or a layer of polyimide), and then a Cu layer is deposited on top of the Si layer.

FIG. 4 is a view as in FIG. 3 of the device after heating to form a copper silicide (Cu.sub.3 Si) layer in keeping with the invention.

FIG. 5 is a view as in FIG. 4 wherein the formation of copper silicide is followed by the deposition of a W layer and then a second layer of Cu on top of the W layer.

FIG. 6 is a diagrammatic cross-sectional view showing a FET device in accordance with a further embodiment of the invention using copper silicide (C.sub.3 Si) to contact source and drain regions and wherein a layer of Cu is first deposited over the entire Si substrate.

FIG. 7 is a view as in FIG. 6 of the device after heating to form a copper silicide (Cu.sub.3 Si) layer in keeping with the invention and the excess Cu Si has been chemically removed.

FIG. 8 is a diagrammatic cross-sectional view showing a device in accordance with another embodiment of the invention wherein Cu.sub.x Ge.sub.1-x is used as stable contact and interconnection metallization and a layer of Cu is first deposited over the exposed surface a a.sup.+ diffused region formed in a p-type Ge substrate and over an oxide layer.

FIG. 9 is a view as in FIG. 8 of the device after heating to form a layer of Cu.sub.x Ge.sub.1-x in keeping with the invention.

FIG. 10 is a view as in FIG. 9 of the device after the excess unreacted Cu has been removed using an excimer laser to etch only in areas where the laser light impinges on the substrate.

FIG. 11 is a diagrammatic cross-sectional view showing a Ge.sub.x Si.sub.1-x /Si junction in accordance with a further embodiment of the invention wherein a layer of Si or Ge is first deposited over the exposed surface of the Ge.sub.x Si.sub.1-x layer through a window formed in the oxide layer and then followed by the deposition of a Cu layer.

FIG. 12 is a view as in FIG. 11 of the device after heating to form a Cu.sub.x Si.sub.1-x or Cu.sub.x Ge.sub.1-x contact metallization.

FIG. 13 is a diagrammatic cross-sectional view illustrating a two level interconnecting structure, of a form considered likely to be used for multilevel interconnect metallization, containing a void-open failure in the upper line just above the connecting stud.

FIG. 14 is a view as in FIG. 13 showing components in keeping with the invention for obviating void-open failures.

FIGS. 15 through 21 show diagrammatically the steps of a selective etch process used in accordance with the invention to provide extremely high selectivity between Cu and Cu.sub.3 Ge.

FIGS. 22 through 25 diagrammatically illustrate the sequence of a self-aligned Cu.sub.3 Ge process, in accordance with the invention, to produce low resistance self-aligned Cu.sub.3 Ge for advanced bipolar, CMOS, and BiCMOS devices.

FIGS. 26 through 28 illustrate respectively a possible CMOS device with self-aligned copper germanide over gate, source, drain, and two examples of bipolar devices with self-aligned Cu.sub.3 Ge over emitter, base and collector.

FIGS. 29 through 32 diagrammatically illustrate an improved technique for fabricating a MOS structure at very low temperatures for applications in CMOS devices in accordance with the invention.

FIGS. 33 through 37 diagrammatically illustrate an improved technique for fabricating Cu.sub.3 Ge, having a work function of 4.6 eV, as a midgap gate metal to be used directly over SiO.sub.2 at very low temperatures for applications in CMOS devices in accordance with the invention.

FIGS. 38 through 40 diagrammatically illustrate an alternative technique to that shown in FIGS. 33 through 37.

FIG. 41 shows the temperature dependence of the resistivity of Cu.sub.3 Ge.

The present invention involves a system and method for forming Cu-semiconductor compounds and the advantageous application thereof to creating interconnection metallization for integrated circuits wherein a Cu film is deposited on a single crystalline semiconductor layer or substrate, e.g., of Si or Ge, held at room temperature, and the Cu-coated substrate is treated to form a Cu-semiconductor compound interface junction. The treatment may consist of merely maintaining the Cu-coated substrate at room temperature for an extended period, e.g., at least about two hours, but typically several hours and possibly for weeks, depending on the thickness of the Cu film. However, in keeping with present processes for manufacturing VLSI devices, the formation of the interface junction may be accelerated by heating the Cu-coated substrate to a temperature of at least about 150.degree. C. for at least about 20 minutes, and preferably at about 200.degree. C. for 30 min., to form a Cu-semiconductor compound interface junction.

More particularly, an example of one embodiment of the present invention will be described with reference to FIG. 1, wherein Cu is deposited on Si to form a stable interconnection metallization in VLSI devices. As shown in FIG. 1, a layer 10 of Si, typically of .about.300-500 .ANG. thickness, is first deposited on top of a layer 12 of refractory metal, e.g., tungsten (W), which is currently used to contact p-n junctions in bipolar technology. This is followed by the deposition of a layer 14 of Cu, typically of .about.3000-5000 .ANG. thickness, on top of the Si layer 10. The structure, which in the example also includes a Si oxide (SiO.sub.2) layer 16 and n.sup.+ diffused region 17 formed in a p-type Si substrate 18, is then heated to 200.degree. C. for 30 min. to form a copper silicide (Ci.sub.3 Si) layer 20 as shown in FIG. 2.

An alternative embodiment is illustrated in FIG. 3, wherein a layer 22 of Si (.about.300-500 .ANG.) is first deposited over the entire Si substrate, i.e., the SiO.sub.2 layer 16 and the exposed portions of the Si substrate 18, and then a layer 24 of Cu (.about.500-1500 .ANG.) is deposited on top of the Si layer as shown in the Figure. The structure is then heated to about 200.degree. C. for 30 min. to form copper silicide (Cu.sub.3 Si) 26 as shown in FIG. 4. This is followed by the deposition of a layer 28 of W and then a second layer 30 of Cu (.about.300-500 .ANG.) on top of the W layer as shown in FIG. 5. This structure is found to be electrically stable up to 600.degree. C. for 30 min..

As an alternative to the SiO.sub.2 for layer 16, it has been found that if an insulating layer of polyimide is used, excellent adhesion between the silicide formed and the polyimide will be achieved.

In FET devices, copper silicide (Cu.sub.3 Si) can be used to contact the gate, source, and drain regions. An example is shown in FIG. 6 wherein a layer 32 of Cu (.about.500-1500 .ANG.) is first deposited over the entire Si substrate contacting source 17a and drain 17b regions in the exposed portions of substrate 18 and gate 17c of polysilicon. The structure is then heated to 200.degree. C. for 30 min. to form copper silicide (Cu.sub.3 Si) 34 and the excess copper silicide is chemically removed, resulting in the structure shown in FIG. 7. Here, a substantial advantage over prior art is that ohmic contacts to source and drain regions can be achieved at very low temperatures, about 150.degree.-200.degree. C., as compared to levels of 600.degree. to 700.degree. C. which are currently used in existing technology.

A similar configuration may be achieved substituting Ge for Si, and, in fact, it has been found that copper germanide (Cu.sub.3 Ge) offers the lowest room temperature resistivity in a stable compound so as to be particularly suitable for use in contact and gate material. FIG. 41 shows the results of resistivity vs. temperature measurements made on copper germanide (Cu.sub.3 Ge). Cu.sub.3 Ge is formed by reacting Cu with Ge at room temperature or typically temperatures as low as 200.degree. C. and below. It may be formed both on Ce or Si substrates. For (Cu.sub.3 Ge) formed on Ge substrates the room-temperature (300 K) resistivity is found to be in the range of 5.5-7 .mu..OMEGA.-cm for a 2000 .ANG. film. At 4.2 K resistivity is 1.7 .mu..OMEGA.-cm. For films formed on Si substrates the resistivity values at 300 K and 4.2 K are, respectively, 14 and 5 .mu..OMEGA.-cm. It is believed that the approximate factor of two increase in resistivity on the Si substrate is primarily due to the incorporation of Si into the (Cu.sub.3 Ge) during annealing. This increase can be reduced by adjusting the relative thicknesses of the Cu and Ge. By comparison, the resistivity values of polycrystalline TiSi.sub.2 and CoSi.sub.2, at room temperature, are 15 and 25 .mu..OMEGA.-cm respectively. Here again it is important to note that while TiSi.sub.2 and CoSi.sub.2 are normally formed at temperatures as high as 600.degree. to 700.degree. C., the low resistivity (Cu.sub.3 Ge) is readily formed at 200.degree. C.

Returning to the substitution of Ge for Si, for example, the Ge can be first deposited followed by the deposition of the Cu. Their thicknesses are adjusted for the minimal Si incorporation during the formation of the germanide; or, the Cu.sub.3 Ge can be used as a gate metal directly on SiO.sub.2 or polysilicon. In the latter instance, the Cu.sub.3 Ge has been shown to be thermally stable on SiO.sub.2 up to 600.degree.-700.degree. C.

FIGS. 8-12 show examples of how Cu.sub.x Ge.sub.1-x can be used as stable contact and interconnection metallization in future devices. A layer 44 of Cu, as shown in FIG. 8, is first deposited to a thickness in the range of .about.2000 to 3000 .ANG. over the exposed surface of a n.sup.+ diffused region 45 formed in a p-type Ge substrate 40 and over an oxide layer 42. The structure is then heated to 200.degree. C. to form a layer 46 of Cu.sub.x Ge.sub.1-x as shown in FIG. 9. The excess unreacted Cu is then removed using a technique which utilizes excimer laser such as KrF at 248 nm or ArF at 193 nm and selected Freon gases such as CF.sub.2 Br.sub.2 as disclosed by J. H. Brannon in IBM TDB, vol. 28, No. 8, 1986. In such a process, etching takes place only in areas where the laser light is impinging on the substrate 40, allowing the use of a simple light-pattern forming system. This results in the structure shown in FIG. 10.

In the fabrication of Ge.sub.x Si.sub.1-x /Si junctions, a layer 47 of Si or Ge, as shown in FIG. 11, is first deposited to a thickness in the range of .about.75 to 500 .ANG. over the exposed surface of a Ge.sub.x Si.sub.1-x layer 49 through a window formed in the oxide layer 50, followed by a Cu layer 48 to a thickness in the range or .about.125 to 3000 .ANG.. The structure disposed on substrate 52, e.g., of Si, is then heated to 200.degree. C. to form Cu.sub.x Si.sub.1-x contact metallization 51 as shown in FIG. 12.

Again, a substantial advantage to be gained with the present invention over the prior art is that electrically stable contact metallization in Ge and Ge.sub.x Si.sub.1-x devices is formed at low temperatures.

A further application of Cu.sub.3 Ge is as electromigration resistant, low resistivity wiring and vias in multilevel interconnect and via structures. More particularly, FIG. 13 illustrates a two level interconnecting structure comprising a Ti/AlCu/Ti upper level 60, a W stud in via 61, and a Ti/AlCu/Ti lower level 62 of a form considered likely to be widely used in the future for multilevel interconnect metallization. However, void-open failures have been observed in the upper Ti/CuAl/Ti lines just above the W stud, as shown at 63 in FIG. 13, which are caused by electromigration. FIG. 14 shows an improved two-level interconnecting structure with significantly improved resistance to electromigration in accordance with the invention. In this structure, the via 61 is filled with Cu.sub.3 Ge and the upper and lower levels 60 and 62 are Cu.sub.3 Ge/Cu/Cu.sub.3 Ge tri-layers, as seen in FIG. 14. Both the Cu and Ge may be deposited using chemical vapor deposition (CVD). The thicknesses of Cu and Ge may be adjusted so that Cu.sub.3 Ge is formed following a low-temperature anneal at 200.degree. C. for 30 min. As noted above, it has been found that Cu.sub.3 Ge exhibits the lowest room temperature resistivity in a compound, and in addition, Cu.sub.3 Ge adheres very well to polyimide, SiO.sub.2 and Si.sub.3 N.sub.4. In filling the vias, CVD Ge may first be deposited, followed by deposition of CVD Cu, or, alternatively, alternate CVD layers of Ge and Cu are deposited. Then, a 30 min. anneal at 200.degree. C. is performed to produce Cu.sub.3 Ge. This arrangement provides the advantage over the prior art of a very low resistance and contact resistance structure with high resistance to electromigration. In addition, it is very simple to fabricate and avoids possible harmful effects to the Si devices.

In order to provide extremely high selectivity between Cu and Cu.sub.3 Ge, a selective etch process may be used in accordance with the invention. Referring to FIGS. 15 through 21, it will be seen that a layer of Ge 70 having a thickness in the range from about 125 to about 1000 .ANG. is selectively deposited on the exposed silicon surface, which as shown in FIG. 15 includes a SiO.sub.2 71 and an n.sup.+ diffused region 72 formed in a p-type Si substrate 73. This is followed by the deposition of a thin Si layer 74 (about 50 to 100 .ANG.) over the entire silicon wafer as shown in FIG. 16. The Si over the SiO.sub.2 is then removed using standard lithographic techniques, resulting in the structure shown in FIG. 17. A Cu layer 75 having a thickness in the range from about 125 to about 2000 .ANG. is deposited over the entire silicon wafer as shown in FIG. 18. The structure in FIG. 18 is then heated to a temperature of 200.degree. C. for 30 min. to form thin Cu.sub.3 Si (76) on top of Cu.sub.3 Ge (77) as shown in FIG. 19. The excess Cu of layer 75 is then selectively removed by etching in a 10:1 solution of HNO.sub.3 :H.sub.2 O which will not chemically attack Cu.sub.3 Si. This results in the structure shown in FIG. 20. The Cu.sub.3 Si layer 76 is then chemically removed by a 5 sec. dip in 50:1 diluted HF, resulting in the structure shown in FIG. 21.

Alternatively, the thin Si layer 74 in FIG. 16 can be selectively deposited over the Ge layer 70 to avoid the lithography step. This technique allows the use of Cu.sub.3 Ge in a self-aligned process for VLSI technology.

The present invention also contemplates a self-aligned Cu.sub.3 Ge process to produce low resistance self-aligned Cu.sub.3 Ge for advanced bipolar, CMOS, and BiCMOS devices. More particularly, with reference to FIGS. 22-25, self-aligned copper germanide can be formed in the following sequence:

1. a selective deposition of a thin Ge film 78 (e.g., 70 nm) over exposed silicon (FIG. 22) of the form shown in FIG. 15. Such deposition is possible with UHV/CVD or other selective epitaxy processes at fairly low temperatures (.ltoreq.700.degree. C.).

2. sputter or evaporate a layer 79 of Cu (e.g. 140 nm) as shown in FIG. 23.

3. the structure shown in FIG. 23 is then heated to temperatures in the range of about 150.degree.-200.degree. C. to form Cu.sub.3 Ge (80) as shown in FIG. 24.

4. a selective wet chemical etch, using for example 10:1 solution of HNO.sub.3 :H.sub.2 O with selectivity of 15:1, is then used to remove the unreacted Cu of layer 79 while leaving Cu.sub.3 Ge intact, as shown in FIG. 25.

Step 1 is not necessary if the substrate is Ge. Alternatively, with a Si substrate one can implement a Si/Ge deposition or ion implantation of Ge followed by thermal oxidation and oxide etch to pile up Ge at the surface.

Possible CMOS devices with self-aligned copper germanide over gate, source, and drain may thus be constructed in the form illustrated in FIG. 26, which is similar to that indicated in FIG. 7 for Cu.sub.3 Si. Similarly, examples of bipolar devices with self-aligned Cu.sub.3 Ge over emitter, base and collector are shown in FIGS. 27 and 28.

An improved technique for fabricating a MOS structure at very low temperatures for applications in CMOS devices in accordance with the invention is illustrated in FIGS. 29 through 32. A layer of Cu 81 is first deposited to a thickness of from 50 .ANG. to 500 .ANG. on a Si substrate 82 at room temperature, as shown in FIG. 29. The structure in FIG. 29 is then heated to a temperature of 200.degree. C. for a period of from 10 to 30 min. in a pressure of about 10.sup.-7 Torr to form the Cu.sub.3 Si layer 83, as shown in FIG. 30. The structure in FIG. 30 is then cooled to room temperature. This is followed by exposing Cu.sub.3 Si layer 83 to oxygen at a pressure of from 10.sup.-6 to 10.sup.-7 Torr for a period ranging from 30 to 45 min. A layer 84 of Ge is then immediately deposited to a thickness of 300 .ANG. to 500 .ANG. on top of the Cu.sub.3 Si layer 83, as shown in FIG. 31. Oxygen introduced in the layer 83 bonds to Si, thus forming a layer 85 of SiO.sub.x (with x.about.2) and freeing Cu, which remarkably is found to react with Ge forming a layer 86 of Cu.sub.3 Ge, resulting in the structure shown in FIG. 32. The advantage of this simple technique over all prior art is that a MOS structure is formed at very low temperatures.

The present invention may also be applied to FET technology by using Cu.sub.3 Ge as a midgap gate metal. In particular, improvement in transconductance is obtained by eliminating or significantly reducing channel implant for the adjustment of the threshold voltage of FETs to a midgap.

Performance improvement in FET technology, as well as an increase in device density, requires scaling down of device dimensions. Howvever, there are some non-scaling parameters that can be modified only with the choice of suitable materials. One such parameter is the resistivity of the interconnect and gate metallurgy. The other is the work function of the gate metal on silicon. Clearly, there is a limit on the extendability of polysilicon gate FETs to the linewidths at and below 0.5 .mu.m. A presently considered polycide approach for the FET gate, reduces resistivity by two orders of magnitude. This approach consists of forming low resistivity silicide, such as WSi.sub.2 or TiSi.sub.2 with an underlayer of poly-Si over the thin gate SiO.sub.2. This polysilicon layer is required for oxidation and to preserve gate integrity.

However, the problem of a proper work function remains, since it is still the work function of n.sup.+ poly-Si (.phi..sub.m =4.05 eV) that sets the mobility of the carriers in the channel for a given threshold voltage V.sub.T. To maximize the mobility, it is necessary to reduce or eliminate channel implant for threshold adjustment. This, for 0.5 .mu.m NMOS technology, leads to a gate metal with the work function of .phi..sub.mn =.about.4.6 eV, which is between n.sup.+ and p.sup.+ -polysilicon. In CMOS technology, such a choice is desirable as well, since it would require minimal and symmetric channel implants even at linewidths below 0.5 .mu.m.

In accordance with the present invention Cu.sub.3 Ge, having a work function of 4.6 eV, is applied as a midgap gate metal to be used directly over SiO.sub.2. The stability of this material is very high and it is very resistant to oxidation. Furthermore, it is an excellent conductor with room temperature resistivity as low as 5.5 .mu..OMEGA.-cm and decreasing to less than 1 .mu..OMEGA.-cm at 77 K. The lowering of the temperature will significantly reduce RC losses in the interconnects. Si-based FETs with fine line dimensions below 0.5 .mu.m are designed to be operated at liquid nitrogen temperatures and a CMOS process for 77 K operation has already been tested. The stability of Cu.sub.3 Ge on SiO.sub.2 has been demonstrated. It offers excellent behavior in an oxygen environment and compatibility with copper metallization.

An improved technique for fabricating structures at very low temperatures for applications in CMOS devices in accordance with the invention is illustrated in FIGS. 33 through 37. As seen in FIG. 33, a layer 90 of Ge may be deposited on a Si substrate of the form shown in FIGS. 6, 7, and 26. More particularly, after forming the gate insulator pattern, a thin Ge film 90 (e.g., 70 nm) may be selectively deposited in areas above the source and drain on the substrate and the gate oxide or insulator as shown in FIG. 34.

Such deposition is possible with UHV/CVD or other selective epitaxy processes at fairly low temperatures (.ltoreq.700.degree. C.). A layer 91 of Cu is then deposited by a suitable technique, such as evaporating or sputtering, to a thickness of 140 nm, for example, on the structure of FIG. 34 creating the structure of FIG. 35. The structure shown in FIG. 35 is then heated to temperatures in the range of 150.degree.-200.degree. C. causing the Ge in the areas above the gate insulator, source, and drain to react with the Cu layer 91 to form Cu.sub.3 Ge (92) as shown in FIG. 36. A selective wet chemical etch, using for example 10:1 solution of HNO.sub.3 :H.sub.2 O with selectivity of 15:1, is then used to remove the unreacted Cu of layer 91 while leaving Cu.sub.3 Ge, intact, as shown in FIG. 37.

An alternative technique is illustrated in FIGS. 38 through 41. An approximately 200 nm layer 100 of Cu.sub.3 Ge with an optional insulator cap 101 can be patterned over the gate insulator 102 of thin SiO.sub.2 layer 103 as seen in FIG. 38. The n.sup.+ source and drain regions 104, 105, can be formed by ion implantation and drive in a conventional self-aligned fashion. An insulator spacer 106 of SiO.sub.2 or Si.sub.3 N.sub.4 is then formed on the sidewall of the Cu.sub.3 Ge gate electrode stack (100, 101) as in FIG. 39. The thin SiO.sub.2 layer 103 is then etched away over n.sup.+ source and drain regions 104, 105, and Ge (107) is selectively deposited over the exposed source and drain layers. The subsequent processing steps for self-aligned Cu.sub.3 Ge formation over the n.sup.+ source and drain regions are similar to those described with respect to FIGS. 35 through 37. The ultimate structure is of the form shown in FIG. 40.

It will accordingly be seen that systems and processes have been disclosed that provide simple and electrically stable interconnection metallization utilizing copper, which can be achieved with comparatively low-temperature annealing.

It is also contemplated that the Cu-semiconductor phenomenon of the invention is not limited to use in VLSI interconnection metallization but also offers other advantageous metallurgical applications which will be apparent to those of skill in the art in light of the present teaching. For instance, Ge may be used to retard corrosion in Cu piping through the formation of a surface layer of Cu.sub.3 Ge by, e.g., CVD deposition of Ge on the pipe.