High dynamic range pixel amplifier

[0001] The invention relates to the field of semiconductor devices and, in particular, to a high dynamic range pixel amplifier for an imager.

[0002] A CMOS imager circuit includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion node and another transistor for resetting the floating diffusion region node to a predetermined charge level prior to charge transference. Each pixel cell is isolated from other pixel cells in the array by a field oxide region (STI) which surrounds it and separates the doped regions of the substrate within that pixel cell from the doped regions of the substrate within neighboring pixel cells.

[0003] In a CMOS imager, the active elements of a pixel cell, for example a four transistor pixel, perform the necessary functions of (1) photon to charge conversion; (2) resetting the floating diffusion node to a known state before the transfer of charge to it; (3) transfer of charge to the floating diffusion node; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.

[0004] FIG. 1 illustrates a block diagram of a CMOS imager device 100 having a pixel array 110 with each pixel cell being constructed as described above. The pixel array 110 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in the array 110 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 110. The row lines are selectively activated by a row driver 145 in response to a row address decoder 155. The column select lines are selectively activated by a column driver 160 in response to a column address decoder 170. Thus, a row and column address is provided for each pixel.

[0005] The CMOS imager 100 is operated by a control circuit 150 that controls address decoders 155, 170 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 145, 160 that apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal Vrst and a pixel image signal Vsig for each row selected pixel in a column are read by sample and hold circuitry 161 associated with the column device 160. A differential signal Vrst−Vsig is produced for each pixel, which is amplified and digitized by analog-to-digital converter 175. The analog-to-digital converter 175 converts the analog pixel signals to digital signals that are fed to an image processor 180 to form a digital image output.

[0006] Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.

[0007] A schematic diagram of an exemplary CMOS pixel four-transistor (4T) pixel cell 10 is illustrated in FIG. 2. The four transistors include a reset transistor 34, source follower transistor 36, row select transistor 38 and a transfer transistor 32. A photosensor 40 converts incident light into a charge. A floating diffusion region 50 receives charge from the photosensor 40 through the transfer transistor 32 and is connected to the reset transistor 34 and the source follower transistor 36. The source follower transistor 36 outputs a signal proportional to the charge accumulated in the floating diffusion region 50 to a sampling circuit when the row select transistor 38 is turned on. The reset transistor 34 resets the floating diffusion region 50 to a known potential prior to transfer of charge from the photosensor 40 and this reset signal is output and sampled by the sampling circuit. The photosensor 40 may be a photodiode, a photogate, or a photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried PNP photodiode, buried NPN photodiode, a buried PN photodiode, or a buried NP photodiode, among others.

[0008] Image sensors, such as an image sensor employing the conventional pixel cell 10, have a characteristic dynamic range. Dynamic range refers to the range of incident light that can be accommodated by an image sensor in a single frame of pixel data. It is desirable to have an image sensor with a high dynamic range to image scenes that generate high dynamic range incident signals, such as indoor rooms with windows to the outside, outdoor scenes with mixed shadows and bright sunshine, night-time scenes combining artificial lighting and shadows, and many others.

[0009] The dynamic range for an image sensor is commonly defined as the ratio of its largest non-saturating signal to the standard deviation of the noise under dark conditions. The dynamic range is limited on an upper end by the charge saturation level of the sensor, and on a lower end by noise imposed limitations and/or quantization limits of the analog-to-digital converter used to produce the digital image. When the dynamic range of an image sensor is too small to accommodate the variations in light intensities of the imaged scene, e.g., by having a low saturation level, image distortion occurs.

[0010] In a conventional CMOS pixel imager with a photodiode, the photodiode converts incident light to an electrical charge. The photodiode accumulates this charge throughout an integration period. At the end of the integration period, the transfer gate is activated, and the charge is transferred from the photodiode to the floating diffusion region.

[0011] When the incident light is of low-intensity such that the charge transferred from the photosensor to the floating diffusion region is low, the signal is very faint. In such a case, it is desirable for the conversion gain (i.e., the ratio of output voltage to input charge) to be high. When the incident light is of high-intensity such that the charge transferred from the photosensor to the floating diffusion region is greater than the capacity of the floating diffusion region, excess charge may overflow and saturate the pixel cell. In such a case, it is desirable that the conversion gain be low.

[0012] However, with conventional imagers, the floating diffusion regions in a pixel array have a fixed capacitance, which means a fixed conversion gain. That is, for a single integration period, all pixel signals are provided with the same conversion gain. As a result, some pixels may saturate while others may provide a faint signal, limiting the dynamic range of the image sensor. Thus, there is a desire and need for a pixel cell capable of selectively attaining a high conversion gain or a low conversion gain to increase the dynamic range of the image sensor.

[0013] The present invention provides a pixel cell capable of selectively attaining a high or low conversion gain.

[0014] In one exemplary embodiment of the invention, a pixel cell is provided which includes a floating diffusion region with a variable capacitance controlled by a gate, having its own intrinsic capacitance. The source and drain regions of the gate are coupled to the floating diffusion region. When the gate is on, the capacitance of the gate is added to that of the floating diffusion region, effectively increasing the capacitance of the floating diffusion region. When the gate is off, the capacitance of the gate is no longer combined with that of the floating diffusion region, thereby reducing the capacitance of the floating diffusion region to solely the floating diffusion region capacitance.

[0015] The pixel cell is capable of providing two or more different non-destructive readouts of the same image signal from the same integration. One readout is taken with the gate on, a second readout is taken with the gate off. This switchability allows the floating diffusion region to have a greater capacitance in the case of high-intensity light or a lower capacitance in the case of low-intensity light. The benefit of having a floating diffusion region with a greater capacitance when the incident light has high intensity is that it provides a lower conversion gain, and thus lower sensitivity readout. Conversely, the floating diffusion may have a lower capacitance when the incident light is of low intensity, providing a higher conversion gain, and thus higher sensitivity readout. The two readouts may be combined to provide a single pixel output signal having a desired level of conversion gain, or one of the pixel output signals can be discarded and the other used during image processing.

[0016] In another exemplary embodiment, the gate may also be switched to a mid-level (between the on and off states), where the voltage applied to it is approximately midway between an on-voltage and ground. When the gate is at mid-level, a portion of the capacitance of the gate is added to that of the floating diffusion region if the voltage on the floating diffusion region is a threshold voltage below the mid-level gate voltage. This embodiment implements a variable capacitor with built-in threshold in a single transistor, providing a knee in the output charge-voltage profile of a pixel. The knee, created at a desired mid-level voltage, permits high conversion gain for low-intensity light situations and low conversion gain for high-intensity light situations. The kneepoint may be adjusted by adjusting the gate voltage. In this embodiment, a single readout is taken.

[0017] In other exemplary embodiments of the present invention, a switchable gate having intrinsic capacitance is coupled to a floating diffusion region at various locations and in various arrangements relative to the floating diffusion region.

[0036] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

[0037] The term “pixel” refers to a photo-element unit cell containing a photoconversion device or photosensor and transistors for processing an electrical signal from electromagnetic radiation sensed by the photoconversion device. The pixels discussed herein are illustrated and described as inventive modifications to four transistor (4T) pixel circuits for the sake of example only. It should be understood that the invention is not limited to a four transistor (4T) pixel, but may be used with other pixel arrangements having fewer (e.g., 3T) or more (e.g., 5T) than four transistors. Although the invention is described herein with reference to the architecture and fabrication of one pixel, it should be understood that this is representative of a plurality of pixels in an array of an imager device. In addition, although the invention is described below with reference to a CMOS imager, the invention has applicability to any solid state imaging device having pixels, such as a CCD or other imager. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0038] Referring now to the drawings, where like elements are designated by like reference numerals, FIG. 3 illustrates a schematic diagram of an exemplary five-transistor (5T) pixel 20 circuit embodiment of the invention. Pixel 20 has all the elements of the prior art pixel 10 shown in FIG. 2, including a transfer gate 32 (TG), reset transistor 34, source follower transistor 36, row select transistor 38, photosensor 40 (PD), and floating diffusion region 50 (FD). As with the pixel 10 of prior art, the photosensor 40 may be a photodiode, a photogate, or a photoconductor. Pixel 20 also includes a novel booster switch 51 (BS).

[0039] Booster switch 51 has an intrinsic capacitance and is provided to selectively increase the capacitance of the floating diffusion region 50. The booster switch 51 is a gate having source and drain terminals commonly connected to the floating diffusion region 50 and is designed to selectively change the capacitance of the floating diffusion region 50 at least once in a single integration period. The degree to which the booster switch 51 increases the capacitance of the floating diffusion region 50 is controlled by a circuit that supplies a voltage being applied to the gate of the booster switch 51.

[0040] FIGS. 4A and 4B illustrate respective plan views of two exemplary pixel cell embodiments of the present invention 20, 20′ having different layout configurations. FIG. 4A illustrates pixel cell 20 including a transfer gate 32, reset transistor 34, source follower transistor 36, row select transistor 38, photosensor 40, and floating diffusion region 50. Pixel cell 20 also has a booster switch 51 fabricated as a gate positioned parallel to the transfer gate 32. The pixel cell 20′ of FIG. 4B also includes a transfer gate 32, reset transistor 34, source follower transistor 36, row select transistor 38, photosensor 40′, floating diffusion region 50′, and booster switch 51′. However, the photosensor 40′ of FIG. 4B has an extended region 41 past the transfer gate 32 such that the booster switch 51′ may be positioned perpendicular to the transfer gate 32. In the illustrated embodiments, the booster switches 51, 51′ sit respectively adjacent to the floating diffusion regions 50, 50′. FIGS. 5A and 5B are cross sectional views of the pixel cell 20 of FIG. 4A taken along lines 5A—5A and 5B—5B, respectively. The booster switch 51 shown in FIG. 5B has a gate structure 54 and source and drain regions which are commonly connected to the floating diffusion region 50, as shown in FIG. 5A. The operation of these components is illustrated and discussed below with respect to the potential diagrams of FIGS. 6–8.

[0041] Referring to the substrate potential diagrams of FIGS. 6–8, the labels PD, TG, BS and FD are used to represent regions of the photosensor 40, transfer gate 32, booster switch 51, and floating diffusion region 50, respectively. At the outset, and referring back to FIG. 3, reset transistor 34 is turned on to reset the floating diffusion region 50 to a known state, which is read out by source follower transistor 36 through an “on” row select transistor 38 onto output line Vout. During the reset of the floating diffusion region, it may be beneficial to have the booster switch 51 voltage at ground to reduce kTC noise component in the high conversion gain range of operation. In the low conversion gain range of operation, the noise will be dominated by photon noise. Next, and now also referring to FIG. 6A, charge is generated and accumulated by the photosensor 40 (PD) during an integration period. The transfer gate 32 (TG) is off and a first voltage is applied to the booster switch 51 (BS). The voltage turns the booster switch 51 (BS) on, providing the floating diffusion region 50 (FD) with a combined capacitance, including its own inherent capacitance and that of the booster switch 51 (BS). When the transfer gate 32 (TG) is then switched on after charge integration, as shown in FIG. 6B, the charge is transferred from the photosensor 40 (PD), through the transfer gate 32 (TG), and into the booster switch 51 (BS) and floating diffusion region 50 (FD). A small amount of charge is also stored in the transfer gate 32 (TG).

[0042] The transfer gate 32 (TG) is then switched off, as shown in FIG. 6C, and the residual amount of charge in the channel of the transfer gate 32 (TG) is transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD). Substantially all of the photogenerated charge is now stored in the booster switch 51 (BS) and floating diffusion region 50 (FD). At this time, a first pixel image output reading may be taken through the row select transistor for the pixel and sampling the pixel output signal Vout (FIG. 3). This produces a first pixel image output signal Vsig1. Vsig1 is read along the charge-voltage profile shown in FIG. 6C′.

[0043] After the first output reading is taken, the voltage applied to the booster switch 51 (BS) is then brought to ground, turning the booster switch 51 (BS) completely off, as shown in FIG. 6D. Any charge stored in the booster switch 51 (BS) is transferred to the floating diffusion region 50 (FD), such that all of the photogenerated charge is stored in the floating diffusion region 50 (FD) alone. At this time, a second pixel output signal Vout reading may be taken to produce a second pixel image output signal Vsig2. Vsig2 is read along the charge-voltage profile shown in FIG. 6D′.

[0044] The first pixel output reading Vsig1 is a low sensitivity readout, even where the photosensor is nearly fully-saturated as shown in FIG. 6A. Since the booster switch 51 (BS) increases the capacitance of the floating diffusion region 50 (FD) by adding its own capacitance, the charge does not exceed the charge storage capacity of the floating diffusion region 50 (FD), as shown in FIG. 6C. This is also indicated in FIG. 6C′, where the slope of the charge-voltage profile is inversely proportional to the sum of the capacitance of the booster switch and the capacitance of the floating diffusion region. This provides a low conversion gain reading for the pixel, which is beneficial for a nearly fully-saturated pixel, as the following discussion will demonstrate.

[0045] The second pixel output reading Vsig2 is a high sensitivity readout. Once the booster switch 51 (BS) is switched off, as shown in FIG. 6D, the floating diffusion region 50 (FD) may saturate. Since the booster switch 51 (BS) is off, the entire charge is captured on the floating diffusion region 50 (FD) and may overflow. This lower storage capacity is indicated in FIG. 6D′, where the slope of the charge-voltage profile is inversely proportional to the charge storage capacity of the floating diffusion region alone. Comparing the charge-voltage profiles of FIGS. 6C′ and 6D′, it is apparent that the pixel will reach saturation and begin to overflow at a lower level of photogenerated charge in the case of FIG. 6D′, where the slope of the charge-voltage profile is steeper. However, in the present invention, since the low conversion gain reading was taken prior to saturation of the floating diffusion region 50 (FD), the high light intensity signal is not lost as a result of the overflow.

[0046] The pixel readings Vrst, Vsig1, and Vsig2 may be combined in different ways. The combined signal can be digitized by an analog to digital converter, e.g., ADC 175 of FIG. 1, and sent to an image processor, e.g., image processor 180 of FIG. 1. For example, signals Vrst-Vsig1 and Vrst-Vsig2 can be produced, digitized, and sent to an image processor. Other possible combinations of the pixel read out are [Vrst−(Vsig1+Vsig2)/2] or Vrst can be combined with just one of Vsig1 and Vsig2 in accordance with a control signal from the image processor to produce Vrst−Vsig1 or Vsrst−Vsig2, which is digitized and fed to the image processor.

[0047] Another example of the two-stage reading method is illustrated in FIGS. 7A–7D, in the case where the photosensor 40 (PD) is nearly empty after charge integration, i.e., where there is a low level of incident light. After reset and dim charge integration, charge is generated and accumulated by the photosensor 40 (PD), as shown in FIG. 7A. The transfer gate 32 (TG) is off while a first voltage is applied to the booster switch 51 (BS). The voltage turns the booster switch 51 (BS) on, providing the floating diffusion region 50 (FD) with a combined capacitance, including its own inherent capacitance and that of the booster switch 51 (BS). When the transfer gate 32 (TG) is switched on after the integration period, the charge is transferred from the photosensor 40 (PD), through the transfer gate 32 (TG), and into the booster switch 51 (BS) and floating diffusion region 50 (FD), as shown in FIG. 7B. A small amount of charge is also stored in the transfer gate 32 (TG).

[0048] The transfer gate 32 (TG) is then switched off, as shown in FIG. 7C, and the residual amount of charge in the channel of the transfer gate 32 (TG) is transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD). All of the photogenerated charge is stored in the booster switch 51 (BS) and floating diffusion region 50 (FD) combined. At this time, the first pixel output reading Vsig1 may be taken. As shown in FIG. 7C, the first pixel output reading will be faint, or low, since the capacitance of the booster switch 51 (BS) and floating diffusion region 50 (FD) combined is far greater than the charge being sampled. However, once the booster switch 51 (BS) is turned off, the entire charge is captured on the floating diffusion region 50 (FD), thereby boosting the second pixel output reading Vsig2, as shown in FIG. 7D. In this case, a high conversion gain reading is provided and a higher pixel output signal is obtained.

[0049] In both illustrated cases, whether the level of incident light is high or low, the first and second pixel output readings may be combined to provide a single pixel output signal having a desired level of conversion gain, or one of the two signal output signals can be used as the pixel output signal for image processing.

[0050] In another operational embodiment of the present invention depicted in FIGS. 8A–8H, only one pixel output reading is taken. FIGS. 8A–8D depict the potential diagram in a low intensity light setting, where the charge generated and accumulated by the photosensor 40 (PD) is low. As shown in FIG. 8A, the charge in the photosensor 40 (PD) is low, the transfer gate 32 (TG) is off, and a first voltage is applied to the booster switch 51 (BS). The voltage turns the booster switch 51 (BS) on, providing the floating diffusion region 50 (FD) with a combined capacitance, including its own inherent capacitance and that of the booster switch 51 (BS). When the transfer gate 32 (TG) is switched on, the charge is transferred from the photosensor 40 (PD), through the transfer gate 32 (TG), and into the booster switch 51 (BS) and floating diffusion region 50 (FD), as shown in FIG. 8B. A small amount of charge is also stored in the transfer gate 32 (TG).

[0051] The transfer gate 32 (TG) is then switched off, as shown in FIG. 8C, and the residual amount of charge in the channel of the transfer gate 32 (TG) is transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD). All of the photogenerated charge is stored in the booster switch 51 (BS) and floating diffusion region 50 (FD) combined.

[0052] It is important to note that the present invention can remove charge-sharing lag, caused by a high pin voltage (Vpin). For a high dynamic range pixel, the full well of the floating diffusion region must at least match the fill well of the photosensor, the full well of the photosensor being the product of area and Vpin. In the field of imager semiconductor devices, minimized area is desirable. Therefore, in order to minimize area and still accommodate the full well of the photosensor, Vpin must be maximized, thus causing charge-sharing lag in a 4T pixel cell.

[0053] The present invention prevents charge-sharing lag while permitting a high Vpin by adding a booster switch and running it at a high voltage during charge transfer across the transfer gate, thereby providing a high capacitance floating diffusion region. Note that, but for charge-sharing lag, the circuit as described with a booster switch would work with a constant voltage on the booster switch as well as with a change in voltage on the booster switch. By pulsing the booster switch between supply (Vaa) and an intermediate voltage, a high Vpin can be tolerated without causing lag. Without pulsing the booster switch, the area of the photosensor would limit the dynamic range of the pixel.

[0054] After the photogenerated charge has been transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD), as shown in FIG. 8C, the voltage applied to the booster switch 51 (BS) may be lowered approximately midway between the first voltage and ground. In the case where the photogenerated charge is low due to low intensity light, all the charge is transferred from the booster switch 51 (BS) such that only the capacitance of the floating diffusion region 50 (FD) is used to store the charge, as shown in FIG. 8D. At this time, the pixel output reading may be taken.

[0055] According to this operation, the output reading is taken when the booster switch gate voltage is brought to a mid-level, which is designed to create a knee in the charge-voltage profile, as shown in FIG. 9. The term “knee” reflects the fact that an angle in the pixel output charge-voltage profile is created, as there are now two different conversion gains and charge-voltage profile regions with different slopes, one corresponding to charges which are only in the floating diffusion region, e.g., FIG. 8D, and the other corresponding to when the charge is of sufficient magnitude to flow into the gate capacitance region as well, e.g., FIG. 8H. Thus, the “knee” provides high conversion gain for low signals and low conversion gain for high signals.

[0056] Turning to FIG. 9, the first segment 61 of the charge-voltage profile below the knee reflects the higher conversion gain of the pixel when the booster switch is on, but the light intensity is low. The slope of the first segment 61 is inversely proportional to the capacitance of the floating diffusion region. A Vsig1 reading along the first segment 61 represents the voltage output for a low level of charge stored by capacitance of the floating diffusion region alone, despite the fact that the booster switch is at mid-level. When there is a higher level of charge (high intensity light setting), the Vsig 1 reading will be along the second segment 62 above the knee. The second segment 62 has a slope that is inversely proportional to the sum of the capacitance of the floating diffusion region and the capacitance of the booster switch. The second segment 62 has a less-steep slope than the first segment 61, which reflects a lower conversion gain, where the capacitance of the booster switch at mid-level is engaged by storing some of the charge in the booster switch as well as in the floating diffusion region.

[0057] FIGS. 8E–8H illustrate the present embodiment in a high intensity light setting, where the charge generated and accumulated by the photosensor 40 (PD) is high. As shown in FIG. 8E, the charge in the photosensor 40 (PD) is high, the transfer gate 32 (TG) is off, and a first voltage is applied to the booster switch 51 (BS). The voltage turns the booster switch 51 (BS) on, providing the floating diffusion region 50 (FD) with a combined capacitance, including its own inherent capacitance and that of the booster switch 51 (BS). When the transfer gate 32 (TG) is switched on, the charge is transferred from the photosensor 40 (PD), through the transfer gate 32 (TG), and into the booster switch 51 (BS) and floating diffusion region 50 (FD), as shown in FIG. 8F. A small amount of charge is also stored in the transfer gate 32 (TG).

[0058] The transfer gate 32 (TG) is then switched off, as shown in FIG. 8G, and the residual amount of charge in the channel of the transfer gate 32 (TG) is transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD). All of the photogenerated charge is stored in the booster switch 51 (BS) and floating diffusion region 50 (FD) combined.

[0059] After the photogenerated charge has been transferred to the booster switch 51 (BS) and floating diffusion region 50 (FD), as shown in FIG. 8G, the voltage applied to the booster switch 51 (BS) may be lowered approximately midway between the first voltage and ground. In the case where the photogenerated charge is high due to high intensity light, some of the capacitance of the booster switch 51 (BS) that was being combined with the capacitance of the floating diffusion region 50 (FD) is removed from the combined capacitance. Some of the charge is transferred from the booster switch 51 (BS) to the floating diffusion region 50 (FD) and some of the charge stays in the booster switch 51 (BS), as shown in FIG. 8H. At this time, the pixel output reading may be taken.

[0060] The readout voltage for the charge generated from a high intensity light setting will be in the second segment 62, as shown in FIG. 9, where the charge is stored in both the floating diffusion region and the booster switch at mid-level. The output voltage is calculated by extrapolating the readout voltage to segment 63. The segment 63 reflects the value of the charge-voltage profile of the floating diffusion region alone, which, without the knee created by the booster switch, would exceed the output capability of the pixel at a lower level of charge. The knee decision point can be adjusted by adjusting the decrease in voltage applied the booster switch 51.

[0061] Having additional booster switches may further enhance the dynamic range of the pixel. More than one booster switch may be coupled to the floating diffusion region. FIG. 10 illustrates a schematic diagram of a six-transistor (6T) pixel 20 circuit embodiment of the invention. Pixel 20″ has all the elements of the pixel 20 shown in FIG. 3, including a transfer gate 32 (TG), reset transistor 34, source follower transistor 36, row select transistor 38, photosensor 40 (PD), and floating diffusion region 50″ (FD). The 6T pixel 20″ in FIG. 10 includes two booster switches, booster switch A 71 (BSA) and booster switch B 72 (BSB).

[0062] The operation of the 6T pixel 20 embodiment is depicted in FIGS. 11A–11D. In a first step, an exemplary level of charge is generated and accumulated by the photosensor 40 (PD), as shown in FIG. 11A. The transfer gate 32 (TG) is off and a first voltage is applied to both booster switches 71 (BSA) and 72 (BSB). The voltage turns the booster switches 71 (BSA) and 72 (BSB) on, providing the floating diffusion region 50 (FD) with a combined capacitance, including its own capacitance and the intrinsic capacitances of the booster switches 71 (BSA) and 72 (BSB). When the transfer gate 32 (TG) is switched on, the charge is transferred from the photosensor 40 (PD), through the transfer gate 32 (TG), and into the booster switches 71 (BSA) and 72 (BSB) and floating diffusion region 50 (FD), as shown in FIG. 11B. A small amount of charge is also stored in the transfer gate 32 (TG).

[0063] The transfer gate 32 (TG) is then switched off, as shown in FIG. 11C, and the residual amount of charge in the channel of the transfer gate 32 (TG) is transferred to the booster switches 71 (BSA) and 72 (BSB) and floating diffusion region 50 (FD). All of the photogenerated charge is stored in the booster switches 71 (BSA) and 72 (BSB) and floating diffusion region 50 (FD) combined.

[0064] After the photogenerated charge has been transferred to the booster switch 71 (BSA) and 72 (BSB) and floating diffusion region 50 (FD), as shown in FIG. 11C, the voltage applied to the booster switch B 72 (BSB) may be lowered to a desired level between the first voltage and ground, while the voltage applied to the booster switch A 71 (BSA) may be lowered to a desired level between the voltage applied to the booster switch B 72 (BSB) and ground. In this case, some of the capacitances of the booster switches 71 (BSA) and 72 (BSB) that were being combined with the capacitance of the floating diffusion region 50 (FD) is removed from the combined capacitance, as shown in FIG. 11D. In this illustration, none of the charge is stored in the booster switch A 71 (BSA). Only a small amount of the charge is still stored in the booster switch B 72 (BSB), while most of the charge is stored in the floating diffusion region 50 (FD). At this time, the pixel output reading may be taken.

[0065] According to this operation, the output reading is taken when the booster switch gate voltages are lowered to two desired levels, which are designed to create two knees in the charge-voltage profile, as shown in FIG. 12. The first segment 81 of the charge-voltage profile below the knee reflects the higher conversion gain of the pixel when the charge is at such a low level that it can be entirely stored in the floating diffusion region. The second segment 83 above the first knee reflects a slightly higher level of charge, such that some of the charge is stored in booster switch B as well as the floating diffusion region. The third segment 85 above the second knee reflects an even higher level of charge, such that both booster switch B and the floating diffusion region are full, and some additional charge is stored in booster switch A as well. For example, the readout voltage for the level of light depicted in FIG. 11D would be in the second segment 83, close to the second knee, since the floating diffusion region is full and the booster switch B is nearly full. As with the 5T pixel of FIGS. 8A–8H, the knee decision point of a 6T pixel can be adjusted by adjusting the decrease in voltage applied to the booster switches A and B. Alternatively, one or both of the booster switches may be used on, off, or at mid-level, such that the 6T pixel behaves as a 5T pixel according to either the two-reading embodiment or the single-reading embodiment of the present invention.

[0066] The pixel of the present invention can be used in a pixel array 110 of the imager device 100 illustrated in FIG. 1. FIG. 13 shows a camera device 200, a typical processor-based camera device modified to include an imager device 100 (FIG. 1) employing pixels of the present invention as an input device to the device 200. The imager device 100 may also receive control or other data from camera device 200 as well.

[0067] Camera device 200 includes a central processing unit (CPU) 202 that communicates with various devices over a bus 204. Some of the devices connected to the bus 204 provide communication into and out of the system 200, illustratively including an input/output (I/O) device 206 and imager device 100. Other devices connected to the bus 204 provide memory, illustratively including a random access memory system (RAM) 210, and a peripheral memory device such as FLASH memory 212. The imager device 100 may be a CCD imager or CMOS imager constructed in accordance with any of the illustrated embodiments.

[0068] The camera device 200 may also be included in a processor-based camera system 300, as illustrated in FIG. 14. Examples of processor-based camera systems 300 which may employ the camera device 200, include, without limitation, computer systems, camera systems, scanners, machine vision systems, vehicle navigation systems, video telephones, surveillance systems, auto focus systems, star tracker systems, motion detection systems, image stabilization systems, and others.

[0069] System 300 includes a central processing unit (CPU) 302 that communicates with various devices over a bus 304. Some of the devices connected to the bus 304 provide communication into and out of the system 300, illustratively including an input/output (I/O) device 306 and camera device 200. Other devices connected to the bus 304 provide memory, illustratively including a random access memory system (RAM) 310, hard drive 312, and one or more peripheral memory devices such as a floppy disk drive 314 and compact disk (CD) drive 316. The camera device 200 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, in a single integrated circuit.

[0070] The above description and drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the invention. Modification of, and substitutions to, specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.