Charge-to-voltage converter with adjustable conversion factor

[0002] This is a continuation, of application Ser. No. 08/566,476 filed Dec. 4, 1995 now abandoned which is a continuation of Ser. No. 08/323,052 filed Oct. 12, 1994 now abandoned which is a continuation of Ser. No. 08/026,017 filed Mar. 4, 1993, now abandoned.

[0003] The present invention relates to a charge-to-voltage converter for converting signal charge packets transferred thereto from a charge transfer region into a signal voltage. In particular, it relates to a charge-to-voltage converter of a floating diffusion output type and a floating gate output type.

[0004] In a horizontal charge transfer region of a CCD area sensor or in a charge transfer region of a CCD delay line, a charge-to-voltage converter of a floating diffusion output type or a floating gate output type is employed as an output circuit for detecting input signal charge packets obtained from a charge transfer region and converting such signal charge packets into a signal voltage.

[0005] As shown in FIG. 5, in a conventional charge-to-voltage converter of a floating diffusion output type, a positive pulse is applied to a precharge gate 7 to switch on the PG 7, so that a potential in an floating diffusion (FD) region 1 can be used as a precharge voltage Vpd applied to a precharge drain (PD) region 2. Subsequently,in a state where the precharge gate is switched off, the signal charge packets transferred from a CCD transfer region 3 are injected into the FD region 1 via an output gate (OG). A signal voltage is produced by detecting the signal potential variation caused in the FD region 1.

[0006] Meanwhile as shown in FIG. 6, in another conventional charge-to-voltage converter of a floating gate output type, an floating gate (FG) 4 is provided on a substrate and is partially overlapped by output gate (OG) of a CCD transfer register 3, and the switching (on/off) action of a MOS transistor 5 is controlled by reset clock pulses φ reset of a predetermined period, so that the FG 4 can be reset periodically to a reset voltage Vreset. A signal voltage is obtained by utilizing the potential variation caused in the FG 4 in accordance with the signal charge passed through the channel under the FG 4.

[0007] However, in the conventional charge-to-voltage converter of a floating diffusion output type and a floating gate output type mentioned above, the capacitance of the converter is of a fixed value. It is, therefore, impossible to selectively change the charge-to-voltage conversion factor of the converter, and the conversion factor is determined merely as a single value as follows.

[0008] With regard to the signal charge quantity Q, the signal amplitude V in the FD region 1 (in FIG. 5) and 11 (in FIG. 6) is expressed as

[0009] V=Q/C=Ne−/C  (1)

[0010] where N is the number of electrons; e-denotes an elemental charge (−1.6×10−19[C]); and C is the capacitance of the FD region 1 (in FIG. 5) and 11 (in FIG. 6).

[0011] Therefore the conversion factor ηH, i.e., the signal amplitude obtained at the time of input of one electron to the FD region 1 (in FIG. 5) and 11 (in FIG. 6), is given by

[0012] ηH=V/N=e−/C  (2)

[0013] As a result, if the conversion factor is once set to a great value in design, the amplitude of the converted voltage is rendered excessively high when a large quantity of signal charge packets is input. Consequently such amplitude exceeds the maximum allowable limit of the converter to eventually raise a problem that proper charge-to-voltage conversion fails to be executed, whereby a sufficient dynamic range of conversion is not achievable.

[0014] To the contrary, if the conversion factor of the converter is set to a small value in design for the purpose of complying with a large quantity of input signal charge packets as well, the amplitude of the converted voltage is rendered excessively low when the input signal charge packets are small in quantity. Harmful influence of noise is prone to be induced by the excessively low voltage which eventually raises a problem in practical use. In this case also, therefore, a sufficient dynamic range of conversion is not achievable either.

[0015] In view of the circumstances mentioned, it is an object of the present invention to provide an improved charge-to-voltage converter which is changeable of the charge-to-voltage conversion factor of the converter by changing the capacitance of the floating diffusion or floating gate.

[0016] It is another object of the present invention to provide an improved charge-to-voltage converter which is capable of realizing a sufficiently wide dynamic range in the conversion to comply with any state where the input signal charge packets are extremely small or great in quantity.

[0017] In one aspect of the present invention, there is provided a charge-to-voltage converter of a floating diffusion output type for producing a signal voltage by injecting signal charge packets transferred from a charge transfer region into a floating diffusion region via an output gate. The converter includes a precharge drain region which is supplied with a reset voltage, a diffusion region which is formed between the floating diffusion through a first channel region and the precharge drain region through a second channel region, a first precharge gate electrode which is formed on the first channel region and a second precharge gate electrode which is formed on the second channel region.

[0018] In another aspect of the present invention, there is provided a charge-to-voltage converter of a floating gate output type for producing a signal voltage out of signal charge packets transferred thereto from a charge transfer region by detecting a potential variation in a floating gate provided on a substrate and is partially overlapped by output gate electrode of the charge transfer register. The converter includes a first diffusion region which is supplied with a reset voltage, a plurality of diffusion regions which are formed between the floating gate and the first diffusion region through a first channel region, at least one channel region which are formed between the diffusion regions and a plurality of reset gate electrodes which are formed on the first channel region and the at least one channel region.

[0019] In accordance with the present invention, since the capacitance of the floating diffusion or floating gate is changeable, hence achieving advantageous effects that the dynamic range of conversion can be widened. Therefore, when the invention is applied to a CCD imager or the like, a remarkable compliance is attainable in any state where the quantity of input light is extremely small or great.

[0020] The invention will be more readily understood with reference to the accompanying drawings, wherein:

[0021] FIGS. 1(a)-1(c) show the constitution of a first embodiment of the present invention applied to a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof;

[0022] FIGS. 2(a)-2(c) show the constitution of a second embodiment of the present invention applied to a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof;

[0023] FIGS. 3(a)-3(c) show the constitution of a third embodiment of the present invention applied to a floating gate output type, in which (a) is a pattern diagram seen from above, and (b) is an equivalent circuit diagram thereof;

[0024] FIGS. 4(a)-4(c) show the constitution of a fourth embodiment of the present invention applied to a floating gate output type, in which (a) is a pattern diagram seen from above, and (b) is an equivalent circuit diagram thereof;

[0025] FIGS. 5(a)-5(c) show the constitution of a conventional example of a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof; and

[0026] FIGS. 6(a)-6(c) show the constitution of another conventional example of a floating gate output type, in which (a) is a pattern diagram seen from above, and (b) is an equivalent circuit diagram thereof.

[0027] The preferred embodiments of the present invention will be described in detail by referring to FIGS. 1 to 4. In these drawings, the same reference numerals are utilized as shown in FIG. 5 and FIG. 6 so far as the same portions are referred.

[0028] FIG. 1 shows the constitution of a first embodiment of the present invention applied to a floating diffusion output type. In this embodiment, a diffusion region 6 is formed adjacent to an FD region 1 through a channel region, and a precharge drain (PD) region 2 is formed adjacent to the diffusion region 6 through a channel region. Further two precharge gates 7, 8 are formed on the channel regions respectively between such diffusion regions 1 & 6 and 6 & 2 to thereby constitute two MOS transistors (switch elements) Q1 and Q2.

[0029] The charge-to-voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the two MOS transistors Q1 and Q2 in accordance with gate pulses PG1 and PG2 respectively.

[0030] (1) In Raising the Conversion Factor:

[0031] Q1 is turned on or off by gate pulses PG1 corresponding to the conventional gate pulses PG.

[0032] Q2 is kept in its on-state.

[0033] (2) In Lowering the Conversion Factor:

[0034] Q1 is kept in its on-state.

[0035] Q2 is turned on or off by gate pulses PG2 corresponding to the conventional gate pulses PG.

[0036] The conversion factor is changeable in the following manner by selectively setting the two MOS transistors Q1 and Q2 as mentioned above.

[0037] (1) In Raising the Conversion Factor:

[0038] With regard to the signal charge quantity Q, the signal amplitude VH in the FD region 1 is expressed as

[0039] VH=Q/C1=Ne−/Cl  (3)

[0040] where N is the number of electrons; e-denotes an elemental charge (−1.6×10−19[C]); and C1 is the capacitance of the FD region 1.

[0041] Therefore the conversion factor ηH, i.e., the signal amplitude obtained at the time of input of one electron to the FD region 1, is given by

[0042] ηH=VH/N=e−/C1  (4)

[0043] (2) In Lowering the Conversion Factor:

[0044] Under the same conditions as those in (3), the signal amplitude VL in the FD region 1 is expressed as

[0045] VL=Q/(C1+C2)=Ne−/(C1+C2)  (5)

[0046] where C2 is the capacitance of the diffusion region 6. The conversion factor ηL is given by

[0047] ηL=VL/N=e−/(C1+C2)  (6)

[0048] As apparent from the above,

[0049] ηH>ηL  (7)

[0050] Consequently it becomes possible to select either of two conversion factors by controlling the switching (on/off) actions of the two MOS transistors Q1, Q2 under external control of the terminal voltages PG1, PG2 of the precharge gates 7, 8.

[0051] FIG. 2 shows the constitution of a second embodiment of the present invention applied to a floating diffusion output type. In the second embodiment, two diffusion regions 6, 9 are formed adjacent to an FD region 1 through channel regions respectively. A PD region 2 is formed adjacent to the outer diffusion region 9 through a channel region. Further three precharge gates 7, 8, 10 are formed on the channel regions respectively between such diffusion regions 1 & 6, 6 & 9 and 9 & 2 to thereby constitute three MOS transistors Q1, Q2, Q3.

[0052] The charge voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the three MOS transistors Q1, Q2, Q3 in accordance with gate pulses PG1, PG2, PG3 respectively.

[0053] (1) In Raising the Conversion Factor to the Maximum:

[0054] Q1 is turned on or off by gate pulses PG1 corresponding to the conventional gate pulses PG.

[0055] Q2 is kept in its on-state.

[0056] Q3 is also kept in its on-state.

[0057] (2) In Setting the Conversion Factor to an Intermediate Value:

[0058] Q1 is kept in its on-state.

[0059] Q2 is turned on or off by gate pulses PG2 corresponding to the conventional gate pulses PG.

[0060] Q3 is kept in its on-state.

[0061] (3) In Lowering the Conversion Factor to the Minimum:

[0062] Q1 is kept in its on-state.

[0063] Q2 is also kept in its on-state.

[0064] Q3 is turned on or off by gate pulses PG3 corresponding to the conventional gate pulses PG.

[0065] The conversion factor is chargeable in the following manner by selectively setting the three MOS transistors Q1, Q2, Q3 as mentioned above.

[0066] (1) In Raising the Conversion Factor to the Maximum:

[0067] VH=Ne−/C1

[0068] ηH=e−/C1  (8)

[0069] (2) In Setting the Conversion Factor to an Intermediate Value:

[0070] VM=Ne−/(C1+C2)

[0071] ηM=e−/(C1+C2)  (7)

[0072] (3) In Lowering the Conversion Factor to the Minimum:

[0073] VL=Ne−/(C1+C2+C3)

[0074] ηL=e−/(C1+C2+C3)  (8)

[0075] where C3 is the capacitance of the diffusion region 9.

[0076] As apparent from the above,

[0077] ηH>ηM>ηL  (9)

[0078] Consequently it also becomes possible to select any of three conversion factors by controlling the switching (on/off) actions of the three MOS transistors Q1, Q2, Q3 under external control of the terminal voltages PG1, PG2, PG3 of the precharge gates 7, 8, 10.

[0079] FIG. 3 shows the constitution of a third embodiment of the present invention applied to a floating gate output type. In this embodiment, switch elements for resetting an FG 4 at a reset voltage Vreset in a predetermined period (φ reset) consist of two MOS transistors Q11, Q12 which are composed of three diffusion regions 11-13 formed adjacent to one another through channel regions, and two gate electrodes 14, 15 formed on the channel regions between such diffusion regions 11-13 respectively, wherein the diffusion region 11 at one end is connected to the FG 4, and the reset voltage Vreset is applied to the diffusion region 13 at the other end.

[0080] The charge-to-voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the two MOS transistors Q11 and Q12 in accordance with gate pulses φ reset1 and φ reset2.

[0081] (1) In Raising the Conversion Factor:

[0082] Q11 is turned on or off by gate pulses φ reset1 corresponding to the conventional gate pulses φ reset.

[0083] Q12 is kept in its on-state.

[0084] (2) In Lowering the Conversion Factor:

[0085] Q11 is kept in its on-state.

[0086] Q12 is turned on or off by gate pulses φ reset2 corresponding to the conventional gate pulses φ reset.

[0087] The conversion factor is changeable in the following manner by selectively setting the two MOS transistors Q11 and Q12 as mentioned above. In the following calculations, the channel capacitance Cch is ignored since its value is negligibly small. However, there occurs essentially no difference at all even if its value is great.

[0088] (1) In Raising the Conversion Factor:

[0089] With regard to the signal charge quantity Qc, the signal amplitude VH in the FD region 1 is expressed as

[0090] VH=Q/C11=Ne−/C11

[0091] ηH=e−/C11  (10)

[0092] where C11 is the capacitance of the diffusion region 11.

[0093] (2) In Lowering the Conversion Factor:

[0094] VL=Q/(C11+C12)=Ne−/(C11+C12)

[0095] ηL=e−/(C11+C12)  (11)

[0096] where C12 is the capacitance of the diffusion region 12.

[0097] As apparent from the above,

[0098] ηH>ηL  (12)

[0099] Consequently it also becomes possible to select either of two conversion factors by controlling the switching (on/off) actions of the two MOS transistors Q11, Q12 under external control of the terminal voltages φ reset1, φ reset2 of the gates 14, 15.

[0100] FIG. 4 shows the constitution of a fourth embodiment of the present invention applied to a floating gate output type. In this embodiment, a diffusion region 16 and a gate electrode 17 are provided in addition to the structure of the foregoing third embodiment to thereby increase another MOS transistor. And thus the switch elements for resetting the FG 4 at the reset voltage Vreset in a predetermined period φ reset) are composed of three MOS transistors Q11, Q12 and Q13.

[0101] The charge-to-voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the three MOS transistors Q11, Q12 and Q13 as follows in accordance with gate pulses φ reset1, φ reset2 and φ reset3 respectively.

[0102] (1) In Raising the Conversion Factor to the Maximum:

[0103] Q11 is turned on or off by gate pulses φ reset1 corresponding to the conventional gate pulses φ reset.

[0104] Q12 is kept in its on-state.

[0105] Q13 is also kept in its on-state.

[0106] (2) In Setting the Conversion Factor to an Intermediate Value:

[0107] Q11 is kept in its on-state.

[0108] Q12 is turned on or off by gate pulses φ reset2 corresponding to the conventional gate pulses φ reset.

[0109] Q13 is kept in its on-state.

[0110] (3) In Lowering the Conversion Factor to the Minimum:

[0111] Q11 is kept in its on-state.

[0112] Q12 is also kept in its on-state.

[0113] Q13 is turned on or off by gate pulses φ reset3 corresponding to the conventional gate pulses φ reset.

[0114] The conversion factor is changeable as follows by the setting mentioned above. In the following equations, the channel capacitance Cch has been ignored since its value is negligibly small. However, there occurs essentially no difference at all even if its value is great.

[0115] (1) In Raising the Conversion Factor to the Maximum:

[0116] VH=Ne−/C11

[0117] ηH=e−/C11  (13)

[0118] (2) In Setting the Conversion Factor to an Intermediate Value:

[0119] VM=Ne−/(C11+C12)

[0120] ηM=e−/(C11+C12)  (14)

[0121] (3) In Lowering the Conversion Factor to the Minimum:

[0122] VL=Ne−/(C11+C12+C13)

[0123] ηL=e−/(C11+C12+C13)  (15)

[0124] where C13 is the capacitance of the diffusion region 16.

[0125] As apparent from the above,

[0126] ηH>ηM>ηL  (16)

[0127] Consequently it also becomes possible to select any of three conversion factors by controlling the switching (on/off) actions of the three MOS transistors Q11, Q12, Q13 under external control of the terminal voltages φ reset1, φ reset2, φ reset3 of the gates 14, 15, 17.

[0128] In the embodiments mentioned above, one or two diffusion regions are formed in addition to the known structure in the prior art to thereby constitute an improvement with an increase of one or two MOS transistors. However, it is to be understood that the present invention is not limited to such embodiments alone. For example, three or more diffusion regions may be added to further increase the number of MOS transistors.