System and method for suppression of RFI interference

[0001] 1. Field of the Invention

[0002] This invention relates to the field of radio frequency interference (RFI) suppression, and particularly to systems and methods for suppressing RFI in wired transmission systems.

[0003] 2. Description of the Related Art

[0004] The performance of wired data transmission systems can be degraded by RFI which originates from local amateur radio operators. For example, a high-speed Internet access system employing VDSL modems might occupy a bandwidth of up to 12 MHz; amateur radio bands are allocated frequency bands between 1.8 MHz and 30 MHz. A signal received by the modem is typically fed to the input of an analog-to-digital converter (ADC). Due in part to poor balance of the twisted pairs making up the data transmission system, RFI from a local ham operator can be coupled into the ADC input. The RFI power may be 10–20 dB larger than the received signal power, thereby significantly degrading the dynamic range of the ADC.

[0005] Some modems employ a receive (RX) filter designed to attenuate any signals beyond 12 MHz. However, such filters are generally less than 100% effective; as such, RFI due to amateur radio frequencies between 1.8 MHz and 30 MHz can adversely affect modem performance.

[0006] A system and method for suppressing RFI is presented, which significantly reduces RFI present in a data signal applied to the analog input of a receiving system.

[0007] The present system receives a differential input signal V_d at a first input, and a signal V_cm which varies with the common mode component of V_d at a second input. Signal V_cm is compared with a predetermined threshold, and an “enable” flag is set when V_cm is greater than the threshold—thereby indicating the presence of RFI in differential input signal V_d and V_cm.

[0008] V_cm is phase shifted by a programmable amount Φ₁, and the phase-shifted output is provided to a first amplifier having a programmable gain G1 which produces an output V_A1 that varies with V_cm*G1. A subtractor circuit receives V_d at a first input and V_A1 at a second input and produces an output V_sub which varies with V_d−V_A1. A second amplifier having a programmable gain G2 receives V_sub at an input and produces an output V_A2 which varies with V_sub*G2.

[0009] An analog input signal processing circuit, typically an analog-to-digital converter (ADC), receives V_A2 at an input which has an associated maximum dynamic range. A processor, typically a digital signal processor (DSP), receives the enable flag and a signal which varies with V_A2—such as the output of an ADC—at respective inputs. The processor is arranged to:

[0010] adjust programmable gain G2 such that V_A2 covers the analog input signal processing circuit's maximum dynamic range;

[0011] adjust, if the enable flag is set, programmable phase Φ₁ and programmable gain G1 to minimize V_A2;

[0012] adjust, after V_A2 is minimized, programmable gain G2 to increase V_A2 such that it again covers the maximum dynamic range.

[0013] When so arranged, most or all of the RFI present in input signal V_d is subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving V_A2.

[0014] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

[0017] The present system reduces undesirable RFI present in a data signal received by, for example, a VDSL modem. The RFI typically originates with local amateur radio operators, which operates on frequency bands from 1.8 MHz to 30 MHz, though the invention is applicable to RFI in any frequency band. Reduction or cancellation of undesirable RFI is needed to ensure that the full dynamic range of the analog receiving circuitry is available to the incoming data signal.

[0018] A diagram illustrating the principles of the present system is shown in FIG. 1. A differential input signal V_d is received at an input 10. A signal V_cm which varies with the common mode component of differential input signal V_d is received at an input 12. In a typical application such as a VDSL modem, a transmitted differential input signal is normally coupled to the modem through a hybrid circuit which includes a transformer. V_cm could be obtained from a center tap on the primary side of the transformer, with V_d being the differential signal across the secondary side. Undesirable RFI may be coupled into V_d and V_cm.

[0019] When RFI is present—

V_d is given by:
V_d=V_dmt+V_rfid+V_n1,
where V_dmt is the desired differential input signal, V_rfid is the differential component of the RFI present in V_d, and V_n1 is an uncorrelated noise signal.
V_cm is given by:
V_cm=V_dmtc+V_rfic+V_n2,
where V_dmtc is the common mode part of the desired input signal, V_rfic is the common mode part of the RFI signal, and V_n2 is an uncorrelated noise signal.

[0020] The differential and common mode components of the RFI signal can be approximated by:
V_rfid=V_da·cos(ωt+Φ_d) and V_c=V_c·cos(ωt+Φ_c),
where V_da and V_c are the amplitudes of the differential and common mode components of the RFI present in V_d and V_cm, respectively, ω is the frequency of the RFI signal, and Φ_d and Φ_c are the phase differences between V_rifd and V_rfic, respectively, and the RFI signal. Then,

[0021] $V_c=\frac{5.48\sqrt{P_t}}{d}\mathrm{and}{V}_{\mathrm{da}}=\frac{5.48\sqrt{P_t}}{d·b}$
where P_t is the RF power transmitted, d is the distance of the modem input cable from the amateur radio transmitter, and b is the “balance” of the cable. “Balance” of the cable is a function of frequency, and reduces at higher frequencies. As a typical example, P_t might be 400 W, d might be 10 m, and b might be 30 db. Then, V_rfid will be about 11 volts, and V_rfic will be about 360 mv. Therefore, in the presence of RFI, V_rfid and V_rfic will be much larger than the desired signal (typically around 60–80 mv for a cable length of 1.5 km). As such, small noise sources V_dmtc, V_n1 and V_n2 can be neglected.

[0022] Signal V_cm is preferably fed to a programmable phase shifter circuit 13 which introduces a phase shift of Φ₁ into V_cm. Φ₁ is preferably varied by means of a control signal ch_PH provided to phase shifter 13; circuit 13 is arranged to vary Φ₁ when ch_PH is set, and to hold Φ₁ at its current setting when ch_PH is reset. The phase-shifted output of phase shifter 13 is connected to an amplifier A1 having a programmable gain G1 which produces an output V_A1 that varies with V_cm*G1. Gain G1 is preferably varied by means of a control signal ch_G1 provided to A1; A1 is arranged to vary G1 when ch_G1 is set, and to hold G1 at its current setting when ch_G1 is reset. Differential input signal V_d is connected to a first input of a subtractor circuit 14, and V_A1 is connected to the subtractor's second input, such that the subtractor produces an output V_sub which varies with V_d−V_A1. Signal V_sub is connected to an amplifier A2 having a programmable gain G2, which produces an output VA2 that varies with V_sub*G2. Gain G2 is preferably varied by means of a control signal ch_G2 provided to A2; A2 is arranged to vary G2 when ch_G2 is set, and to hold G2 at its current setting when ch_G2 is reset. In the examples herein, the control signals are “set” when they are at a logic “1”, and are “reset” when they are at a logic “0”; of course, this might be reversed in some applications.

[0023] Signal V_A2 is provided to the input 15 of an analog input signal processing circuit 16 which has an associated maximum dynamic range. When RFI is present in signal V_A2, it takes up some of this dynamic range, and thereby reduces the dynamic range available for the desired input signal. It is this dynamic range that the invention is designed to take full advantage of, by reducing the RFI present in V_A2.

[0024] When arranged as shown (and with V_dmtc, V_n1 and V_n2 neglected), signal V_A2 is given by:
V_A2=G2(V_dmt+V_da·cos(ωt+Φ_d)−(G1(V_c·cos(ωt+Φ_c+Φ₁)))
The RMS value of signal V_A2 for a given V_dmt signal will be a minimum when the differential and common mode components of the RFI are cancelled. To achieve this, the phase Φ₁ and the gain Gi need to be adjusted such that Φ_c+Φ₁=Φ_d and

[0025] $\mathrm{G1}=\frac{V_{\mathrm{da}}}{V_c};$
the RMS value of signal V_A2 will be higher for all other values of Φ₁ and G1. The present invention controls the phase Φ₁ and the gain G1 of amplifier A1 to minimize the RMS value of signal V_A2. If RFI is present, there will be a common mode RFI component present in V_cm, and a differential component present in V_d. The common mode and differential RFI components present in V_cm and V_d are highly correlated. Thus, gain applied to V_cm (G1) is adjusted so that the magnitudes of the common mode and differential RFI components match, so that when the gain-adjusted common mode component is subtracted from the differential component, the RFI in the resulting signal is substantially reduced or eliminated.

[0026] If there is RFI present, then the common mode component V_dmtc of the desired signal will be attenuated by the gain G1 of PGA1, and there will be limited degradation of desired signal V_dmt. This is because, after attenuation, the common mode component V_dmtc will be much smaller than V_dmt, and thus the subtraction will have a very limited effect on V_dmt.

[0027] The invention preferably provides a means of disabling the RFI cancellation scheme when the RFI present is less than a predetermined threshold, so that the scheme does not add noise to the signal path or reduce the magnitude of desired signal V_dmt. This is accomplished by comparing V_cm with a threshold voltage (V_th) selected to indicate the presence of RFI, using a comparison circuit 19 such as a comparator A3 (as shown in FIG. 1), for example. When V_cm>V_th, an “enable flag” ENB is set—indicating the presence of RFI; conversely, when V_cm<V_th, ENB is reset (i.e., set to a logic “0” in the examples herein).

[0028] The invention includes a processor 20, typically a DSP, which receives ENB and outputs control signals ch_G2, ch_G1 and ch_PH. When ENB is reset, processor 20 disables the RFI cancellation scheme. Disabling the cancellation scheme comprises resetting control signals ch_G1 and ch_PH so that G1 and Φ₁ become fixed. Disabling the cancellation scheme preferably also comprises disabling subtractor circuit 14, such that V_sub=V_d−V_A1 when ENB is set, and V_sub=V_d when ENB is not set; this might be accomplished with a control signal ENB2 generated by the DSP, which tracks the state of ENB.

[0029] The system operates as follows. An RMS voltage value V_RMS(max) corresponding to the full dynamic range of the input 15 of analog input signal processing circuit 16 is ascertained. Circuit 16 typically produces an output 18 which varies with the voltage applied to its input. The RMS voltage V_A2(RMS) of signal V_A2 applied to input 15 is compared with V_RMS(max); this is preferably accomplished by processor 20, which receives the output 18 of analog input signal processing circuit 16 and compares it with a stored value representing V_RMS(max). When V_A2(RMS)=V_RMS(max), no action is necessary. However, if V_A2(RMS)≠V_RMS(max), processor 20 sets control signal ch_G2, causing the gain G2 of amplifier A2 to vary. G2 is varied until V_A2(RMS)=V_RMS(max), at which point ch_G2 is reset, thereby locking in G2.

[0030] Now, if enable flag ENB is set, processor 20 sets control signal ch_PH, causing the phase shift Φ₁ introduced by programmable phase shifter 13 to vary. Φ₁ is varied until a minimum value for V_A2(RMS) is achieved, at which point ch_PH is reset. Control signal ch_G1 is then set, causing the gain G1 of amplifier A1 to vary. G1 is varied until a minimum value for V_A2(RMS) is achieved, at which point ch_G1 is reset. Φ₁ and G1 are varied iteratively until the lowest possible minimum value for V_A2(RMS) is achieved, at which point G1 and Φ₁ are locked in. Because only Φ₁ and G1 are being adjusted, any reduction in V_A2(RMS) as Φ₁ and G1 are varied is largely due to RFI being subtracted from V_d by subtractor 14.

[0031] Then, processor 20 again sets control signal ch_G2, causing the gain G2 of amplifier A2 to vary until V_A2(RMS)=V_RMS(max), at which point ch_G2 is reset. By so doing, most or all of the RFI present in input signal V_d is subtracted from V_d by subtractor circuit 14.

[0032] Comparison circuit 19 might alternatively be implemented with a one-bit or a multiple-bit ADC, with V_th connected to the ADC's reference voltage input and V_cm connected to its analog input. In some applications, it might be desirable for the system to have a variable threshold voltage V_th. This could be accommodated by using a multiple-bit ADC that receives a fixed threshold voltage Vth, with processor 20 arranged to interpret the ADC's digital output based on the desired threshold voltage. If using a one-bit ADC, V_th itself would have to vary.

[0033] A preferred method of reducing RFI in accordance with the present invention is illustrated in FIG. 2; the steps shown in the flow chart would be employed with a system configuration similar to that shown in FIG. 1. In step 30, the RMS value of the signal applied to the analog input signal processing circuit is measured; in the preferred embodiment, the analog input signal processing circuit is an ADC, and a DSP monitors the ADC's digital output (which varies with the ADC's analog input) to determine the RMS value of the ADC's input signal. A DSP typically employs an algorithm to perform the measurement, which determines the RMS value for a “frame” having a defined duration.

[0034] Next, in step 32, the measured RMS value is compared with a predetermined value. If the RMS value is equal to the predetermined value—indicating that the applied signal covers the analog input's associated dynamic range—nothing needs to be done, and no changes are made. The gain of amplifier A2 is held constant by keeping ch_G2=0 (step 33), and the RMS value of the applied signal continues to be measured (step 30).

[0035] If the measured RMS value of the applied signal is not equal to the predetermined value, the applied signal is amplified with the gain required to make the applied signal equal to the RMS value (step 34). With respect to the system shown in FIG. 1, this is accomplished by setting control signal ch_G2 such that the gain G2 of amplifier A2 is varied until the RMS value of the applied signal is equal to the predetermined RMS value. If there is no RFI present in the applied signal, adjusting G2 just scales the signal based on its “PAR” (peak-to-average ratio) value. If RFI is present in the applied signal, adjusting G2 results in the RMS value of the desired signal being less than the predetermined value, though this is corrected in the subsequent steps.

[0036] As noted above, an enable flag ENB is set when V_cm is greater than a threshold value V_th, indicating the presence of RFI. In step 36, the state of the enable flag is determined, typically by the processor. If the flag is reset, indicating that V_cm<V_th, then control reverts to step 30. If ENB is set, V_cm is phase-shifted by a Φ₁ that is adjusted until the RMS value of V_A2 is at a minimum (step 38). With respect to the system shown in FIG. 1, this is accomplished by setting control signal ch_PH such that programmable phase shifter 13 varies Φ₁ until V_A2 is minimized. This will be an iterative process, with Φ₁ adjusted and RMS value V_A2 measured (step 40) (preferably by monitoring the digital output of ADC 16) until the minimum RMS value is achieved (step 42). When the minimum RMS value is achieved, control signal ch_PH is reset.

[0037] Then, the phase-shifted V_cm is amplified with a gain G1 that is adjusted until the RMS value of V_A2 is at a minimum (step 44). With respect to the system shown in FIG. 1, this is accomplished by setting control signal ch_G1 such that the gain of amplifier A1 is varied until V_A2 is minimized. This will be an iterative process, with gain G1 adjusted and RMS value V_A2 measured (step 46) (preferably by monitoring the digital output of ADC 16) until the minimum RMS value is achieved (step 48), at which point control signal ch_G1 is reset (step 50)—thereby locking in gain G1. Steps 38, 40, 42, 44, 46, 48 and 50 may be repeated until the values of G1 and Φ₁ which provide the lowest possible RMS value are identified. By achieving the minimum RMS value by adjusting Φ₁ and the gain of A1—which affects only V_cm and not V_d—the RFI component of V_A2 is significantly reduced, leaving only the desired signal.

[0038] Note that it is not essential that the present system and method include the ability to phase-shift V_cm. If Φ_d and Φ_c are small or equal, little to no phase-shifting is required to substantially cancel the RFI. However, in most cases superior RFI cancellation will be achieved when a phase-shifting capability is included. The method illustrated in FIG. 2 is merely a preferred method; many other process sequences could be employed to implement the invention. It is only essential that the common mode component of the differential input signal be amplified and subtracted from the differential input signal so as to minimize the resulting difference signal, and then increasing the gain applied to the resulting difference signal to cover the dynamic range of the receiver's analog input.

[0039] While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.