System and method for extracting and compensating for reference frequency error in a communications system

[0002] 1. Field of Invention

[0003] This invention relates to communications systems. Specifically, the present invention relates systems for measuring and correcting error in reference frequency sources in cellular telecommunications systems.

[0004] 2. Description of the Related Art

[0005] Cellular telecommunications systems are characterized by a plurality of mobile transceivers in communication with one or more base stations. Each transceiver includes a transmitter and a receiver. The receiver must often translate signals within a certain range of frequencies to a different range or band of frequencies. The accuracy of the frequency translation is affected by the accuracy of a periodic reference signal used in the translation. For example, in a code division multiple access (CDMA) cellular telephone network, a local oscillator in a mobile receiver provides a periodic signal that facilitates the translation of incoming radio frequency (RF) signals to an intermediate frequency (IF) band. If the frequency of the local oscillator is inaccurate, the translated signals may be translated outside of the desired IF band.

[0006] Digital telecommunications systems may employ one of several methods to demodulate a digitally modulated waveform. Such methods include binary-phase-shift-keying (BPSK), quadrature-phase-shift-keying (QPSK), offset QPSK (OQPSK), m-ary phase-shift-keying (MPSK), or quadrature amplitude modulation (QAM). It is often necessary for the system to lock to a received RF signal. The ability of the modulator to lock on the signal, and therefore its performance as indicated by the degradation in the measured bit error rate (BER) versus the theoretical BER, is influenced by the phase noise of the generated periodic reference signals.

[0007] Voltage-controlled temperature-compensated crystal oscillators (VC-TCXOs) often generate the periodic reference signals. A VC-TCXO has a control input used to adjust the frequency of the VC-TCXO in response to a high BER.

[0008] To measure the BER, a digital zero-crossing counter circuit is often used to perform error calculations on an IF output from the receiver. However, the counter circuit requires that the IF output signal drive digital circuitry in the zero-crossing circuit. This represents an inconvenience that increases system design time and expense. In addition, processing of high frequency IF signals requires fast digital circuitry that consumes excess power.

[0009] Alternatively, a digital signal processor calculates an error metric from digital baseband signals in the receiver. This system however, typically has limited accuracy and lock-in range.

[0010] Hence, a need exists in the art for an accurate, power-efficient system for measuring errors due to inaccurate reference frequencies. There is a further need for a system to compensate for the errors, the system having excellent error measurement accuracy and lock-in range.

[0011] The need in the art is addressed by the system for extracting and compensating for reference frequency error of the present invention. In the illustrative embodiment, the inventive system is adapted for use with a communications system and includes a frequency generator for outputting a reference signal of a first frequency. The frequency generator has a control input for adjusting the first frequency in response to a control signal. A receive circuit receives an input signal and provides an output signal having a first and second component in response thereto. An error extraction circuit provides an error value based on a phase difference between the first component and the second component, and provides the control signal in response thereto.

[0012] In a specific embodiment the frequency generator includes a voltage-controlled oscillator. The receive circuit is a telecommunications receiver that includes a vector demodulator. The vector demodulator produces in-phase and quadrature signals from the input signal. The in-phase and quadrature signals correspond to the first and second signal components, respectively. The error extraction circuit includes a positive error counting circuit for generating a positive count when the first component lags the second component. The error extraction circuit further includes a negative error counting circuit that generates a negative count when the first component leads the second component. The positive error counting circuit and the negative error counting circuit include first and second edge-triggered J-K flip-flops, respectively. A J-input of the second J-K flip-flop is connected in parallel to a clock input of the first J-K flip-flop, and a J-input of the first J-K flip-flop is connected to a clock input of the second J-K flip-flop. A K-input of the first J-K flip-flop and a K-input of the second J-K flip-flop are tied high.

[0013] In the illustrative embodiment, the error extraction circuit further includes an accumulation circuit for providing a difference of the positive count and the negative counts. The accumulation circuit includes an up-counter having an input connected to a Q-output of the first J-K flip-flop, and a down-counter having an input connected to a Q-output of the second J-K flip-flop. The accumulation circuit further includes a subtractor having an input connected, in parallel, to the output of the up-counter and the output of the down-counter. A frequency error control circuit generates the control signal from the difference of the positive count and the negative counts. The magnitude of the control signal is dependent on parameters of the frequency generator.

[0014] FIG. 1 is a block diagram of a conventional telecommunications receiver having a master reference frequency source for providing a reference frequency.

[0015] FIG. 2 is a diagram showing in-phase and quadrature signals output from a comparator and provided via the receiver of FIG. 1 when the reference frequency has a negative error.

[0016] FIG. 3 is a diagram showing in-phase and quadrature signals output from a comparator and provided via the receiver of FIG. 1 when the reference frequency has a positive error.

[0017] FIG. 4 is a block diagram showing the system for extracting and compensating for reference frequency error of the present invention implemented in the receiver of FIG. 1.

[0018] FIG. 5 is block diagram of the system for extracting and compensating for reference frequency error of FIG. 4.

[0019] FIG. 6 is a more detailed diagram of the system of FIG. 5.

[0020] FIG. 7 is a diagram of a J-K flip-flop module adapted for use with the system of FIG. 5.

[0021] While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant-utility.

[0022] The following review of the operation of a traditional telecommunications receiver is intended to facilitate an understanding of the present invention.

[0023] FIG. 1 is a block diagram of a conventional telecommunications receiver 20. The receiver 20 includes, from left to right, an antenna 22, a duplexer 24, a receive circuit 26, and a digital signal processor 28. A front end of the receive circuit 26 includes, from left to right, an amplifier 30, a radio frequency (RF)-to-intermediate frequency (IF) mixer 32, a bandpass filter 34, and an automatic gain control circuit (AGC) 36. The output of the AGC 36 is connected to a vector demodulator of the receive circuit that includes, from left to right, first 38 and second 40 IF-to-baseband mixers, lowpass filters 42, and analog-to-digital converters (ADCs) 44.

[0024] In operation, the antenna 22 receives a transmitted RF signal that is routed through the duplexer 24 and then input to the receive circuit 26. In the receive circuit 26, the received RF signal is amplified by the amplifier 30 and then converted to an IF signal via the RF-to-IF mixer 32. The resulting IF signal is filtered by the bandpass filter 34 and output to the AGC 36 where the gain of the signal is adjusted and input, in parallel, to the IF-to-baseband mixers 38, 40. The first 38 and second 40 IF-to-baseband mixers output in-phase (I) and quadrature (Q) signal components of the IF signal, respectively. The I and Q signals are then filtered by the lowpass filters 42 and converted to digital signals 50 via the ADCs 44.

[0025] The RF-to-IF mixer 32, the IF-to-baseband mixers 38 and 40, and the ADCs 44 all require a frequency reference input to successfully perform their tasks, allowing the receiver 20 to lock on to a received signal and perform the necessary frequency conversions. A first local oscillator, i.e., phase-locked loop/frequency divider (PLL) 50 supplies the RF-to-IF mixer 32 with a reference frequency by phase-locking the output of the PLL 32 to a predetermined multiple of the frequency of a master reference signal 52 from a master reference frequency source 54. Similarly, second 56 and third 58 PLLs supply the IF-to-baseband mixers 38, 40 and the ADCs 44 with reference frequencies derived from the master reference signal 52, respectively. A ninety degree phase shifter 60 shifts the phase of the reference frequency output of the second PLL 56 by ninety degrees for use by the second IF-to-baseband mixer 40.

[0026] The master reference frequency source 54 is typically a voltage-controlled temperature-compensated crystal oscillator (VC-TCXO). The frequency of the master reference signal 52 is adjustable via a frequency control signal 62 from the DSP 28 in response to signal reception errors detected by the DSP 28.

[0027] FIG. 2 is a diagram showing digital in-phase (I) 72 and quadrature phase (Q) 74 signals output from a comparator (as discussed more fully below) and provided via the receive circuit 26 of FIG. 1 when the reference frequency provided by the master reference frequency source 54 of FIG. 1 has a negative error. The I and Q signals 72 and 74, respectively, have been converted to digital signals suitable for interfacing to digital logic circuits. The I and Q signals 72 and 74, respectively, have the phase relationship of the original baseband I and Q signals. The I signal 72 leads the Q signal 74 as is illustrated by the fact that a first rising edge 76 of the I signal 72 occurs just before a first rising edge 78 of the Q signal 74.

[0028] FIG. 3 is a diagram showing digital I 82 and Q signals 84 output from a comparator (as discussed more fully below) and provided via the receive circuit 26 of FIG. 1 when the reference frequency provided by the master reference frequency source 54 of FIG. 1 has a positive error. The I 82 and Q 84 signals have been converted to digital signals suitable for interfacing to digital logic circuits. The I and Q signals 82 and 84, respectively, have the phase relationship of the original baseband I and Q signals. The I signal 82 lags the Q signal 84 as is illustrated by the fact that a first rising edge 86 of the I signal 82 occurs just after a first rising edge 88 of the Q signal 84.

[0029] FIG. 4 is a block diagram showing the frequency error control system 100 for extracting and compensating for reference frequency error of the present invention implemented in a receiver 20′.

[0030] The receiver 20′ includes, from left to right, an antenna 22′, a duplexer 24′, a receive circuit 26′, and a digital signal processor 28′. A front end of the receive circuit 26′ includes, from left to right, an amplifier 30′, a radio frequency (RF)-to-intermediate frequency (IF) mixer 32′, a bandpass filter 34′, and an automatic gain control circuit (AGC) 36′. The output of the AGC 36′ is connected to a vector demodulator of the receive circuit that includes, from left to right, first 38′ and second 40′ IF-to-baseband mixers, lowpass filters 42′, and analog-to-digital converters (ADCs) 44′.

[0031] In operation, the antenna 22′ receives a transmitted RF signal that is routed through the duplexer 24′ and then input to the receive circuit 26′. In the receive circuit 26′, the received RF signal is amplified by the amplifier 30′ and then converted to an IF signal via the RF-to-IF mixer 32′. The resulting IF signal is filtered by the bandpass filter 34′ and output to the AGC 36′ where the gain of the signal is adjusted and input, in parallel, to the IF-to-baseband mixers 38′, 40′. The first 38′ and second 40′ IF-to-baseband mixers output in-phase (I) and quadrature (Q) signal components of the IF signal, respectively. The I and Q signals are then filtered by the lowpass filters 42′ and converted to digital signals 50′ via the ADCs 44′.

[0032] The RF-to-IF mixer 32′, the IF-to-baseband mixers 38′ and 40′, and the ADCs 44′ all require a frequency reference input to successfully perform their tasks, allowing the receiver 20′ to lock on to a received signal and perform the necessary frequency conversions. A first local oscillator, i.e., phase-locked loop/frequency divider (PLL) 50′ supplies the RF-to-IF mixer 32′ with a reference frequency by phase-locking the output of the PLL 32′ to a predetermined multiple of the frequency of a master reference signal 52′ from a master reference frequency source 54′. Similarly, second 56′ and third 58′ PLLs supply the IF-to-baseband mixers 38′, 40′ and the ADCs 44′ with reference frequencies derived from the master reference signal 52′, respectively. A ninety degree phase shifter 60′ shifts the phase of the reference frequency output of the second PLL 56′ by ninety degrees for use by the second IF-to-baseband mixer 40′.

[0033] The master reference frequency source 54′ is a voltage-controlled temperature-compensated crystal oscillator (VC-TCXO). The frequency of the master reference signal 52′ is adjustable via a frequency control signal 118 from the DSP 28′ in response to signal reception errors detected by the system 100.

[0034] The system 100 receives I and Q-inputs from the low pass filters 42′ corresponding to the outputs of the first mixer 38′ and the second mixer 40′, respectively. The system 100 extracts an error value based on a cumulative phase difference between the inputs and then outputs the reference frequency control signal 118′ to correct the frequency of the master reference frequency source 54′ in response to the error value.

[0035] Those skilled in the art will appreciate that the system 100′ may be implemented in the digital signal processor 28′ without departing from the scope of the present invention.

[0036] FIG. 5 is block diagram of the system 100 for extracting and compensating for reference frequency error of FIG. 4. The system 100 includes a first analog-to-digital converter (ADC) 102 and a second ADC 104 connected to a first edge-triggered J-K flip-flop 106 and a second edge-triggered J-K flip-flop 108. The outputs of the first 106 and second 108 J-K flip-flops are connected to an up-counter 110 and a down-counter 112, respectively. The outputs from the counters 110 and 112 are connected to the inputs of a subtractor 114 whose output is connected to the input of a frequency error control circuit 116 that outputs the reference frequency control signal 118.

[0037] In operation, the first ADC 102 receives the analog I-signal output of the first mixer 38 of FIG. 1 after filtering by the lowpass filter 42 of FIG. 1. The first ADC 102 converts the analog I-signal to a digital signal suitable for driving digital circuitry such as the J-K flip-flops 106 and 108. The first ADC 102 is implemented with a bistable comparator that compares the input analog I-signal to a threshold thereby quantizing the value into a high voltage state or a low voltage state depending on the result of the comparison. Those skilled in the art will appreciate that the ADC 102 may be implemented with a different type of analog-to-digital converter without departing from the scope of the present invention.

[0038] Similarily, the second ADC 104 receives the analog Q-signal output of the second mixer 40 of FIG. 1 after filtering by the lowpass filter 42 of FIG. 1. The second ADC 104 converts the analog Q-signal to a digital signal suitable for driving digital circuitry such as the J-K flip-flops 106 and 108. The second ADC 104 is implemented with a bistable comparator that compares the input analog Q-signal to a threshold thereby quantizing the value into a high voltage state or a low voltage state depending on the result of the comparison. Those skilled in the art will appreciate that the ADC 104 may be implemented with a different type of analog-to-digital converter without departing from the scope of the present invention.

[0039] The digital I-signal output from the ADC 102 is connected, in parallel, to a J-input 120 of the first J-K flip-flop, and to a clock input 122 of the second J-K flip-flop 108. The digital Q-signal output from the second ADC 104 is connected, in parallel, to a J-input 121 of the second J-K flip-flop 108 and to a clock input 124 of the first J-K flip-flop 106. A K-input 128 of the first J-K flip-flop 106 and a K-input 132 of the second J-K flip-flop 108 are connected to a high voltage source (V_cc) such as five volts, i.e., are tied high. The complimentary outputs 126 and 130 remain unconnected, i.e., as open circuits, while the K-inputs 128 and 132 remain connected to the high voltage source (see FIG. 7). An up-count Q-output 134 of the first J-K flip-flop 134 is connected to the input of the up-counter 110 and a down-count Q-output 136 of the second J-K flip-flop 108 is connected to the input of the down-counter 112.

[0040] The novel design of the present invention is facilitated by the fact that when I signal lags the Q signal, a positive reference frequency error is indicated. Similarly, a negative frequency error in the reference frequency signal causes the I-signal to lead the Q-signal.

[0041] In the following discussion, the term previous state refers to the state of the J-input of a J-K flip-flop before the J-K flip-flop is clocked by a signal to its clock input. The transition function of the J-K flip-flops 106 and 108 is illustrated in the following table where a 0 corresponds to a low state, and a 1 corresponds to a high state.

[0042] The table illustrates that, for example, in the last column, when the J and K inputs of the J-K flip-flops 106 or 108 are high (1 1), and the previous state of the Q-output was low (0), the Q-output will toggle to high (1). Note that only the second (0 1) and third (1 1) columns of data are applicable to the J-K flip-flops 106 and 108 because the K-inputs 128 and 132, respectively, remain high.

[0043] The J-K flip-flops 106 and 108 are rising-edge triggered flip-flops, meaning that the flip-flops 106 and 108 are clocked when their clock inputs 124 and 122, respectively, transition from low to high.

[0044] With reference to FIG. 2, when the I-signal 72 leads the Q-signal 74, the first rising-edge 76 of the I-signal 72 clocks the second J-K flip-flop 108. The down-count output 136 of the J-K flip-flop 108 transitions to a high state in response to the low state of the Q-signal 74 (see the last column (1 1) in Table 1). The high state of the down-count output 136 triggers the down-counter 112, which increments a negative error count in response to the high state. Simultaneously, the up-count output 134 of the first J-K flip-flop 106 remains low (see the second column of data (0 1) in Table 1). Hence, when the I-signal 72 leads the Q-signal 74, the up-count output 134 remains low while down-count output 136 toggles.

[0045] With reference to FIG. 3, when the I-signal 82 lags the Q-signal 84, the first rising-edge 88 of the Q-signal 82 clocks the first J-K flip-flop 106. The up-count output 134 of the first J-K flip-flop 106 transitions to a high state in response to the previous low state of the I-signal 82 (see the last column (1 1) in Table 1). The high state of the up-count output 134 triggers the up-counter 110, which increments a positive error count in response to the high state. Simultaneously, the down-count output 136 of the second J-K flip-flop 108 remains low (see the second column of data (0 1) in Table 1). Hence, when the I-signal 82 lags the Q-signal 84, the up-count output 134 toggles while down-count output 136 remains low.

[0046] The up-counter 110 and the down-counter 112 accumulate totals of the instances of positive reference frequency error and the instances of negative reference frequency error, respectively. These totals are output to the subtractor 114. The subtractor 114 takes a difference between the totals to obtain a signal representation 138 of the direction of and the amount of error in the reference frequency. This error signal 138 is output to the frequency control circuit 116 where the signal 138 is adjusted to provide the control signal 118. The required adjustments to the error signal 138 vary depending on the type of master reference frequency source (see 54 of FIG. 1) used and may include signal gain adjustments. The control signal 118 is provided to the master reference frequency source 54 of FIG. 1 where it corrects the output reference frequency in response to the magnitude of the error signal 138.

[0047] The up-counter 110 and the down-counter 112 are periodically activated by a programmable gating control circuit, 140. The gating control circuit 140 controls the period of activation, i.e., gating period (T_gate) of the counters 110 and 112. At the end of a predetermined gating time interval, the up-counts and down-counts of the up-counter 110 and the down-counter 112, respectively, are re-set to zero via the programmable gating control circuit 140. The gating control circuit 140 is easily implemented with a programmable timer that periodically issues a clear signal for a predetermined duration to the counters 110 at a programmed time interval. The predetermined duration and the time interval, i.e, T_gate, are dependent upon the application in which the system 100 is used.

[0048] The construction of the individual ADCs 102 and 104, J-K flip-flops 106 and 108, counters 110 and 112, and error control circuit 116 are well known in the art. ←

[0049] FIG. 6 is a more detailed diagram of the system 100 of FIG. 5. In the present specific embodiment, the first ADC 102 is implemented as a comparator circuit employing a first Schmitt trigger 156. The first Schmitt trigger 156 is accompanied by a gain circuit having a first resistor (R₁) 150 with one end connected to the analog input I-signal and the opposite end connected to the negative terminal of a first operational amplifier 152. The negative terminal of the first operational amplifier 152 is connected to one end of a second resistor (R₂) 154. The opposite end of the second resistor 154 is connected to the output of the operational amplifier 152. The output of the operational amplifier 152 is fed to the Schmitt trigger 156 and then input one end of a third resistor (R₃) 158. The opposite end of the third resistor 158 provides a digital I-output signal as the output of the first ADC 102.

[0050] Similarly, the second ADC 104 is implemented as a comparator circuit employing a second Schmitt trigger 166. The Schmitt trigger 166 is preceded by a gain circuit having a fourth resistor (R₄) 160 with one end connected to the analog input Q-signal and the opposite end connected to the negative terminal of a second operational amplifier 162. The negative terminal of the second operational amplifier 162 is connected to one end of a fifth resistor (R₅) 164. The opposite end of the fifth resistor 164 is connected to the output of the operational amplifier 162. The output of the operational amplifier 162 is fed to the second Schmitt trigger 166 and then input one end of a sixth resistor (R₆) 168. The opposite end of the sixth resistor 168 provides a digital Q-output signal as the output of the second ADC 104.

[0051] The positive terminals of the first 152 and second 162 operational amplifiers are fed by a voltage divider having a reference voltage (V_ref) 170, a seventh resistor (R₇) 172, and an eighth resistor (R₈) 174. The eighth resistor 174 is connected at one end to ground, i.e., 0 volts. The other end of the eighth resistor is connected, in parallel, to one end of the seventh resistor 172 and to the positive terminals of the first 152 and second 162 operational amplifiers. The other end of the seventh resistor 172 is connected to the positive terminal of the reference voltage 170.

[0052] In the present embodiment, R₁=R₄=100 kΩ, R₂=R₅=490 kΩ, R₃=R₅=10 kΩ, R₇=33 kΩ, and R₈=10 kΩ. The first 152 and second 162 operational amplifiers are {fraction (1/2 )} LM258 operational amplifiers. The first 156 and second 166 Schmitt triggers are {fraction (1/6 )} 74ACT14 Schmitt triggers. The J-K flip-flops 106 and 108, are implemented with a SN74LS73AN edge triggered flip-flop module.

[0053] By analyzing the transfer characteristics of the first 102 and second 104 ADCs, those skilled in the art will appreciate that the ADCs 102 and 104 are comparator circuits with high and low threshold voltages. Hysteresis characteristics, i.e., the difference between the high and low threshold voltages of the ADCs 102 and 104 are designed to limit the effects of noise on the output of the ADCs 102 and 104.

[0054] When the input waveform, i.e., the analog I-input and/or the analog Q-input voltages reach the high voltage threshold, the output of the ADC 102 and/or 104 transitions to a high state. When the input waveform reaches the low voltage threshold, the output of the ADC 102 and/or 104 transitions to a low state.

[0055] Those skilled in the art will appreciate that the high and low threshold voltages may be equal without departing from the scope of the present invention. Also, the resistors R1 though R8 may be replaced with circuit elements having different impedences. In addition, the ADCs 102 and/or 104 may be implemented with another type of circuit without departing from the scope of the present invention.

[0056] For telecommunications applications employing FM (frequency modulation) modulation, the gating times of the up-counter 110 and down-counter 112 place restraints on the bit size of the counters 110 and 112. In the present specific embodiment, the counters 110 and 112 are 16-bit counters.

[0057] For a carrier frequency of 300 Hz, adequate voice accommodation requires that the system 100 has a gating period larger than approximately 10 milliseconds. The gating period for the system 100 is chosen to be approximately 40 milliseconds.

[0058] The maximum number signal of cycles N_max, i.e., the maximum number of cycles of the analog and/or digital I and/or Q signals within a time interval T_gate, where T_gateis the gating period of the system 100 is:

[0059] N_max=T_gate×2π(ΔF)(1+π/2(Offest))  [1]

[0060] Where Offset is the fixed DC frequency offset of the carrier wave and ((Offset)²<<1); ΔF is the peak FM deviation of the carrier wave. The frequency resolution of the system 100 is 2/T_gate. Methods for achieving the appropriate gating period are well known in the art.

[0061] Equation [1] may then be used to verify the applicability of the particular implementation to a particular application. Using equation [1], for example, and assuming, for a particular application T_gate=0.04 seconds, ΔF=10,000 Hz, Offset=5,000 Hz, then N_max=4487 cycles. The counters 110 and 112 are 16-bit counters and therefore have maximum counts of 64,000. Thus the counters 110 and 112 can easily handle 4487 cycles and are sufficient for the particular application.

[0062] FIG. 7 is a diagram of a SN74LS73AN J-K flip flop module 180 adapted for use with the system 100 of FIG. 5. The module 180 implements the J-K flip-flops 106 and 108 of FIG. 5. A high voltage source (V_cc) is input to one end of a resistor 184, the opposite end of which is connected, in parallel to one end of a capacitor 186 the other end of which is connected to ground, first 188 and second clear-inputs 190 (Clr₁and Clr₂) and first 192 and second 194 K-inputs (K₁and K₂), and a module voltage input 196 (V_cc). A first complimentary output ({overscore (Q)}₁) 198 and a second complimentary output ({overscore (Q)}₂) 200 are left unconnected. A first output (Q₁) 202 is input to the up-counter 110 of FIG. 5 and a second output (Q₂) is input to the down-counter 112 of FIG. 5. The analog I-signal is input, in parallel, to a first J-input (J₁) 206 and a second clock input (Clk₂) 208. The analog Q-signal is input, in parallel, to a second J-input (J₂) 210 and a first clock input (Clk₁) 212.

[0063] In the present embodiment, the capacitance of the capacitor 186 is approximately 0.01 micro Farads and the resistance of the resistor 184 is approximately 50 Ohms. The capacitor 186 helps to remove any alternating current (AC) component of the high voltage 182. The resistor 184 is optional.

[0064] Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof

[0065] It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.

[0066] Accordingly,