Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness

[0001] This invention relates to methods of forming thinner silicon structures with precisely defined thicknesses in a thin silicon substrate, and more particularly to subtractive methods of precisely thinning selected portions of a silicon structure to form recesses with various precise depths in the surface of the thin silicon substrate into which recesses various devices including MOSFETS, resistors, capacitors and diodes can be formed.

[0002] This invention provides a method for forming a structure with a precision recessed gate structure for an Ultra Thin (UT) Silicon-On-Insulator (SOI) device comprising a thin layer of doped silicon formed on the surface of a Buried OXide (BOX) layer. The method can also be used for precision thinning of selected regions of the top silicon layer on a SOI (SOI) wafer. This can be used to provide an optimal silicon thickness for each type of electronic device which is to be formed on the same wafer. For example, MOSFETS require thinner silicon than resistors or capacitors or diodes in order to achieve the best electrical characteristics.

[0003] Scaling of SOI devices can be limited by the ability to thin the silicon. The silicon thickness must be thinned to achieve device performance targets, but simultaneously the silicide used to contact the source/drain region must be prevented from consuming the entire thickness of the silicon and as a result contacting the BOX layer. This is a significant problem because source/drain contact resistance increases very rapid as the silicide layer approaches the BOX layer.

[0004] FIGS. 1A and 1B illustrates a possible approach to forming a raised source/drain structure that employs the option of forming raised source regions and drain regions (above the SOI structure) juxtaposed with the gate electrode stack of the MOSFET device by deposition of additional silicon adjacent to the gate electrode stack after formation thereof.

[0005] In FIG. 1A, a MOSFET device 10 is shown in an intermediate stage of manufacture. The substrate 12 comprises a BOX layer upon which a thin doped silicon layer 14 has been formed to serve as the doped region in which the source/drain and channel of an FET device are to be formed. Above the center of the silicon layer 14, a gate electrode stack comprising a gate oxide layer GOX, a polysilicon gate G and a silicide layer SCD have been patterned followed by formation of sidewall spacers on the sidewalls of the gate electrode stack ST.

[0006] FIG. 1B shows the device 10 after the exposed surfaces of the thin silicon layer aside from the spacers SP has been coated with a thin epitaxial silicon layer 16 to form what will later be employed as raised source/drain regions by additional processing steps as will be well understood by those skilled in the art.

[0007] The method of FIGS. 1A and 1B has significant issues with the selective epitaxy necessary to form the raised source drain. In the selective epitaxy process, silicon is deposited selectively only on exposed silicon surfaces and not on dielectric surfaces such as silicon dioxide isolation regions and silicon nitride spacers. This process is difficult to control because it relies on the balance between silicon deposition and etching in a chemical vapor deposition reactor. Even when acceptable deposition rates on silicon are achieved while simultaneously getting no significant deposition on the dielectric surfaces, the shapes of corners and edges of the silicon surfaces can be changed because of variations in the silicon growth/etch rates with crystallographic orientation. This leads to faceting of these edges resulting in unacceptable device structures. The process is also very sensitive to surface contamination and prior processing conditions during such commonly used process steps as ion implantation, reactive ion etching and wet chemical cleans and etches. The deposition rates are also affected by dopant species and concentration in the silicon surface layers. This can lead to different deposition thicknesses on nFETs and pFETs which is generally undesirable.

[0008] Another option is recessing the gate. Such an approach is described by Morimoto et al. U.S. Pat. No. 6,492,696 entitled “Semiconductor Device And Process Of Manufacturing The Same”. Morimoto et al. describes use of a LOCOS process to form a recess of a controlled thickness. A LOCOS film is formed on the surface of exposed areas on the surface of a silicon layer of an SOI substrate. Then the LOCOS film is etched away, leaving a thinner channel region (a recessed channel region) where the LOCOS film has been etched away. Next, a metal film is formed on the entire surface of the substrate to form a silicide film. Since this method utilizes the SOI substrate by adjusting the thickness of the surface silicon layer, the depth of a source/drain region can be controlled, so a source/drain region of relatively large depth can be formed by a common step for forming the source/drain region. This LOCOS recessing process is problematic due to the control necessary in defining the silicon thickness below the gate electrode stack.

[0009] An object of this invention is to provide a method of forming a precision recessed gate structure using selective Reactive Ion Etching (RIE) of regions in the silicon.

[0010] In accordance with this invention, a method is provided for forming precision recessed structure such as a gate structure by the process of forming an amorphized region in a SOI silicon layer by ion implantation into the too surface of the SOI silicon layer. The following step is selective Reactive Ion Etching (RIE) of the amorphized region in the silicon to form the recess therein.

[0015] The process flow of one embodiment of this invention, which is employed to form a recessed gate MOSFET is described below with reference to FIGS. 2A-2M. In accordance with the method of FIGS. 2A-2M, the structure of an MOSFET device 20 is defined in part by production of a precisely controlled gate recess 38 shown in FIG. 2C formed by the selective reactive ion etching of amorphized silicon formed by ion implantation.

Form Masking Layers Over Silicon-on-Insulator (SOI) Layer

[0016] Starting in FIG. 2A, the MOSFET device 20 is shown in an early stage of manufacture. The substrate which has a planar upper surface comprises a BOX layer 22 formed on a wafer (not shown for convenience of illustration). Above the BOX layer 22, a conformal, planar, thin, p-doped, crystalline silicon layer 24 with top and bottom surfaces has been formed to serve as the doped region in which the source/drain and channel of an FET device is to be formed. As will be well understood by those skilled in the art, the silicon layer 24 is lightly p-type doped before the start of processing. After the BOX layer 22 is formed and after the isolation processing (which is not discussed herein but which will be well understood by those skilled in the art), the nFET regions get a p-well implant and the pFET regions get a n-well implant to form p- and -doped regions respectively, as will also be well understood by those skilled in the art.

[0017] Above the thin doped, crystalline silicon layer 24, a conformal, planar, hard mask layer 28 which can be silicon oxide has been formed and coated with a silicon nitride layer 30 which is a thin layer that is also sacrificial. A photoresist (PR) mask 32 with a gate opening 33 therethrough has been formed over the silicon nitride (nitride) cap layer 30 above the center of the device 20. The mask 32 was formed by applying photoresist and exposing it using conventional photolithographic techniques. The photoresist mask 32 has been employed to etch a gate window 34 through the nitride layer 30 and the hard mask layer 28 down to the surface of the thin, doped, crystalline silicon layer 24.

Amorphize Exposed Area of Silicon-on-Insulator Layer

[0018] In FIG. 2B, the device 20 of FIG. 2A is shown after ion implanting ions 36I through the window 34 into the surface of the thin doped, crystalline silicon layer 24 amorphizing a specific thickness of the exposed portion of the thin, doped crystalline silicon layer 24 reaching down from the top surface of crystalline silicon layer 24 to a shallow depth well above bottom surface of crystalline silicon layer 24 and well above the top surface of the BOX layer 22. The thickness of the amorphized silicon layer 36 in the surface of the crystalline silicon layer 24 can be precisely tailored by changing the ion energy, dose or ion species of the ions 36I during performance of the ion implantation process. The preferred ions 36I are silicon or germanium. The implant is masked using a material for the hard mask layer 28, such as silicon dioxide, silicon nitride or silicon oxynitride or a combination of these films which has been patterned using conventional lithography. If the structure to be built is a recessed channel MOSFET, the hard mask layer 28 and the can nitride layer 30 will also act as the mandrel on which temporary or disposable spacers are formed. The thickness of the amorphous layer is determined by the energy of the implantation procedure. For example, TABLE I shows the amorphous layer thickness for several energies of germanium ions implanted to a dose of 5.0×10¹⁴ ions/cm2. As is shown by FIG. 2B, the thickness of the amorphized silicon layer 36 is a fraction of the thickness of the crystalline silicon layer 24, leaving the lower portion of the crystalline silicon layer 24 in its original condition as doped, crystalline silicon. Beneath the amorphized silicon layer 36 is a thinner region 66 of the crystalline silicon layer 24, whereas aside from the amorphized silicon layer 36 are thicker regions 64 of the crystalline silicon layer 24, since they have not been amorphized.

[0019]

	TABLE I
	Energy (Kev)	Thickness (nm)
	10	19.0
	15	24.0
	20	28.5
	25	32.0
	30	38.0
	35	42.5
	40	49.3

Strip Photoresist Mask

[0020] In FIG. 2C, the device 20 of FIG. 2B is shown after the preliminary steps of stripping away the photoresist mask 32 which removes the upper portion of the gate window 34, leaving a lower gate window 34′ through the cap nitride layer 30 and the hard mask layer 28 down to the ton of the amorphized silicon layer 36.

Form Recess in Silicon-on-Insulator Layer with Selective Etch

[0021] Referring again to FIG. 2C, the next step is a selective reactive ion etch (RIE) of the amorphized silicon layer 36 through the gate window 34′ that has formed the recess 38. The conditions used for this etch must be such that the differential etch rate of the amorphous silicon is approximately three (3) times greater than that of thin, doped crystalline silicon layer 24. The differential etch rate provides a self-limiting etch which when combined with an interferometric endpoint system and the low etch rate allows the etch to precisely stop at the boundary between the implant damaged layer 36 and the thin crystalline silicon layer 24 therebelow and juxtaposed therewith laterally. The result is that gate window 34′ has been expanded into a deeper gate window 34′ that reaches down from the top surf of silicon layer 24 to the newly exposed surface of the thin doped silicon p-crystalline layer 24 at the bottom of the recess 38, newly exposed surface is well above the bottom surface of layer 24. A selective, low etch rate silicon etching process that can be used is based on using a mixture of hydrogen bromide (HBr) vapor with oxygen (O₂) gas in a diluent gas done in a decoupled plasma reactor, which is a dry etching process. The operation regime employs a pressure range of 20-60 mT (milli-Torr); hydrogen bromide (HBr) vapor HBr flow in the range of 150-300 sccm and oxygen (O₂) flow 4-10 sccm. Helium is used as the diluent gas. The key to success of this dry etching process is the use of low bias power. The interferometric endpoint system is used to stop the dry etching process, precisely, just after the desired silicon thickness has been etched.

Temporary Sidewall Spacer Formation

[0022] FIG. 2D shows the device 20 of FIG. 2C after temporary (disposable) sidewall spacers 40 have been formed in the gate window 34′ reaching from the bottom of the recess 38 on the exposed surface of silicon layer 24 up alongside the sidewalls of the gate window 34′ in silicon layer 24, the mask layer 28 and the cap nitride layer 30. Silicon nitride, silicon dioxide, silicon oxynitrides or combinations of these films can be used to form the temporary sidewall spacers 40 by CVD, PECYD or other deposition techniques.

[0023] The following step is to etch back the temporary spacers 40 partially by directional Reactive Ion Etching (RIE) to produce the configuration shown in FIG. 2D leaving the bottom of the recess 38 open down to the surface of the silicon recess 38 in the center of the gate window 34′. The width of temporary sidewall spacers 40 after etching should be from 10 nm to 75 nm. As a result, spacers 40 taper outwardly from the bottom to the top, being wider at the bottom of the gate window 34′ and narrowing down to a point near the top of the gate window 34′.

Gate Oxide Formation

[0024] FIG. 2E shows the device 20 of FIG. 2D after formation of a gate oxide layer 42 on the surface of the silicon recess 38 in the center of the gate widow 34′ at the bottom of the silicon recess 38, spaced far above the bottom surface of crystalline silicon layer 24. The gate oxide layer 42 can be a thermally grown silicon oxide or an oxynitride, with or without a pre-growth or post-growth nitridization treatment such as nitrogen ion implantation or plasma treatment. Post nitrogen treatment or post growth annealing can also be done. An alternative gate dielectric may be deposited such as a high permittivity (high-K) insulator by various techniques such as Atomic Layer Deposition (ALD) or CVD. Various pre-deposition and post-deposition treatments as described above for thermally grown silicon oxides can be applied to the high-K films also. Examples of high-K materials suitable for this application are HfO₂, ZrO₂, Ta₂ O₂, SrTiO₃ and LaAlO₃.

Formation of Gate Electrode

[0025] FIG. 2F shows the device 20 of FIG. 2E after formation of the gate electrode 44 by deposition of polysilicon into the gate window 34′ covering the gate oxide layer 42 and filling the space defined by the temporary sidewall spacers 40. The gate electrode 44, which is shown in a cross sectional view, has an inverted trapezoidal shape with curved sidewall which is narrower at the bottom than the top, with the curved sidewalls conforming to the temporary sidewall spacers 40.

Planarization of Gate Polysilicon

[0026] FIG. 2F also shows the device after planarization of the top of the polysilicon, gate electrode 44 down to the level of the cap layer 30 by the well known process of Chemical-Mechanical Polishing (CMP).

Removal of the Mandrel Material

[0027] FIG. 2G shows the device 20 of FIG. 2F after removal of the mandrel material comprising the cap layer 30 and the hard mask 28 leaving the gate stack ST of the gate electrode 44 and the gate oxide 42 bordered by the temporary sidewall spacers 40 alone in the center of the doped, thin crystalline silicon layer 24. The cap layer 30 and the hard mask 28 were removed by a conventional selective etching process.

Removal of Spacers

[0028] FIG. 2H shows the device 20 of FIG. 2G after removal of the temporary sidewall spacers 40 exposing the sidewalls of the gate stack ST (i.e. the sidewalls of the gate electrode 44 and the sidewalls of the gate oxide 42). Thus the gate stack ST has its base supported on the bottom surface of the recess 38. FIG. 2H shows that gate stack ST extends from the bottom surface of recess 38, where it is based, and above the ton surface of thin crystalline silicon layer 24. Moreover, the gate stack ST is located in the center of the recess 38 with a gap between the outer sidewalls of the recess 38 in the surface of the thin crystalline silicon layer 24 and the lateral walls of the gate oxide layer 42 and the lower outer edges of the gate electrode 44. Because the gate stack ST is based on the bottom of the recess 38, it is spaced far above the thin crystalline silicon layer 24 by the precise silicon thickness as described above with respect to FIG. 2C.

Gate Electrode Reoxidation

[0029] FIG. 21 shows the device 20 of FIG. 2H after growth of a thin thermal oxide layer 46 on the exposed top and sidewall surfaces of the gate electrode 44, which preferably has a thickness of from about 1 nm to about 5 nm.

Form nFET Extension/Halo Mask

[0030] Form a photolithographic mask to cover all areas except where the nFET devices are to be formed.

Implant nFET Extensions

[0031] FIG. 2J shows the device 20 of FIG. 21 after a shallow nFET extension implant in the top surface of the thin crystalline silicon layer 24 with dopant 48I to form N− dopant regions 48 in the thin crystalline silicon layer 24 aside from that gate oxide layer 42 including the depressed regions of the recess 38 in the top surface of the thin crystalline silicon layer 24 including the top surface of recess 38, above the bottom surface of the thin crystalline silicon layer 24 and the top surface of the BOX layer 22.

[0032]

	TABLE II
	nFET	Extension Implant
		Low energy
	Dopant	Arsenic
	Energy	0.5 to 15 Kev
	Dose	2E14/cm2 to 2E15/cm2
	Angle	0 to 10 degrees C.

Perform nFET Halo Implant

[0033] Then an nFET halo implant is performed using either boron or BF₂ in accordance with the parameters of either TABLE IIIA or TABLE IIIB to form p-doped halo regions (not shown) as will be well understood by those skilled in the art.

[0034]

	TABLE IIIA
	nFET	Halo Implant
	Dopant	Boron
	Energy	5 to 50 Kev
	Dose	2E13/cm2 to 2E14/cm2
	Angle	0 to 45 degrees

[0035]

	TABLE IIIB
	nFET	Halo Implant
	Dopant	BF2
	Energy	10 to 70 Kev;
	Dose	2E13/cm2 to 2E14/cm2
	Angle	0 to 45 degrees

Strip nFET Photoresist Mask

[0036] Then the nFET extension/halo mask is stripped away to prepare for the pFET implant process

Form pFET Extension/Halo Mask

[0037] Form a photolithographic mask to cover all areas except where the pFET devices are to be formed. While these areas are not shown, since the features of the invention have been illustrated with respect to the nFET devices, the process is performed analogously as will be well understood by those skilled in the art.

Implant pFET Extensions

[0038] Perform a pFET extension implant with boron or BF₂ dopant in accordance with the parameters of either TABLE IVA or TABLE IVB below to form p-dopant regions (not shown) in the silicon layer 24 aside from the pFET gate oxide layer (not shown) of the pFET devices (not shown) including the depressed regions of the pFET recesses (not shown).

[0039]

	TABLE IVA
	pFET	Extension Implant
	Dopant	Boron
	Energy	0.2 to 10 Kev
	Dose	2E14/cm2 to 2E15/cm2
	Angle	0 to 10 degrees

[0040]

	TABLE IVB
	pFET	Extension Implant
	Dopant	BF2
	Energy	1 to 30 Kev
	Dose	2E14/cm2 to 2E15/cm2
	Angle	0 to 10 degrees

Perform pFET Halo Implant

[0041] Then an pFET halo implant is performed in accordance with the parameters of either TABLE V to form p-doped halo regions (not shown) as will be well understood by those skilled in the art.

[0042]

	TABLE V
	pFET	Halo Implant
	Dopant	Arsenic
	Energy	20 to 100 Kev
	Dose	2E13/cm2 to 2E15/cm2
	Angle	0 to 45 degrees

Strip pFET Photoresist Mask

[0043] Then the pFET extension/halo mask is stripped away to prepare for Source/Drain formation process.

Form Source/Drain Spacers

[0044] FIG. 2K shows the device 20 of FIG. 2J after formation of the source/drain sidewall spacers 48 aside from the gate electrode stack ST on the sidewalls thereof. The sidewall spacers 48 are formed of an FET spacer material such as silicon nitride, silicon dioxide, silicon oxynitrides or a combination of these films. The sidewall spacers 48 can be formed by CVD, PECVD or other deposition techniques followed by directional RIE. The spacer width of the sidewall spacers 48 after etching should be from about 15 nm to about 80 nm.

Form nFET Source/Drain Mask

[0045] Form a photolithography to mask all areas except where the nFETs such as source/drain regions 52 in FIG. 2L are being formed.

Perform nFET Source/Drain Implant

[0046] FIG. 2L shows the device 20 of FIG. 2K during the next step of performing an nFET source/drain implant using the parameters in Table VIA or VIB below or a combination of the two forming the source/drain regions 52 in the top surface of the thin crystalline silicon layer 24 aside from the source/drain sidewall spacers 48 with the source/drain region 52 being located far above the bottom surface of the thin crystalline silicon layer 24 and the to surface of the BOX layer 22.

[0047]

	TABLE VIA
	nFET	Source/Drain Implant
	Dopant	Arsenic
	Energy	5 to 50 Kev
	Dose	1E15/cm2 to 1E16/cm2
	Angle	0 to 10 degrees

[0048]

	TABLE VIB
	nFET	Source/Drain Implant
	Dopant	Phosphorous
	Energy	2 to 20 Kev
	Dose	1E15/cm2 to 1E16/cm2
	Angle	0 to 10 degrees

Strip nFET Source/Drain Mask

[0049] Next the nFET source/drain mask is stripped.

Form pFET Source/Drain Mask

[0050] Form a photolithography to mask all areas except where the pFETs are being formed.

Perform pFET Source/Drain Implant

[0051] The next step is to perform a pFET source/drain implant using the parameters in Table VIIA or VIIB below.

[0052]

	TABLE VIIA
	pFET	Source/Drain Implant
	Dopant	Boron
	Energy	3 to 15 Kev
	Dose	1E15/cm2 to 1E16/cm2
	Angle	0 to 10 degrees

[0053]

	TABLE VIIB
	pFET	Source/Drain Implant
	Dopant	BF2
	Energy	10 to 50 Kev
	Dose	1E15/cm2 to 1E16/cm2
	Angle	0 to 10 degrees

Photoresist Strip

[0054] Next the nFET source/drain mask is stripped

Perform Source/Drain Anneal

[0055]

	TABLE VIIIA
	Source/Drain Anneal	Rapid Thermal Anneal (RTA)
	Temperature	800 to 1100 degrees C.
	Time	0 to 60 seconds

[0056]

	TABLE VIIIB
	Source/Drain Anneal	Conventional Anneal
	Temperature	850 to 1000 degrees C.
	Time	2 to 30 minutes

Silicide Formation

[0057] FIG. 2M shows the device 20 of FIG. 2L after formation of self-aligned silicide layer 54 on the source/drain 52 and polysilicon gate surfaces. Titanium, Cobalt, Nickel or other metals can be used to form the suicide.

[0058] The basic MOSFET transistors are now formed.

[0059] Any one of many contact and metallization schemes known to those skilled in the art of integrated circuit processing can now be used to produce the complete integrated circuit chip.

Precision Thinning of Selected Region of SOI Wafers

[0060] The process flow of a second embodiment of this invention, which is employed to perform thinning of selected regions of SOI wafers is described below with reference to FIGS. 3A-3C. In accordance with the method of FIGS. 3A-3C, the structure of a device 60, e.g. a semiconductor chip, is defined in part by production of a precisely controlled gate recess 38 shown in FIG. 3C formed by the selective reactive ion etching of amorphized silicon formed by ion implantation.

[0061] The precision thinning method described above can also be used to produce multiple thicknesses of silicon 24 on buried silicon oxide (BOX) layer 22, i.e. SOI wafers, so that various electronic devices on the same device 60 can built with the optimal thickness for each device. A process flow for this structure is described below with reference to FIGS. 3A-3C.

Amorphize Silicon Thickness in Selected Areas

[0062] FIG. 3A shows an SOI device 60, which comprises a BOX layer 22 on which a thin crystalline silicon layer 24 has been formed. A photoresist mask 32 has been formed on the left side of the device 60 leaving surface of the silicon layer 24 on the right side exposed. The photoresist mask 32 is formed by applying photoresist and exposing it using conventional photolithographic techniques. In FIG. 3A, the exposed portion of the crystalline silicon layer 24 is shown being amorphized by the process of ion implantation of ions 36I as described above to form an amorphous silicon layer 36 in the ton surface of the right side of the SOI device 60, aside from the mask 32 leaving a thinner crystalline silicon layer 66 below the amorphous silicon layer 36. A thicker crystalline silicon layer 64 remains below the photoresist mask 32.

[0063] FIG. 3B shows the SOI device 60 of FIG. 3A after a selective Reactive Ion Etch (RIE) for removal of the amorphized layer 36 has been performed using the conditions described above to form a recess 38 with a controlled depth, as described above. The result of removal of the amorphized layer 36 is that the top surface of thinner crystalline silicon layer 66 is exposed where the recess 38 has been formed. An undercut of the recess 38 below a portion of the photoresist mask 32 is shown as will be well understood by those skilled in the art of the selective RIE process.

[0064] FIG. 3C shows the device of FIG. 3B after the photoresist mask 32 has been stripped away from above the thicker crystalline silicon layer 64 leaving the SOI device 60 with the thinner crystalline silicon layer 66 exposed below the recess 38 and the thicker crystalline silicon layer 64 exposed aside from the recess 38.

[0065] As stated above, with reference to FIGS. 3A-3C. use is made of conventional microelectronic processing methods to form various electronic devices in the regions of silicon thinned to the optimal thickness for each type of device. As state above, this invention provides a method for forming a structure with a precision recessed gate structure for an Ultra Thin (UT) silicon SOI device comprising a thin layer of doped silicon formed on the surface of a Buried OXide (BOX) layer. The method can also be used for precision thinning of selected regions of the top silicon layer on a Silicon-On-Insulator (SOI) wafer. This can be used to provide an optimal silicon thickness for each type of electronic device which is to be formed on the same wafer. For example, MOSFETS require thinner silicon than resistors or capacitors or diodes in order to achieve the best electrical characteristics. Also, as stated above, with reference to FIGS 3A-3C the precision thinning method described above can also be used to produce multiple thicknesses of silicon 24 on buried silicon oxide (BOX) layer 22, i.e. SOI wafers, so that various electronic devices on the same device 60 can built with the optimal thickness for each device.

[0066] While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.