Process of fabricating semiconductor device having low-resistive contact without high temperature heat treatment

[0002] This invention relates to a process of fabricating a semiconductor device and, more particularly, to a process of fabricating a semiconductor device with a low-resistive contact without a high temperature heat treatment.

[0003] In order to form a low-resistivity contact with a semiconductor substrate in a contact hole, refractory metal film is deposited so as to cover the contact area of the semiconductor substrate, and the refractory metal reacts with the semiconductor through a heat-treatment so as to produce a refractory metal silicide layer. Titanium is attractive, because the titanium forms a low Schottky barrier together with any one of the p-type semiconductors and the n-type semiconductors. Moreover, the titanium easily reduces natural oxide unavoidably covering the contact area, and the silicidation smoothly proceeds.

[0004] An experiment is reported by Akihiro Sakamoto et al in “Lower Thickness Limit of Ti Film in BLK-W Contact”, Proceedings of 38th. Spring Conference of Applied Physics Society, 30p-W-7. According to the paper, a titanium film was deposited form 5 nanometers to 40 nanometers thick on a single crystal silicon substrate, and was annealed at 800 degrees centigrade for 30 seconds. Sakamoto et. al. taught that the contact resistance was drastically increased when the titanium film was equal to or less than 10 nanometers thick.

[0005] A process of forming a metal-semiconductor ohmic contact is disclosed in Japanese Patent Publication of Unexamined Application No. 4-215424. According to the Japanese Patent Publication of Unexamined Application, arsenic was ion implanted into a semiconductor layer so as to make the semiconductor layer amorphous, and titanium was deposited to 100 nanometers thick on the amorphous semiconductor layer. The titanium layer was annealed at a low temperature equal to or less than 500 degrees centigrade.

[0006] The first prior art ohmic contact disclosed in the paper encounters a problem in high contact resistance, because the ohmic contact is formed with the single crystal silicon. The high temperature annealing is another problem. The high temperature annealing causes the dopant impurity to be diffused into the silicon substrate, and destroys the impurity profile.

[0007] The impurity profile is less affected in the second prior art process, because the titanium layer is annealed at the relatively low temperature. However, the amorphous silicon layer requires the thick titanium layer of 100 nanometers thick, and the deposition consumes time and a large amount of titanium. Thus, the second prior art process encounters another problem in high production cost.

[0008] A problem inherent in the second prior art contact is a high contact resistance. The high contact resistance is derived from shortage of dopant impurity in the contact area. The dopant impurity tends to be diffused into the thick refractory metal silicide layer, and makes the dopant concentration in the contact area light. This tendency is conspicuous in a miniature contact hole of the order of 0.5 micron by 0.5 micron square or 0.5 micron in diameter.

[0009] The aspect ratio of the contact hole is getting larger and larger together with the integration density. It is impossible to properly deposit refractory metal on the bottom surface of a miniature contact hole with a large aspect ratio through sputtering. Device manufacturers try to use a chemical vapor deposition so as to perfectly grow a refractory metal layer or a refractory metal silicide layer over the surface defining the miniature contact hole with the large aspect ratio. However, the refractory metal grows differently on the contact area depending upon the conductivity type of the contact area. When the refractory metal is concurrently deposited on a heavily doped p-type contact area and a heavily doped n-type contact area, the refractory metal layer on the heavily doped p-type contact area is different in thickness from the heavily doped n-type contact area. If one of the refractory metal layers is optimized, the other refractory metal layer is so thin that the electric resistance is increased. On the other hand, if the other refractory metal layer is optimized, the refractory metal layer is too thick, and leakage current is increased.

[0010] It is therefore an important object of the present invention to provide a process of fabricating a semiconductor device through which the contact resistance of a miniature contact hole is decreased by using a low temperature heat treatment.

[0011] It is also an important object of the present invention to provide a process of fabricating a semiconductor device through which contact areas different in conductivity type are properly covered with refractory metal layers or refractory metal silicide layers.

[0012] The present inventors contemplated the problems, and investigated influences of crystal structure on the contact resistance. The present inventors formed p-type single crystal impurity regions exposed by miniature contact holes of 0.5 micron square and p-type amorphous impurity regions also exposed by miniature contact holes of 0.5 micron square. The present inventors deposited titanium on the p-type single crystal impurity regions and the p-type amorphous impurity regions, and varied the thickness of the titanium layers. The titanium layers were treated with heat at 500 degrees centigrade for 30 minutes in nitrogen ambience, and titanium silicide layers formed contacts with the p-type single crystal impurity regions and the p-type amorphous impurity regions. The present inventors measured the contact resistance, and plotted the contact resistances in FIG. 1. Plot PL1 represents the contact resistance of the p-type single crystal impurity regions, and plot PL2 was indicative of the contact resistance of the p-type amorphous impurity regions.

[0013] The present inventors noticed that the contact resistance was varied between the single crystal and the amorphous silicon regions. The single crystal region required a thick titanium layer for a low resistivity contact, while the amorphous region formed a low-resistivity contact between 3 nanometers thick and 10 nanometers thick. The present inventors first concluded that the amorphous refractory metal layer between 3 nanometers and 10 nanometers thick was desirable for a low-resistivity contact.

[0014] The present inventors further investigated growing technologies, and found that a chemical vapor deposition was available for refractory metal deposited on an amorphous dopant impurity region exposed by a miniature contact hole with a large aspect ratio. A contact region was changed to amorphous by using an ion-implantation. Boron/boron difluoride (BF₂) or phosphorous/arsenic was desirable for the ion-implantation. If TiCl₄was reduced in the chemical vapor deposition, titanium was deposited at a certain temperature not higher than 600 degrees centigrade.

[0015] In accordance with one aspect of the present invention, there is provided a process of fabricating a semiconductor device on a semiconductor substrate, comprising: a) preparing a semiconductor layer; b) forming an insulating layer over the semiconductor layer; c) forming an opening in the insulating layer so that the semiconductor layer is exposed to the opening; d) making the semiconductor layer exposed to the opening amorphous; e) depositing a refractory metal layer from 3 nanometers to 10 nanometers thick on the semiconductor layer; and f) treating the refractory metal layer with heat so as to convert the refractory metal layer to a refractory metal silicide layer.

[0016] In accordance with another aspect of the present invention, there is provided a process of fabricating a semiconductor device, comprising the steps of: a) preparing a semiconductor layer; b) forming an insulating layer having an opening where the semiconductor layer is exposed; c) making the semiconductor layer exposed to the opening amorphous; and d) depositing a refractory metal layer by using a chemical vapor deposition so as to grow a refractory metal silicide on the semiconductor layer.

[0017] The features and advantages of the process according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which:

[0018] FIG. 1 is a graph showing relation between contact resistance and the thickness of a titanium layer on the bottom surface of a contact hole;

[0019] FIGS. 2A to 2F are cross sectional views showing a process of fabricating a semiconductor device according to the present invention;

[0020] FIGS. 3A to 3F are cross sectional views showing another process of fabricating a semiconductor device according to the present invention;

[0021] FIGS. 4A to 4H are cross sectional views showing yet another process of fabricating a semiconductor device according to the present invention;

[0022] FIGS. 5A and 5B are cross sectional views showing essential steps of still another process of fabricating a semiconductor device according to the present invention;

[0023] FIGS. 6A to 6E are cross sectional views showing still another process of fabricating a semiconductor device according to the present invention; and

[0024] FIG. 7 is a graph showing relation between the thickness of a titanium layer and the conductivity type of a silicon layer thereunder.

[0025] First Embodiment

[0026] FIGS. 2A to 2F illustrate a process of fabricating a semiconductor device embodying the present invention. The process starts with preparation of a p-type single crystal silicon substrate 1a, and a field oxide layer 1bis selectively grown on the major surface of the p-type silicon substrate 1a. The field oxide layer 1bdefines a plurality of active areas in the major surface, and two active areas are shown in FIGS. 2A to 2F. A lightly doped n-type well 3ais formed in one of the active areas, and a heavily doped p-type impurity region 3band a heavily doped n-type impurity region 4aare formed in the lightly doped n-type well 3aand the other of the active areas, respectively. The heavily doped p-type impurity region 3bis electrically isolated from the heavily doped n-type impurity region 4aby means of the field oxide layer 1b.

[0027] Boro phospho-silicate glass is deposited to 1.5 microns thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms an inter-level insulating layer 5a.

[0028] Photo-resist solution is spun onto the inter-level insulating layer 5a, and is baked so as to form a photo-resist layer on the inter-level insulating layer 5a. A pattern image representative of contact holes is optically transferred to the photo-resist layer so as to form a latent image therein. The latent image is developed, and the photo-resist layer is patterned into a photo-resist etching mask (not shown) for the contact holes. Thus, the photo-resist etching mask is provided on the inter-level insulating layer 5athrough a lithography.

[0029] Using the photo-resist etching mask, the inter-level insulating layer 5ais selectively etched so as to form contact holes 5band 5ctherein. The heavily doped n-type impurity region 4aand the heavily doped p-type impurity region 3bare respectively exposed to the contact holes 5b/5cof 0.5 micron square as shown in FIG. 2A. In this instance, openings of the photo-resist etching mask are slightly deviated from target positions over the heavily doped n-type impurity region 4aand the heavily doped p-type impurity region 3b, and, for this reason, the contact holes 5b/5care not exactly nested in the heavily doped n-type impurity region 4aand the heavily doped p-type impurity region 3b, respectively.

[0030] Subsequently, a photo-resist ion-implantation mask 6ais formed on the inter-level insulating layer 5aby using lithography, and the heavily doped n-type impurity region 4ais covered with the photo-resist ion-implantation mask 6a. Boron difluoride (BF₂) is ion-implanted through the contact hole 5cinto the heavily doped p-type single crystal impurity region 3bat dose of 5×10¹⁴cm⁻²to 5×10¹⁵cm⁻²under acceleration energy of 10 KeV to 30 KeV. A surface portion of the heavily doped p-type impurity region 3abecomes amorphous due to the ion bombardment expressed by mark “x”, and a p-type amorphous silicon layer 3cis formed in the heavily doped p-type single crystal impurity region 3bas shown in FIG. 2B. After the ion-implantation, the photo-resist ion-implantation mask 6ais stripped off, and the heavily doped n-type single crystal impurity region 4ais exposed again.

[0031] Another photo-resist ion-implantation mask 6bis provided on the inter-level insulating layer 5aby using the lithography, and the p-type amorphous silicon layer 3cis covered with the photo-resist ion-implantation mask 6b. Phosphorous is ion implanted through the contact hole 5binto the heavily doped n-type single crystal impurity region 4aat dose of 3×10¹⁴cm⁻²to 1×10¹⁵cm⁻²under acceleration energy of 10 KeV to 70 KeV. A surface portion of the heavily doped n-type single crystal impurity region 4abecomes amorphous due to the ion bombardment expressed by mark “x”, and an n-type amorphous silicon layer 4bis formed in the surface portion as shown in FIG. 2C. After the ion-implantation, the photo-resist ion-implantation mask 6bis stripped off.

[0032] Subsequently, titanium is sputtered over the entire surface of the resultant semiconductor structure, and a titanium layer 7atopographically extends over the entire surface. A collimator plate (not shown) is provided between the titanium target and the semiconductor structure shown in FIG. 2C for preventing the semiconductor structure from titanium particles obliquely radiated from the target, and has an aspect ratio of 3 in this instance. When the titanium is deposited through the collimator plate over the entire surface containing the bottom surfaces of the contact holes 5b/5cand the upper surface of the interlevel insulating layer 5a, the titanium layer 7ais not uniformly deposited, and the ratio of the titanium layer on the bottom surface to the titanium layer on the upper surface is of the order of 13 percent. In order to regulate the titanium layer 7afrom 3 nanometers to 10 nanometers thick, the titanium layer 7ais deposited from 23 nanometers to 77 nanometers thick on the upper surface of the inter-level insulating layer 5a.

[0033] Titanium nitride is sputtered over the titanium layer 7a, and the titanium layer 7ais overlain by a titanium nitride layer 7bas shown in FIG. 2D. The titanium nitride layer 7bis 100 nanometers thick over the upper surface of the inter-level insulating layer 5a. The titanium nitride layer 7bdefines secondary holes 5dand 5ein the contact holes 5band 5c, respectively. The titanium nitride layer 7bdoes not allow the titanium layer 7ato be nitrided in an annealing step, and the titanium nitride layer 7ballows the manufacturer to decrease the thickness of the titanium layer 7a. The titanium nitride layer 7bfurther serves as a barrier layer against tungsten in a later stage.

[0034] The resultant semiconductor structure is placed in nitrogen ambience, and is heated to between 400 degrees and 500 degrees centigrade. The semiconductor structure is maintained in the high temperature nitrogen ambience for 10 minutes to 60 minutes, and the titanium reacts with the p-type amorphous silicon 3cand the n-type amorphous silicon 4bso as to form titanium silicide layers 3d/4cas shown in FIG. 2E. Thus, the titanium reacts with the silicon at 400 degrees to 500 degrees centigrade, because the silicon is amorphous.

[0035] The p-type amorphous silicon and the n-type amorphous silicon are recrystallized during the annealing. The annealing temperature is low enough that the heavily doped n-type single crystal impurity region 4aand the heavily doped p-type single crystal impurity region 3bmaintain the impurity profiles. Moreover, the heat activates the boron difluoride and the phosphorous both implanted beneath the periphery of the field oxide layer 1b, and the boron difluoride and the phosphorous form an additional p-type impurity region 3eand an additional n-type impurity region 4dmerged into the heavily doped p-type single crystal impurity region 3band the heavily doped n-type single crystal impurity region 4a. Thus, the contact holes 5b/5care finally nested into the heavily doped n-type single crystal impurity region 4a/4dand the heavily doped p-type single crystal impurity region 3b/3e, respectively, and the mis-alignment of the photo-resist etching mask for the contact holes does not deteriorate electric characteristics of contacts between the heavily doped p-type/n-type single crystal impurity regions 3b/3e/4a/4dand conductive plugs formed in the secondary holes 5d/5eat a later stage. The ion-implanted impurities are activated at 10 to 50 percent through the annealing at 400 degrees to 500 degrees centigrade with respect to the annealing at 850 degrees centigrade, and reverse leakage current across the p-n junction is ten times larger than that annealed at 850 degrees centigrade. However, the reverse leakage current is admittable in a standard semiconductor integrated circuit.

[0036] Subsequently, tungsten is deposited over the titanium nitride layer 7b. The tungsten fills the secondary holes 5d/5e, and swells into a tungsten layer of 0.5 micron thick over the inter-level insulating layer 5a. A photo-resist etching mask (not shown) is formed on the tungsten layer by using the lithography, and the tungsten layer is selectively etched away. As a result, tungsten plugs 7c/7dare left in the secondary holes 5d/5e. The photo-resist etching mask is stripped off.

[0037] Aluminum alloy target (not shown) is prepared, and contains copper at 0.5 percent. The aluminum alloy is deposited to 0.5 micron thick over the entire surface of the resultant semiconductor structure by using a sputtering, and a photo-resist etching mask (not shown) is provided on the aluminum alloy layer by using the lithography. The aluminum alloy layer, the titanium nitride layer and the titanium layer are selectively etched away, and form multi-layer metal wirings 8aand 8bas shown in FIG. 2F.

[0038] The titanium layer 7aranges from 3 nanometers to 10 nanometers thick according to the present invention. If the titanium layer 7ais thinner than 3 nanometers, the titanium silicide layer 4c/3dare too thin to decrease the contact resistance. On the other hand, if the titanium layer 7ais thicker than 10 nanometers, the p-type dopant impurity and the n-type dopant impurity are diffused from the heavily doped p-type impurity region 3band the heavily doped n-type impurity region 4ainto the titanium silicide layers 3d/4c, and the resistance is increased in the n-type impurity region 4adue to shortage of the dopant impurities. Especially, the contact resistance over the n-type impurity region 4atends to be increased. Moreover, it is hard to deposit titanium more than 10 nanometers thick on the bottom surfaces of the contact holes 5b/5cby using the sputtering.

[0039] In this instance, boron difluoride and phosphorous are ion implanted. However, boron and arsenic are available for the ion-implantation.

[0040] The present inventors evaluated the contact formed through the process described hereinbefore. The contact resistance over the heavily doped p-type single crystal impurity region 3b/3ewas of the order of 150 ohms, and the contact resistance over the heavily doped n-type single crystal impurity region 4a/4dwas of the order of 100 ohms.

[0041] Second Embodiment

[0042] FIGS. 3A to 3F illustrate another process embodying the present invention. The process starts with preparation of a p-type single crystal silicon substrate 11a, and a field oxide layer 11bis selectively grown on the major surface of the p-type silicon substrate 11a. The field oxide layer 11bdefines a plurality of active areas in the major surface, and two active areas are shown in FIGS. 3A to 3F. A lightly doped n-type well 13ais formed in one of the active areas, and a heavily doped p-type impurity region 13band a heavily doped n-type impurity region 14aare formed in the lightly doped n-type well 13aand the other of the active areas, respectively. The heavily doped p-type impurity region 13bis electrically isolated from the heavily doped n-type impurity region 14aby means of the field oxide layer 11b.

[0043] Boro phospho-silicate glass is deposited to 1.5 microns thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms an inter-level insulating layer 15a.

[0044] A photo-resist etching mask (not shown) is provided on the inter-level insulating layer 15athrough a lithography. Using the photo-resist etching mask, the inter-level insulating layer 15ais selectively etched so as to form contact holes 15band 15ctherein. The heavily doped n-type impurity region 14aand the heavily doped p-type impurity region 13bare respectively exposed by the contact holes 15b/15cof 0.5 micron square as shown in FIG. 3A. In this instance, openings of the photo-resist etching mask are slightly deviated from target positions over the heavily doped n-type impurity region 14aand the heavily doped p-type impurity region 13b, and, for this reason, the contact holes 15b/15care not exactly nested in the heavily doped n-type impurity region 14aand the heavily doped p-type impurity region 13b, respectively.

[0045] Phosphorous is ion implanted through contact holes 15b/15cinto the heavily doped n-type single crystal impurity region 14aand the heavily doped p-type single crystal impurity region 13bat dose equal to or greater than 3×10¹⁴cm⁻²under acceleration energy of 70 KeV. Surface portions of these single crystal impurity regions 14a/13bbecome amorphous due to the ion bombardment marked with “x”, and the heavily doped n-type single crystal impurity region 14aand the heavily doped p-type single crystal impurity region 13bare overlain by an n-type amorphous silicon layer 14band a p-type amorphous silicon layer 13c, respectively, as shown in FIG. 3B. If the dose is less than 3×10^{14 cm−2}, the ion bombardment hardly makes the single crystal impurity regions 14b/13camorphous.

[0046] Subsequently, a photo-resist ion-implantation mask 16ais formed on the inter-level insulating layer 15aby using lithography, and the heavily doped n-type impurity region 14ais covered with the photo-resist ion-implantation mask 16a. Boron is ion-implanted through the contact hole 15cinto the heavily doped p-type single crystal impurity region 13bat dose of 1×10¹⁵cm⁻²to 5×10¹⁵cm⁻²under acceleration energy of 20 KeV to 50 KeV as shown in FIG. 3C.

[0047] The boron is so light that the minimum dose for the amorphous silicon is 1×10¹⁶cm⁻². For this reason, the surface portion of the heavily doped p-type impurity region 13bis converted to an amorphous through the bombardment of phosphorous. However, the boron is expected to change the n-type well 13abeneath the field oxide layer 11bto a p-type region so as to cure the mis-alignment of the photoresist etching mask for the contacts 15b/15c. After the ion-implantation, the photo-resist ion-implantation mask 16ais stripped off.

[0048] Subsequently, titanium is sputtered over the entire surface of the resultant semiconductor structure, and a titanium layer 17atopographically extends over the entire surface. The titanium layer 17ais not uniform in thickness as described hereinbefore, and the titanium layer 17aon the n-type amorphous layer 14band the p-type amorphous layer 13cranges from 3 nanometers to 10 nanometers thick.

[0049] Titanium nitride is sputtered over the titanium layer 17a, and the titanium layer 17ais overlain by a titanium nitride layer 17bas shown in FIG. 3D. The titanium nitride layer 17bis 100 nanometers thick over the upper surface of the inter-level insulating layer 15a. The titanium nitride layer 17bdefines secondary holes 15dand 15ein the contact holes 15band 15c, respectively. The titanium nitride layer 17bbehaves similarly to the titanium nitride layer 7b.

[0050] The resultant semiconductor structure is placed in nitrogen ambience, and is heated to between 400 degrees and 500 degrees centigrade. The semiconductor structure is maintained in the high temperature nitrogen ambience for 10 minutes to 60 minutes, and the titanium reacts with the p-type amorphous silicon 13cand the n-type amorphous silicon 14bso as to form titanium silicide layers 13d/14cas shown in FIG. 3E. Thus, the titanium reacts with the silicon at 400 degrees to 500 degrees centigrade, because the silicon is amorphous.

[0051] The p-type amorphous silicon and the n-type amorphous silicon are recrystallized during the annealing. The annealing temperature is low enough that the heavily doped n-type single crystal impurity region 14aand the heavily doped p-type single crystal impurity region 13bmaintain the impurity profiles. Moreover, the heat activates the boron and phosphorous both implanted beneath the periphery of the field oxide layer 11b, and the boron and the phosphorous form an additional p-type impurity region 13eand an additional n-type impurity region 14dmerged into the heavily doped p-type single crystal impurity region 13band the heavily doped n-type single crystal impurity region 14a. Thus, the contact holes 15b/15care finally nested into the heavily doped n-type single crystal impurity region 14a/14dand the heavily doped p-type single crystal impurity region 13b/13e, respectively, and the mis-alignment of the photo-resist etching mask for the contact holes does not deteriorate electric characteristics of the contacts between the heavily doped p-type/n-type single crystal impurity regions 13b/13e/14a/14dand conductive plugs formed in the secondary holes 15d/15eat a later stage.

[0052] In this instance, the p-type amorphous layer 13cis formed by using the boron instead of the boron difluoride. The boron allows the p-type amorphous layer 13cand the n-type amorphous layer 14bto be recrystallized at lower temperature within a shorter time period than the boron difluoride, and the ion-implanted dopant impurities are rapidly activated. The fluorine impedes the recrystallization and the activation. However, the fluorine is never introduced into the amorphous layers 13c/14bin this instance.

[0053] Subsequently, the secondary holes 15d/15eare plugged with pieces of tungsten 17c/17d, and multi-layer wirings 18a/18bare patterned on the inter-level insulating layer 15aas similar to the first embodiment. The resultant semiconductor structure is illustrated in FIG. 3F.

[0054] The process implementing the second embodiment achieves all the advantages of the first embodiment. Moreover, the ion-implantation of phosphorous is carried out without a photo-resist etching mask, and the process of the second embodiment is simpler than that of the first embodiment. For this reason, the production cost is decreased.

[0055] Third Embodiment

[0056] FIGS. 4A to 4H illustrate yet another process of fabricating a semiconductor device embodying the present invention. The process starts with preparation of a p-type single crystal silicon substrate 21a, and a field oxide layer 21bis selectively grown on the major surface of the p-type silicon substrate 21a. The field oxide layer 21bdefines a plurality of active areas in the major surface, and two active areas are shown in FIGS. 4A to 4H. A lightly doped n-type well 23ais formed in one of the active areas, and a heavily doped p-type impurity region 23band a heavily doped n-type impurity region 24aare formed in the lightly doped n-type well 23aand the other of the active areas, respectively. The heavily doped p-type impurity region 23bis electrically isolated from the heavily doped n-type impurity region 24aby means of the field oxide layer 21b.

[0057] Boro phospho-silicate glass is deposited to 1.5 microns thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms an inter-level insulating layer 25a.

[0058] A photo-resist etching mask (not shown) is provided on the inter-level insulating layer 25athrough lithography. Using the photo-resist etching mask, the inter-level insulating layer 25ais selectively etched so as to form contact holes 25band 25cof 0.5 micron square therein. The heavily doped n-type impurity region 24aand the heavily doped p-type impurity region 23bare respectively exposed by the contact holes 25b/25cas shown in FIG. 4A. In this instance, openings of the photo-resist etching mask are slightly deviated from target positions over the heavily doped n-type impurity region 24aand the heavily doped p-type impurity region 23b, and, for this reason, the contact holes 25b/25care not exactly nested in the heavily doped n-type impurity region 24aand the heavily doped p-type impurity region 23b, respectively.

[0059] Subsequently, a photo-resist ion-implantation mask 26ais formed on the inter-level insulating layer 25aby using lithography, and the heavily doped n-type impurity region 24ais covered with the photo-resist ion-implantation mask 26a. Boron difluoride is ion implanted through the contact hole 25cinto the heavily doped p-type single crystal impurity region 23bunder the conditions similar to the first embodiment. A surface portion of the heavily doped p-type impurity region 23abecomes amorphous due to the ion bombardment expressed by mark “x”, and a p-type amorphous silicon layer 23cis formed in the heavily doped p-type single crystal impurity region 23bas shown in FIG. 4B. After the ion-implantation, the photo-resist ion-implantation mask 26ais stripped off, and the heavily doped n-type single crystal impurity region 24ais exposed again.

[0060] Another photo-resist ion-implantation mask 26bis provided on the inter-level insulating layer 25aby using lithography, and the p-type amorphous silicon layer 23cis covered with the photo-resist ion-implantation mask 26b. Phosphorous is ion implanted through the contact hole 25binto the heavily doped n-type single crystal impurity region 24aunder the conditions similar to the first embodiment. A surface portion of the heavily doped n-type single crystal impurity region 24abecomes amorphous due to the ion bombardment expressed by mark “x”, and an n-type amorphous silicon layer 24bis formed in the surface portion as shown in FIG. 4C. After the ion-implantation, the photo-resist ion-implantation mask 26bis stripped off.

[0061] The resultant semiconductor structure is placed in inert ambience containing nitrogen. The p-type amorphous silicon layer 23cand the n-type amorphous silicon layer 24bare heated to between 800 degrees and 900 degrees centigrade, and are maintained in the high-temperature inert ambience for 10 minutes to 30 minutes. The boron of the boron difluoride and the phosphorous are perfectly activated, and the p-type amorphous silicon layer 23cand the n-type amorphous silicon layer 24bare recrystallized again. Moreover, an additional p-type region 23dand an additional n-type region 24care merged with the heavily doped p-type single crystal impurity region 23band the heavily doped n-type single crystal impurity region 24a. Thus, the mis-alignment between the heavily doped single crystal impurity regions 23b/24aand the contact holes 25c/25bis cured through the heat treatment. The resultant semiconductor structure is illustrated in FIG. 4D.

[0062] Subsequently, arsenic is ion implanted through the contact holes 25b/25cinto the heavily doped p-type single crystal impurity region 23b/23dand the heavily doped n-type single crystal impurity region 24a/24c. The dose is more than 2×10¹⁴cm⁻²and much less than the dose of the boron difluoride. The acceleration energy is regulated to 30 KeV. If the dose of the arsenic is less than 2×10¹⁴cm⁻², an amorphous silicon layer is not produced. On the other hand, if the dose of the arsenic is greater than the dose of the boron difluoride, an n-type amorphous silicon layer is formed on the heavily doped p-type single crystal impurity region 23b/23d. The bombardment of arsenic makes a surface portion of the heavily doped p-type single crystal impurity region 23b/23dand a surface portion of the heavily doped n-type single crystal impurity region 24a/24camorphous. Thus, the heavily doped p-type single crystal impurity region 23b/23dand the heavily doped n-type single crystal impurity region 24a/24care respectively overlain by a p-type amorphous silicon layer 23eand an n-type amorphous silicon layer 24das shown in FIG. 4E.

[0063] Subsequently, titanium is sputtered over the entire surface of the resultant semiconductor structure, and a titanium layer 27atopographically extends over the entire surface. The titanium layer 27ais not uniform in thickness, and the p-type amorphous silicon layer 23eand the n-type amorphous silicon layer 24dare covered with the titanium layer 27aranging from 3 nanometers to 10 nanometers thick.

[0064] Titanium nitride is sputtered over the titanium layer 27a, and the titanium layer 27ais overlain by a titanium nitride layer 27bas shown in FIG. 4F. The titanium nitride layer 7bis 100 nanometers thick over the upper surface of the inter-level insulating layer 25a. The titanium nitride layer 27bdefines secondary holes 25dand 25ein the contact holes 25band 25c, respectively. The titanium nitride layer 27bserves as a protective layer as similar to that of the first embodiment.

[0065] The resultant semiconductor structure is placed in inert ambience containing nitrogen, and is heated to between 400 degrees and 500 degrees centigrade. The semiconductor structure is maintained in the high temperature inert ambience for 10 minutes to 60 minutes, and the titanium reacts with the p-type amorphous silicon 23eand the n-type amorphous silicon 24dso as to form titanium silicide layers 23e/24das shown in FIG. 4G. Thus, the titanium reacts with the silicon at 400 degrees to 500 degrees centigrade, because the silicon is amorphous. The p-type amorphous silicon and the n-type amorphous silicon are recrystallized during the annealing, and the ion-implanted arsenic is activated. The annealing temperature is low enough that the heavily doped n-type single crystal impurity region 24aand the heavily doped p-type single crystal impurity region 23bmaintain the impurity profiles. Even though the arsenic is activated, the single crystal impurity region 23b/23dare maintained in the p-type.

[0066] Subsequently, the secondary holes 25d/25eare plugged with pieces of tungsten 27c/27d, and multi-layer wirings 28a/28bare patterned on the inter-level insulating layer 25aas similar to the first embodiment. The resultant semiconductor structure is illustrated in FIG. 4H.

[0067] The process implementing the third embodiment achieves all the advantages of the first embodiment. Moreover, the boron and the phosphorous are activated at approximately 100 percent during the heat treatment described in conjunction with FIG. 4D, and the reverse leakage current is decreased from those of the first and second embodiments.

[0068] If the arsenic increases the contact resistance between the heavily doped p-type single crystal impurity region 23b/23dand the titanium silicide layer 23eto non-acceptable level, boron difluoride may be ion implanted into the heavily doped p-type single crystal impurity region 23b/23dinstead of the arsenic. The p-type amorphous silicon layer 23eand the n-type amorphous silicon layer 24dmay be formed through an ion-implantation of boron difluoride and an ion-implantation of phosphorous, respectively.

[0069] Fourth Embodiment

[0070] FIGS. 5A and 5B illustrate still another process of fabricating a semiconductor device embodying the present invention. The process implementing the fourth embodiment is available for impurity regions wide enough to nest contact holes therein.

[0071] The process starts with preparation of a p-type single crystal silicon substrate 31a, and a field oxide layer 31bis selectively grown on the major surface of the p-type silicon substrate 31a. The field oxide layer 31bdefines a plurality of active areas in the major surface, and two active areas are shown in FIGS. 5A and 5B. A lightly doped n-type well 33ais formed in one of the active areas, and a heavily doped p-type impurity region 33band a heavily doped n-type impurity region 34aare formed in the lightly doped n-type well 33aand the other of the active areas, respectively. The heavily doped p-type impurity region 33bis electrically isolated from the heavily doped n-type impurity region 34aby means of the field oxide layer 31b.

[0072] Boro phospho-silicate glass is deposited to 1.5 microns thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms an inter-level insulating layer 35a.

[0073] A photo-resist etching mask (not shown) is provided on the inter-level insulating layer 35athrough lithography. Using the photo-resist etching mask, the inter-level insulating layer 35ais selectively etched so as to form contact holes 35band 35ctherein. The heavily doped n-type impurity region 34aand the heavily doped p-type impurity region 33bare respectively exposed by the contact holes 35b/35cas shown in FIG. 5A. The photo-resist etching mask is then stripped off.

[0074] There is an margin between the heavily doped single crystal impurity regions 34a/33band the contact holes 35b/35cas described hereinbefore. For this reason, even if the photo-resist etching mask is mis-aligned with the target areas over the heavily doped single crystal impurity regions 34a/33b, the contact holes 35b/35care still nested in the heavily doped single crystal impurity regions 34a/33b, respectively.

[0075] Arsenic or boron difluoride is ion implanted through the contact holes 35b/35cinto the heavily doped n-type single crystal impurity region 34aand the heavily doped p-type single crystal impurity region 33bas similar to the third embodiment. The ion bombardment makes a surface portion 34bof the heavily doped n-type single crystal impurity region 34aand a surface portion 33cof the heavily doped p-type single crystal impurity region 33bamorphous. If the arsenic is ion implanted, the dose should be selected in such a manner that the implanted arsenic does not change the conductivity type of the heavily doped p-type single crystal impurity region 33b. Similarly, if the boron difluoride is ion implanted, the dose should be selected in such a manner that the implanted boron does not change the conductivity type of the heavily doped n-type single crystal impurity region 34a.

[0076] Thereafter, the process proceeds to the steps shown in FIGS. 4F to 4H.

[0077] Fifth Embodiment

[0078] FIGS. 6A to 6E illustrate still another process of fabricating a semiconductor device embodying the present invention. The process starts with preparation of a p-type single crystal silicon substrate 41a, and a field oxide layer 41bis selectively grown on the major surface of the p-type silicon substrate 41a. The field oxide layer 41bdefines a plurality of active areas in the major surface, and two active areas are shown in FIGS. 6A to 6E. A lightly doped n-type well 43ais formed in one of the active areas, and a heavily doped p-type impurity region 43band a heavily doped n-type impurity region 44aare formed in the lightly doped n-type well 43aand the other of the active areas, respectively. The heavily doped p-type impurity region 43bis electrically isolated from the heavily doped n-type impurity region 44aby means of the field oxide layer 41b.

[0079] Boro phospho-silicate glass is deposited over the entire surface of the resultant semiconductor structure, and forms an inter-level insulating layer 45a.

[0080] A photo-resist etching mask (not shown) is provided on the inter-level insulating layer 5athrough lithography. Using the photo-resist etching mask, the inter-level insulating layer 45ais selectively etched so as to form contact holes 45band 45ctherein. The heavily doped n-type impurity region 44aand the heavily doped p-type impurity region 43bare respectively exposed by the contact holes 45b/45cas shown in FIG. 6A.

[0081] Subsequently, a photo-resist ion-implantation mask 46ais formed on the inter-level insulating layer 45aby using lithography, and the heavily doped n-type impurity region 44ais covered with the photo-resist ion-implantation mask 46a. Boron difluoride (BF₂) is ion-implanted through the contact hole 45cinto the heavily doped p-type single crystal impurity region 43b, and a surface portion of the heavily doped p-type impurity region 43abecomes amorphous due to the ion bombardment expressed by mark “x”. Thus, a p-type amorphous silicon layer 43cis formed in the heavily doped p-type single crystal impurity region 43bas shown in FIG. 6B. After the ion-implantation, the photo-resist ion-implantation mask 46ais stripped off, and the heavily doped n-type single crystal impurity region 44ais exposed again.

[0082] Another photo-resist ion-implantation mask 46bis provided on inter-level insulating layer 45aby using the lithography, and the p-type amorphous silicon layer 43cis covered with the photo-resist ion-implantation mask 46b. Phosphorous is ion implanted through the contact hole 45binto the heavily doped n-type single crystal impurity region 44a, and a surface portion of the heavily doped n-type single crystal impurity region 44abecomes amorphous due to the ion bombardment expressed by mark “x”. Thus, an n-type amorphous silicon layer 44bis formed in the surface portion as shown in FIG. 6C. After the ion-implantation, the photo-resist ion-implantation mask 46bis stripped off. Subsequently, titanium is deposited over the entire surface of the resultant semiconductor structure by using a plasma-assisted chemical vapor deposition. In detail, the resultant semiconductor structure is placed in a reaction chamber of a plasma-assisted chemical vapor deposition system (not shown), and the p-type semiconductor substrate 41ais heated to between 450 degrees and 650 degrees centigrade. A gaseous mixture is introduced into the reaction chamber, and is regulated to between 1 torr and 100 torr. The gaseous mixture contains TiCl₄, H₂and Ar, and flow rates of TiCl₄, H₂and Ar are regulated from 5 sccm to 20 sccm, 1000 sccm to 2000 sccm and 200 sccm to 500 sccm, respectively. TiCl₄is decomposed, and the entire surface of the semiconductor structure is covered with a titanium layer 47a. The titanium immediately reacts with the amorphous silicon, and titanium silicide layers 43d/44care formed on the p-type amorphous silicon layer 43cand the n-type amorphous silicon layer 44b. There is no substantial time delay between the introduction of the gaseous mixture and the deposition of titanium, and the titanium silicide layer 43dis approximately equal in thickness to the titanium silicide layer 44cregardless of the conductivity type of the amorphous silicon. When the titanium layer 47aon the amorphous silicon layers 44b/43creaches a certain thickness equivalent to a titanium layer ranging between 3 nanometers to 10 nanometers thick, the plasma-assisted chemical vapor deposition is completed. When the titanium layer 47ais assumed to be uniformly grown, the titanium silicide layers 43d/44crange between 7.5 nanometers to 25 nanometers thick.

[0083] Subsequently, titanium nitride is deposited from 30 nanometers to 50 nanometers thick over the titanium layer 47aand the titanium silicide layers 43d/44cby using a low-pressure chemical vapor deposition. The p-type silicon substrate 41ais heated to between 450 degrees and 650 degrees centigrade, and a gaseous mixture of TiCl₄, NH₃and N₂is regulated to between 1 torr to 100 torr. The flow rates of TiCl₄, NH₃and N₂are regulated from 20 sccm to 50 sccm, 50 sccm to 100 sccm and 2000 sccm to 5000 sccm, respectively. Thus, the titanium layer 47aand the titanium silicide layers 43d/44care covered with a titanium nitride layer 47bas shown in FIG. 6D.

[0084] The p-type amorphous layer 43cand the n-type amorphous layer 44bare recrystallized during the chemical vapor depositions. Even if the boron and the phosphorous are ion implanted into the peripheries beneath the field oxide layer 41b, the boron and the phosphorous are activated during the chemical vapor depositions, and an additional p-type region 43eand an additional n-type region 44dare merged with the heavily doped p-type single crystal impurity region 43band the heavily doped n-type single crystal impurity region 44a, respectively.

[0085] If the activation and the recrystallization is insufficient, a large amount of reverse current flows through the junction. A post annealing may be carried out at 450 degrees to 500 degrees centigrade for 30 minutes or 700 degrees centigrade for 30 seconds after the formation of the titanium nitride layer 42.

[0086] Subsequently, tungsten is deposited over the titanium nitride layer 47b. The tungsten fills the secondary holes defined by the titanium nitride layer 47b, and swells into a tungsten layer over the inter-level insulating layer 45a. A photo-resist etching mask (not shown) is formed on the tungsten layer by using lithography, and the tungsten layer is selectively etched away. As a result, tungsten plugs 47c/47dare left in the secondary holes. The photo-resist etching mask is stripped off.

[0087] Aluminum alloy is deposited over the entire surface of the titanium nitride layer 47bby using a sputtering, and a photo-resist etching mask (not shown) is provided on the aluminum alloy layer by using lithography. The aluminum alloy layer, the titanium nitride layer 47band the titanium layer 47aare selectively etched away, and form multi-layer metal wirings 48aand 48bas shown in FIG. 6E.

[0088] Boron and arsenic are available for making the single crystal impurity regions amorphous.

[0089] As will be understood from the foregoing description, the chemically active amorphous silicon layers 43c/44bare exposed by the contact holes 45b/45c, and no substantial time delay is introduced between the supply of TiCl₄and the deposition of titanium. As a result, the titanium silicide layers 43d/44cequal in thickness are concurrently grown on the impurity regions 43b/44a, respectively, and do not deteriorate electric characteristics of the semiconductor device. The delay time is clear at a low temperature less than 60 degrees in centigrade.

[0090] The titanium is deposited by using the chemical vapor deposition as described hereinbefore. The chemical vapor deposition creates a uniform layer rather than the sputtering, and the titanium on the amorphous layers easily exceeds 10 nanometers thick. It is not necessary to regulate the titanium on the amorphous layers to 10 nanometers or less. However, a thin titanium layer decreases the contact resistance.

[0091] If titanium is directly deposited on a p-type single crystal impurity region and an n-type single crystal impurity region without the ion-bombardment shown in FIGS. 6B and 6C, the titanium decomposed from TiCl₄is deposited as indicated by plots PL3 and PL4 in FIG. 7, and the titanium layer on the n-type single crystal impurity region becomes much thicker than the titanium layer on the p-type single crystal impurity region. This is because of the fact that long time delay is introduced from the supply of TiCl₄and the deposition of titanium on the p-type single crystal impurity region. As a result, the contacts suffers from either leakage current or contact resistance as described in conjunction with the prior art.

[0092] On the other hand, the contacts according to the present invention are small in leakage current and low in contact resistance by virtue of the titanium silicide layers equally deposited on the amorphous layers.

[0093] Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention.

[0094] For example, the present invention is applicable to other refractory metals in so far as the refractory metal is chemically active on an amorphous silicon layer.