US 6,815,286 B2Grant
Memory device
Issue Date:2004-11-09
•30 Claims
•4 Drawing Sheets
Abstract
A method of forming and operating a memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer with variable electrical conductivity; and (e) at least one passive layer containing a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.
Metadata
Assignee
- Advanced Micro Devices, Inc.
Inventors
- Juri H. Krieger
- Nikolai Yudanov
Application Information
Application Number:US 10/238,880
Filing Date:2002-09-11
Priority Date:2001-08-13
Art Unit:7
Classifications
IPC:
H01L 218238H01L 218244
Field of Search:
438 3438149438153438238438381438400438680438681
Patent Drawings (4 sheets)
Description
Cross-Reference to Related Application
[0002] This application is a Continuation-in-Part of PCT application PCT/RU01/00334 filed Aug. 13, 2001.
Field of the Invention
[0003] This present invention relates to novel memory devices. The invention is useful in the development, manufacture, and use of a variety of devices and/or technologies, including, inter alia, memory devices for electronic computers, associative memory systems, circuit elements with programmable resistance for creating synapses for neuronal nets, direct access data banks, and new types of video/audio equipment.
Background of the Invention
[0004] Modern electronic computers employ several different types of memory devices for various purposes and functions requiring different performance/operating characteristics, e.g., read/write and storage/retrieval speeds. The multiplicity of different requirements for the various memory devices substantially complicates the operation of computer systems, increases start-up times, and complicates data storage.
[0005] As a consequence of the above-mentioned drawbacks and disadvantages associated with current memory device technology, a high priority task of the microelectronics industry is creation/development of a universal memory device/system having high read/write speeds, high storage density, and long term data retention characteristics.
[0006] A number of electronic memory or switching devices have been proposed or developed which include a bi-stable element that can be controllably alternated between high impedance and low impedance states by application of an electrical input, e.g., a voltage equal to or greater than a threshold voltage. Memory and switching devices utilizing such threshold-type behavior have been demonstrated with both organic and inorganic thin film semiconductor materials, including amorphous silicon, chalcogenides such as arsenic trisulphide-silver (As2S3—Ag), organic materials, and heterostructures such as SrZrO3(0.2% Cr)/SrRuO3. See, for example: U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; 5,670,818; 5,770,885; and 6,150,705; Russian Patent No. 2,071,126; S. R. Ovshinsky, Phys. Rev. Lett., 36, 1469 (1976); J. H. Krieger, et al., J. Struct. Chem., 34, 966 (1993); J. H. Krieger, et al., Synthetic Metals, 122, 199 (2001); R. S. Potember, et al., Appl. Phys. Lett., 34 (6), 405 (1979); Y. Machida, et al., Jap. J. Appl. Phys., Part 1, 28 (2), 297 (1989); A. Beck, et al., Appl. Phys. Lett., 77, 139 (2000); and C. Rossel et al., J. Appl. Phys. (2001), in press.
[0007] U.S. Pat. No. 6,055,180 to Gudeson, et al. discloses an electrically addressable, passive storage device for registration, storage, and/or processing of data, comprising a functional medium in the form of a continuous or patterned structure capable of undergoing a physical or chemical change of state. The functional medium comprises individually addressable cells each of which represents a registered or detected value or is assigned a predetermined logical value. Each cell is sandwiched between an anode and cathode (electrode means) which contact the functional medium of the cell for electrical coupling therethrough, with the functional medium having a non-linear impedance characteristic, whereby the cell can be directly supplied with energy for effecting a change in the physical or chemical state in the cell.
[0008] A disadvantage/drawback of the storage device of U.S. Pat. No. 6,055,180, however, is that writing of information can occur only once, and reading of the stored information is performed optically, thereby increasing the size and complexity of the device and its use, at the same time reducing reliability of reading of the information due to the difficulty in accurately positioning the optical beam. In addition, an alternate writing method utilizing thermal breakdown caused by application of a high voltage is also disadvantageous in that writing of information can only occur once, and high voltages, hence high electrical fields, are required.
[0009] JP 62-260401 discloses a memory cell with a three-layer structure comprised of a pair of electrodes with a high temperature compound (i.e., molecule) sandwiched therebetween, which memory cell operates on a principle relying upon a change of electrical resistance of the compound upon application of an external electric field. Since the conductivity of the compound can be controllably altered between two very different levels, information in bit form can be stored therein.
[0010] U.S. Pat. No. 5,761,116 to Kozicki et al. discloses a “programmable metallization cell” comprised of a “fast ion conductor”, such as a film or layer of a chalcogenide doped with a metal ion, e.g., silver or copper, and a pair of electrodes, i.e., an anode (e.g., of silver) and a cathode (e.g., of aluminum), spaced apart at a set distance on the surface of the doped chalcogenide. The silver or copper ions can be caused to move through the chalcogenide film or layer under the influence of an electric field. Thus, when a voltage is applied between the anode and the cathode, a non-volatile metal dendrite (“nano-wire”) grows on the surface of the chalcogenide film or layer (“fast ion conductor”) from the cathode to the anode, significantly reducing the electrical resistance between the anode and cathode. The growth rate of the dendrite is a function of the applied voltage and the interval of its application. Dendrite growth may be terminated by removing the applied voltage and the dendrite may be retracted towards the cathode by reversing the polarity of the applied voltage.
[0011] U.S. Pat. No. 5,670,818 to Forouhi et al. discloses a read-only memory device in the form of an electrically programmable antifuse comprised of a layer of amorphous silicon between metal conductors. Under application of a high voltage, a portion of the amorphous silicon layer undergoes a phase change and atoms from the metal conductors migrate into the silicon layer, resulting in formation of a thin conducting filament (“nano-wire”) composed of a complex mixture of silicon and metal.
[0012] The principal shortcomings of the above-described memory devices relying upon nano-wire formation are related to the low operational speeds caused by the extended interval required for effecting substantial change in the electrical resistance between the electrodes/conductors and to the high voltage required, e.g., ˜60 V. Such drawbacks significantly limit practical use of the cells in current high speed electronic devices.
[0013] U.S. Pat. No. 4,652,894 to Potember et al. discloses a current-controlled, bi-stable threshold or memory switch, comprised of a layer of a polycrystalline metal-organic semiconductor material sandwiched between a pair of metallic electrodes, wherein the layer of metal-organic semiconductor material is an electron acceptor for providing fast switching at low voltages between high and low impedance states.
[0014] Practical implementation of the threshold memory switch of U.S. Pat. No. 4,652,894 is limited, however, principally due to the use of low temperature metal-organic semiconductor compounds which are not sufficiently mechanically robust, and more importantly, are insufficiently resistant to chemical degradation when subjected to the elevated temperatures commonly associated with modern semiconductor manufacturing processing, i.e., greater than about 150° C. and as high as about 400° C. In addition, the physical characteristics of the metal-organic semiconductor materials cause poor repeatability of the read/write/erase cycle, and storage is limited to only 1 bit of formation, thereby prohibiting use in high information density applications/devices.
[0015] In view of the above, there exists a clear need for memory devices which are free of the above-described shortcomings, drawbacks, and disadvantages associated with memory devices of the conventional art. The present invention, therefore, has as its principal aim the development of a universal memory device/system for high speed data storage and retrieval, with capability of long term storage at high bit densities.
Disclosure of the Invention
[0016] An advantage of the present invention is an improved memory storage and retrieval device.
[0017] Another advantage of the present invention is an improved memory storage and retrieval device not requiring formation of conventional semiconductor junctions.
[0018] Yet another advantage of the present invention is an improved memory storage and retrieval device which can be readily fabricated from a variety of materials.
[0019] Still another advantage of the present invention is an improved memory storage and retrieval device having very high read and write speeds, long term data retention, and high data storage density.
[0020] Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
[0021] According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a memory storage and retrieval device, comprising:
[0022] (a) an electrically conductive first electrode;
[0023] (b) an electrically conductive second electrode; and
[0024] (c) a layer stack intermediate the first and second electrodes, the layer stack comprising:
[0025] (d) at least one active layer with variable electrical conductivity; and
[0026] (e) at least one passive layer comprised of a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.
[0027] In accordance with embodiments of the present invention, the electrical conductivity of the at least one active layer is reversibly varied upon introduction and removal of charged species; and the at least one passive layer is comprised of a source material for reversibly donating the charged species to and accepting the charged species from the active layer.
[0028] According to preferred embodiments of the invention, the charged species comprise ions or a combination of ions and electrons, the ions being selected from the group consisting of: metal ions, metal-containing ions, non-metal ions, and non-metal-containing ions.
[0029] Embodiments of the present invention include those wherein the layer stack comprises a pair of active layers in mutual contact; and the layer stack may further comprise:
[0030] (f) at least one barrier layer comprised of a material which impedes spontaneous movement of the charged species when the electrical potential difference is not applied between the first and second electrodes.
[0031] Further embodiments of the present invention include those wherein the at least one barrier layer is positioned within the stack intermediate the active layer and the passive layer; embodiments wherein the layer stack comprises first and second active layers and the at least one barrier layer is positioned within the stack intermediate the first and second active layers; and embodiments wherein the layer stack comprises first and second passive layers in respective contact with the first and second electrically conductive electrodes.
[0032] According to still further embodiments of the present invention, the at least one active layer and the at least one passive layer are each comprised of the same material, e.g., an intercalation compound such as LixVSe2or LixHfSe2, whereby the stack effectively comprises a single layer.
[0033] In accordance with embodiments of the present invention, each of the first and second electrically conductive electrodes comprises at least one electrically conductive material selected from the group consisting of metals, metal alloys, metal nitrides, oxides, sulfides, carbon, and polymers; and according to particular embodiments of the invention, each of the first and second electrically conductive electrodes comprises at least one material selected from the group consisting of aluminum (Al), silver (Ag), copper (Cu), titanium (Ti), tungsten (W), their alloys and nitrides, amorphous carbon, transparent oxides, transparent sulfides, and conductive organic polymers, each of the first and second electrically conductive electrodes being from about 3,000 to about 8,000 Å thick, preferably about 5,000 Å thick.
[0034] According to embodiments of the present invention, the at least one active layer comprises at least one material with a relatively lower intrinsic electrical conductivity when free of the charged species and a relatively higher electrical conductivity when doped with the charged species, i.e., the at least one active layer comprises at least one material selected from the group consisting of dielectrics, semiconductors, ferroelectrics, ceramics, organic polymers, molecular crystals, and composites thereof, wherein the at least one active layer includes a plurality of channels or pores extending therethrough for facilitating movement of the charged species therein, selected from the group consisting of Si, amorphous Si, organic polymers, silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), boron nitride (BN), carbon tri-nitride (CN3), copper oxide (Cu2O), vanadium oxide (V2O3), ferroelectric materials, materials containing electrolyte clusters, and intercalation compounds selected from LixVSe2and LixHfSe2; and the at least one active layer is from about 50 to about 1,000 Å thick, preferably about 100 Å thick.
[0035] In accordance with embodiments of the present invention, the at least one passive layer comprises at least one super-ionic conductor material or intercalation compound, wherein the at least one super-ionic conductor material or intercalation compound reversibly donates and accepts charged species; e.g., ions or ions+electrons, the ions being selected from the group consisting of silver (Ag), copper (Cu), gold (Au), lithium (Li), sodium (Na), potassium (K), zinc (Zn), magnesium (Mg), other metal or metal-containing ions, hydrogen (H), oxygen (O), fluorine (F), and other halogen-containing ions; and the at least one super-ionic conductor material or intercalation compound is selected from the group consisting of AgI, AgBr, Ag2S, Ag2Se, Ag2−xTe, RbAg4I5, CuI, CuBr, Cu2−xS, Cu2−xSe, Cu2−xTe, AgxCu2−xS, Cu3HgI4, Cu3HgI4, AuI, Au2S, Au2Se, Au2S3, NaxCuySe2, LiNiO2, LixTiS2, LixMoSe2, LixTaS2, LixVSe2, LixHfSe2, LixWO3, CuxWO3, NaxWO3, Naβ-Al2O3, (AgI)x(Ag2OnB2O3)1−x, Ag2CdI4, CuxPb1−xBr2−x, Li3M2(PO4)3—where M=Fe, Sc, or Cr, K3Nb3B2O12, K1−xTi1−xNbxOPO4, SrZr1−xYbxO3, Sr1−x/2Ti1−x, NbxO3−δ, β-Mg3Bi2, Cs5H3(SO4)x.H2O, M3H(XO4)2—where M=Rb, Cs, or NH4and X=Se or S, NaZr2(PO4)3, Na4.5FeP2O8(OF)1−x, ZrO2−x, CeO2−x, CaF2, and BaF2, and is from about 20 to about 100 Å thick, preferably about 50 Å thick.
[0036] According to embodiments of the present invention, the at least one barrier layer comprises at least one material selected from the group consisting of Li3N and LiAlF4and is from about 20 to about 300 Å thick, preferably about 50 Å thick.
[0037] Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.
Brief Description of the Drawings
[0038] The following detailed description of the embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which similar reference numerals are employed throughout to designate similar features, and in which the various features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features, wherein:
[0039] FIGS. 1(A)-1(B), show, in schematic, partially cut-away perspective view, an example of a two-layer memory device 10 according to the invention for illustrating the principle of conductivity modulation;
[0040] FIG. 2 is a current (I)-voltage (V) plot for illustrating operation of memory devices according to the invention;
[0041] FIG. 3 is a plot of voltage (V) and current (I) vs. time (in nsec.) during switching of memory devices according to the invention from a high resistance “off” state (corresponding to a logical 0) to a low resistance “on” state (corresponding to a logical 1); and
[0042] FIGS. 4-9 illustrate in simplified, schematic cross-sectional view, several memory device constructions according to the invention, each comprising a layer stack between a pair of vertically spaced apart first and second electrodes.
Description of the Invention
[0043] The present invention is based upon the discovery by the inventors that: (1) materials exist, or can be prepared, which can be made to exhibit reversible change, i.e., modulation, of their electrical conductivity upon application and subsequent removal of an electrical field; and (2) useful devices, in particular memory devices, can be fabricated wherein the phenomenon of reversible conductivity change or modulation exhibited by such materials forms the basis for operation of the devices.
[0044] Specifically, there exists a large class of materials with relatively low intrinsic electrical conductivity, including various dielectrics, ferroelectrics, semiconductors, ceramics, organic polymers, molecular crystals, and composites of the aforementioned materials, which are potentially useful as an active layer of a memory device, which materials can be formed into layers exhibiting a substantial increase in conductivity (i.e., conductivity modulation) when doped with charged species of various types, for example ions or a combination of ions and electrons, which are introduced thereinto under the influence of an applied electrical field of a first polarity, and which layers reversibly exhibit a substantial decrease in electrical conductivity when the charged species are caused to be at least partially withdrawn therefrom by application of an electrical field of a second, opposite polarity. Thus, active layers according to the present invention are susceptible to conductivity modulation by means of reversible doping/withdrawal of charged species, e.g., ions or ions+electrons, under the influence of applied electric fields of appropriate polarity. According to the inventive methodology, materials suitable for use as the active layers typically comprise a plurality of micro-channels or pores for facilitating reversible movement of the charged species therethrough, and typically are selected from among Si, amorphous Si, organic polymers, silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), vanadium oxide (V2O3), boron nitride (BN), carbon tri-nitride (CN3), copper oxide (Cu2O), ferroelectric materials, materials containing electrolyte clusters, and intercalation compounds selected from LixVSe2and LixHfSe2.
[0045] A key feature of the present invention is the presence of an additional layer of material, termed a passive layer, for reversibly functioning as a source of the charged species, e.g., ions or ions+electrons, which are introduced (injected) into the active layer during application of the first polarity electrical field and as an acceptor (sink) of the charged species which are removed (withdrawn) from the active layer during application of the second, opposite polarity electrical field. According to the invention, materials suitable for use as the passive layer include those which readily and reversibly donate/accept charged species, for example, compounds with mobile ions, including super-ionic conductors and intercalation compounds, e.g., AgI, AgBr, Ag2S, Ag2Se, Ag2−xTe, RbAg4I5, CuI, CuBr, Cu2−xS, Cu2−xSe, Cu2−xTe, AgxCu2−xS, Cu3HgI4, Cu3HgI4, AuI, Au2S, Au2Se, Au2S3, NaxCuySe2, LiNiO2, LixTiS2, LixMoSe2, LixTaS2, LixVSe2, LixHfSe2, LixWO3, CuxWO3, NaxWO3, Naβ-Al2O3, (AgI)x(Ag2OnB2O3)1−x, Ag2CdI4, CuxPb1−xBr2−x, Li3M2(PO4)3—where M=Fe, Sc, or Cr, K3Nb3B2O12, K1−xTi1−xNbxOPO4, SrZr1−xYbxO3, Sr1−x/2Ti1−x, NbxO3−δ, β-Mg3Bi2, Cs5H3(SO4)x.H2O, M3H(XO4)2—where M=Rb, Cs, or NH4and X=Se or S, NaZr2(PO4)3, Na4.5FeP2O8(OF)1−x, ZrO2−x, CeO2−x, CaF2, and BaF2, which materials reversibly donate/accept silver (Ag), copper (Cu), gold (Au), lithium (Li), sodium (Na), potassium (K), zinc (Zn), magnesium (Mg), other metal or metal-containing ions, hydrogen (H), oxygen (O), fluorine (F), and other halogen-containing ions.
[0046] Several of the above-listed materials, e.g., LixVSe2, LixHfSe2, may be simultaneously utilized for the active layer and the passive layer, whereby embodiments of memory devices fabricated according to the invention with such materials capable of simultaneously functioning as the active and passive layers effectively comprise a single layer sandwiched between a pair of electrodes.
[0047] Materials usable as the passive layer are characterized by the ease, i.e., rapidity, with which they donate and accept charged species, e.g., ions or ions+electrons, under the influence of a relatively weak electric field, i.e., within the range of electric fields used in typical semiconductor devices such as flash memories. Thus, application of a first polarity electric field to a layer stack comprised of at least one active layer and at least one passive layer will draw charged species such as ions or ions+electrons from the latter into the former, and application of a second, opposite polarity electric field will “pull” at least some of the ions or ions+electrons out of the former layer and return them to the latter layer. Further, the donation and acceptance of the charged species is reversible and can be modulated for extremely long time periods and for millions of cycles.
[0048] According to the invention, the performance of memory cells or devices is a function of the conductivity modulation characteristics of the material(s) of the active layer. Thus, the ease with which charged species such as ions or ions+electrons are reversibly donated to the active layer (i.e., doped therein) and withdrawn therefrom determines the ease with which “programming” and “erasing” of the memory device occurs. Since this feature necessitates facile movement of the charged species, e.g., ions or ions+electrons, into and out from the active layer, the ions or ions+electrons will travel freely in the material, and thus have a tendency to return to their initial state or location under the influence of internal electrical fields (as during absence of the externally applied electrical field). Therefore, according to the invention, in order to improve the data retention characteristics of the memory devices, the interval during which relaxation occurs is controlled, i.e., the interval when the previously injected mobile ions or ions+electrons are partially displaced or move out of the active layer and return to the passive layer and the conductivity therefore decreases, is controlled. Such control may, for example, be achieved by providing at least one barrier layer for impeding motion of the charged species in the absence of an applied electrical field. Therefore, for a material to be useful as a barrier layer, it must have the property of not permitting easy travel therethrough of charged species such as ions or ions+electrons, or a property of not attracting, or even repelling, ions or ions+electrons. Thus, the barrier layer limits spontaneous movement of the charged species (i.e., movement in the absence of an externally applied electric field) between the active layer and the passive layer, thereby increasing the data retention time of the memory device. Suitable materials for use as the barrier layer according to the invention include Li3N and LiAlF4.
[0049] According to the invention, a layer stack is formed which comprises at least one active layer and at least one passive layer, and optionally including at least one barrier layer. The layer stack is sandwiched between a pair of electrically conductive electrodes which serve as electrical connections for supplying the requisite externally applied electrical fields. Suitable electrically conductive materials for use as electrodes include metals, metal alloys, metal nitrides, oxides, sulfides, carbon, and polymers, including for example: aluminum (Al), silver (Ag), copper (Cu), titanium (Ti), tungsten (W), their alloys and nitrides, amorphous carbon, transparent oxides, transparent sulfides, and organic polymers. The work functions of the particular materials utilized for the electrodes determines the ease with which charged species are injected into the device under the influence of the applied electric field, and in turn, affects the memory function of the device, i.e., the speed at which the device can be programmed, read, and erased, as well as the amount of electrical power required to perform these functions. In addition, one of the electrodes may, in some instances, serve as a reactant material for forming the passive layer of the device.
[0050] Referring now to FIGS. 1(A)-1(B), shown therein, in schematic, partially cut-away perspective view, is an example of a two-layer memory device 10 according to the invention for illustrating the principle of conductivity modulation. As illustrated, memory device 10 comprises an upper electrode 1 and a lower electrode 2 with a layer stack interposed therebetween, comprised of an upper, active layer 3 (bounded on opposite vertically extending sides by encapsulation layer 9) in contact with upper electrode 1 and a lower, passive layer 5 in contact with lower electrode 2. Passive layer 5 is a source (i.e., donor) and acceptor of a charged species, illustratively (but not limitatively) positively charged ions 6 (typically metal ions) and active layer 3 is a poorly electrically conducting material (e.g., an insulator) including a plurality of micro-channels or pores 7 extending generally vertically between passive layer 5 and upper electrode 1 for facilitating injection and transport of the ions 6 in the active layer 3. Thus, FIG. 1(A) illustrates the condition of memory device 10 when in the high resistance, low conductivity “off” state, i.e., no applied electric field, with ions 6 essentially confined to passive layer 5 and the micro-channels or pores 7 substantially devoid of ions 6; whereas FIG. 1(B) illustrates the condition of memory device 10 when in the low resistance, high conductivity “on” state, i.e., after application of an electric field of polarity and strength sufficient to cause ions 6 from the passive layer 5 to be injected (donated) into the micro-channels or pores 7 of the active layer 3 to form electrically conductive “nano-wires” 8. (In this regard, it should be noted that some ions 6 may be present within micro-channels or pores 7 when device 10 is in the “off” state; however, the amount of ions is insufficient to establish electrically conductive “nano-wires” 8).
[0051] Adverting to FIG. 2, shown therein is a current (I)-voltage (V) plot for illustrating operation of memory devices according to the invention. Starting at the origin of the plot (i.e., V and I=0), the voltage (V) applied to a device in the “off” (insulating, high resistance, or low conductivity) state is initially increased along curve 1. When the applied voltage reaches the programming threshold voltage VT, typically in the range 0.5-4 V, the device quickly switches from the high resistance “off” state along curve 2. During programming, ions from the passive layer are mobilized by the applied electric field, injected into the active layer, and arranged into conductive micro-channels (as shown in FIG. 1(B)). The sharp decrease in resistance corresponds to the point at which formation of the electrically conductive micro-channels is complete, thereby providing a low resistance.
[0052] The memory device can be read at any voltage below the threshold voltage VT, i.e., the “read region”. Thus, a low voltage may be utilized to probe the device and check its resistance, wherein a low current indicates the device is in the high resistance, “off” state, and a high current indicates the device is in the low resistance, “on” state. The “read” operation is non-destructive and does not disturb the state of the device.
[0053] From the low resistance state, the applied voltage may be reduced towards 0 V along curve 3. The slope of the I-V curve indicates the memory device is in the low resistance state, since the steeper the slope of the I-V curve, the lower the resistance. The difference between the “on” and “off” states is termed the “on/off ratio”, which may be as high as 9 orders of magnitude for the inventive devices, i.e., from several M′Ωto ˜100-200′Ω, but typically is ˜4-6 orders of magnitude.
[0054] With the device in the low resistance “on” state, erase may be performed by applying an increasingly negative voltage (along curve 3) until the erase threshold voltage VEis reached, at which point the device rapidly switches back to the high resistance “off” state along curve 4. Erase threshold voltages VEare typically in the same range as programming threshold voltages VT, but can be tuned depending upon the choice of materials for the active and passive layers, electrodes, and layer thicknesses. In conceptual terms, an erase operation corresponds to the removal of a minimum amount of charged species, e.g., ions from the micro-channels or pores sufficient to interrupt continuity of the conductive nano-wires. As a consequence, only a small number of ions needs to be removed from the micro-channels or pores to effectively sever the conductive wire and thereby increase the resistance.
[0055] Referring to FIG. 3, which is a plot of voltage (V) and current (I) vs. time (in nsec.) during switching of memory devices according to the invention from a high resistance “off” state (corresponding to a logical 0) to a low resistance “on” state (corresponding to a logical 1), it is evident that switching times are very fast, i.e., on the order of about 100 nsec., indicating high operational speed.
[0056] A variety of device constructions comprising a layer stack between a pair of vertically spaced apart first and second electrodes are possible according to the invention, as illustrated in simplified, schematic cross-sectional view in FIGS. 4-9, wherein each of the various constituent layers is comprised of one or more of the above-described materials indicated as suitable for use as that constituent layer.
[0057] FIG. 4 shows a memory device 20 according to the invention, comprising a single layer sandwiched between a pair of electrodes, i.e., a combined active layer/passive layer 3/5 (such as of LixVSe2or LixHfSe2, as described above), or a composite material comprised of a porous dielectric doped with ions or ion clusters) sandwiched between upper and lower electrodes 1 and 2;
[0058] FIG. 5 shows a memory device 30 according to the invention, comprising a layer stack sandwiched between upper and lower electrodes 1 and 2, the layer stack including an upper, active layer 3 and a lower, passive layer 5;
[0059] FIG. 6 shows a memory device 40 according to the invention, comprising a layer stack sandwiched between upper and lower electrodes 1 and 2, the layer stack including a pair of active layers 3 including a first, upper active layer 3Aand a second, lower active layer 3B, and a lower, passive layer 5;
[0060] FIG. 7 shows a memory device 50 according to the invention, comprising a layer stack sandwiched between upper and lower electrodes 1 and 2, the layer stack including an upper, active layer 3 and a lower, passive layer 5, with a barrier layer 4 inserted between the upper, active layer 3 and the lower, passive layer 5;
[0061] FIG. 8 shows a memory device 60 according to the invention, comprising a layer stack sandwiched between upper and lower electrodes 1 and 2, the layer stack including a pair of active layers 3 including a first, upper active layer 3Aand a second, lower active layer 3B, a barrier layer 4 inserted between the first, upper active layer 3Aand the second, lower active layer 3B, and a lower passive layer 5; and
[0062] FIG. 9 shows a memory device 70 according to the invention, comprising a layer stack sandwiched between upper and lower electrodes 1 and 2, the layer stack including a first, upper passive layer 5A, a pair of active layers 3 including a first, upper active layer 3Aand a second, lower active layer 3B, a barrier layer 4 inserted between the first, upper active layer 3Aand the second, lower active layer 3B, and a second, lower passive layer 5B.
[0063] The thickness of each of the constituent layers of each of the embodiments illustrated in FIGS. 4-9 are as follows:
[0064] first and second electrically conductive electrodes 1 and 2: from about 3,000 to about 8,000 Å, with 5,000 Å presently preferred;
[0065] active layer 3 or active layers 3Aand 3B: from about 50 to about 1,000 Å thick, with 100 Å presently preferred;
[0066] passive layer 5 or passive layers 5Aand 5B: from about 20 to about 100 Å thick, with 50 Å presently preferred; and
[0067] barrier layer 4: from about 20 to about 300 Å thick, with 50 Å presently preferred.
[0068] Each of the constituent layers may be prepared according to conventional techniques and methodologies and, for brevity's sake, details are not provided herein, except as noted below and in examples 1-17 described below:
[0069] the electrodes are formed via conventional thin film deposition techniques, e.g., thermal evaporation, sputtering, e-beam evaporation, etc.;
[0070] the passive layer may be formed by conventional thin film deposition techniques such as thermal evaporation, CVD, spin coating, or by first depositing a layer of a metal ultimately included in the passive layer, e.g., by reacting an initially formed Cu layer with a S, Se, or Te-containing gas or liquid to form a layer of a reaction product, e.g., Cu2S or Cu2Se in contact with the Cu layer;
[0071] porous active layers, such as porous Si or organic materials may be formed according to well-known thin film deposition techniques, such as thermal evaporation, spin coating, CVD, etc. Preferable pore sizes are 10-100 Å, with 30 Å preferred;
[0072] active layers comprising electrolyte clusters, i.e., groups of particles with 10-100 Å sizes may be introduced into the pores of porous Si or SiO2in a concentration of about 10-30% by dipping the porous Si or SiO2in a saturated electrolyte solution, followed by evaporation of the solvent to yield particles, i.e., clusters, of electrolyte.
[0073] materials such as refractory metal selenides, etc. may be formed by thermal CVD of gaseous precursors; e.g., HfSe2may be prepared by CVD from HfCl4and H2Se.
Example 1
[0074] Ti/LixVSe2/Al (or Ti), wherein LixVSe2serves as a combined active+passive layer (as in FIG. 4). The first, or lower electrode of Ti or Al was vapor deposited on the surface of an insulating layer at a thickness of about 3,000-8,000 Å, preferably about 5,000 Å. The LixVSe2combined active+passive layer was deposited via CVD at a thickness of about 50-300 Å, preferably about 100 Å, with Li ions intercalated by treatment with a solution of n-butyl lithium in hexane. The second, or upper electrode of Ti or Al was vapor deposited on the LixVSe2layer at a thickness of about 3,000-8,000 Å, preferably about 5,000 Å.
Example 2
[0075] Ti/LixTiS2/VSe2/Al (or Ti), wherein LixTiS2serves as a passive layer and VSe2serves as an active layer (as in FIG. 5). This cell was fabricated in similar manner as Example 1, except that the VSe2active layer was deposited by CVD on the surface of the LixTiS2passive layer prior to deposition of the second, upper electrode. The thickness of the VSe2active layer was about 50-300 Å, preferably 100 Å.
Example 3
[0076] Ti/LixVSe2/HfSe2/Al (or Ti), wherein LixVSe2serves as a passive layer and HfSe2serves as an active layer, each layer being deposited via CVD.
Example 4
[0077] Ti/LixVSe2/Li3N3/HfSe2/Al (or Ti), wherein LixVSe2serves as a passive layer, Li3N serves as a barrier layer, and VSe2serves as an active layer (as in FIG. 7). The Li3N barrier layer may also be deposited via CVD and is about 20-100 Å thick, preferably about 50 Å thick.
Example 5
[0078] Ti/LixTiS2/a-Si/Al (or Ti), similar to Example 2, except for an amorphous silicon (a-Si) active layer (formed by CVD) substituted for VSe2.
Example 6
[0079] Ti/LixTiS2/p-Si/Al (or Ti), similar to Example 5, except for a porous silicon (p-Si) active layer (formed by CVD) substituted for a-Si.
Example 7
[0080] Ti/LixTiS2/p-SiO2/Al (or Ti), similar to Examples 5 and 6, except for a porous silicon dioxide (p-SiO2) active layer (formed by CVD or from a sol-gel of tetraethoxyorthosilicate, TEOS) substituted for a-Si or p-Si.
Example 8
[0081] Ti/Cu2−xS/p-SiO2/Al (or Ti), similar to Example 7, except that Cu2−xS (preferably Cu1.8S) is substituted for LixTiS2as a passive layer. The Cu2−xS passive layer may be formed by first depositing (e.g., vapor depositing) an about 100-300 Å thick layer of Cu (150 Å presently preferred) on the surface of the lower electrode (Ti), followed by an about 15 min. treatment of the Cu layer with H2S gas in a chamber at room temperature for reaction to form Cu2−xS.
Example 9
[0082] Ti/Cu2−xS/Cu2O/Al (or Ti), similar to Example 8, except that CuO is substituted for p-SiO2as an active layer. The Cu2−xS passive layer is first formed by depositing (e.g., vapor depositing) an about 200-400 Å thick layer of Cu (250 Å presently preferred) on the surface of the lower electrode (Ti), followed by an about 10 min. treatment of the Cu layer with H2S gas in a chamber at room temperature for reaction to form Cu2−xS. The Cu2−xS layer is then reacted with O2gas in a chamber for about 10 min. to form a layer of Cu2O over the layer of Cu2−xS.
Example 10
[0083] Ti/Cu2−xSe/p-SiO2/Al (or Ti), similar to Example 8, except that Cu2−xSe is substituted for Cu2−xS as the passive layer by using H2Se gas in place of H2S for reaction with the initially deposited Cu layer.
Example 11
[0084] Ti/Ag2S/p-SiO2/Al (or Ti), similar to Example 8, except that Ag2S is substituted for Cu2−xS as the passive layer. The Ag2S passive layer may be formed by first depositing (e.g., vapor depositing) an about 100-300 Å thick layer of Ag (150 Å presently preferred) on the surface of the lower electrode (Ti), followed by about 15 min. reaction with H2S in a chamber at room temperature to form Ag2S.
Example 12
[0085] Ti/Cu2−xS/BN/Al (or Ti), similar to Example 8, with an about 50-300 Å thick layer of CVD-deposited BN (100 Å presently preferred) substituted for p-SiO2as the active layer.
Example 13
[0086] Ti/Cu2−xS/C3N/Al (or Ti), similar to Example 8, with an about 50-300 Å thick layer of CVD-deposited, amorphous C3N (100 Å presently preferred) substituted for p-SiO2as the active layer.
Example 14
[0087] Ti/Cu2−xS/BaTiO3/Al (or Ti), similar to Example 8, with an about 50-300 Å thick layer of CVD-deposited, ferroelectric BaTiO3(100 Å presently preferred) substituted for p-SiO2as the active layer.
Example 15
[0088] Ti/Cu2−xS/polyester/Al (or Ti), similar to Example 8, with an about 50-300 Å thick layer of spin-coated polystyrene (100 Å presently preferred) substituted for p-SiO2as the active layer.
Example 16
[0089] Ti/CuWO3/p-Si/Al (or Ti), similar to Example 6, except that CuWO3is substituted for LixTiS2as the passive layer. The CuWO3passive layer may be formed by first depositing (e.g., vapor depositing) an about 100-300 Å thick layer (150 Å presently preferred) of tungsten (W) on the surface of the lower (Ti) electrode, and reacting the W layer with O2gas in a chamber for about 10 min. to form a layer of WO3. A layer of CuI is then spin-coated onto the layer of WO3and the combination reacted at about 150° C. to form CuxWO3.
Example 17
[0090] Ti/Cu—CuI/p-Si/Al (or Ti), similar to Example 6, except that Cu—CuI is substituted for LixTiS2as the passive layer. The Cu—CuI passive layer may be formed by first depositing (e.g., vapor depositing) an about 100-300 Å thick layer (150 Å presently preferred) of copper (Cu) on the surface of the lower (Ti) electrode, followed by spin-coating a layer of CuI on the Cu layer.
Example 18
[0091] Cu/Cu2−xS/p-SiO2/Al (or Ti), similar to Example 8, except that the first electrode is made of Cu rather than Ti.
Example 19
[0092] Ag/Ag2S/p-SiO2/Al (or Ti), similar to Example 11, except that the first electrode is made of Ag rather than Ti.
[0093] The above-described illustrative, but non-limitative examples of memory devices or cells fabricated according to the inventive concept and methodology reflect the extreme flexibility and versatility with regard to device structures and materials selection afforded by the present invention. Inasmuch as the read, write, and erase characteristics of the inventive devices are readily amenable to variation by means of appropriate selection of materials and layer thicknesses, the inventive devices are well suited for use in a variety of applications currently employing conventional semiconductor-based memory devices. Moreover, the inventive memory devices are readily fabricated in cost-effective manner utilizing conventional manufacturing technologies.
[0094] In the previous description, numerous specific details are set forth, such as specific materials, structures, reactants, processes, etc., in order to provide a better understanding of the present invention. However, the present invention can be practiced without resorting to the details specifically set forth. In other instances, well-known processing materials, structures, and techniques have not been described in detail in order not to unnecessarily obscure the present invention.
[0095] Only the preferred embodiments of the present invention and but a few examples of its versatility are shown and described in the present invention. It is to be understood that the present invention is capable of use in various other embodiments and is susceptible of changes and/or modifications within the scope of the inventive concept as expressed herein.
Claims
What is claimed is:
1. A method for forming a reversibly programmable memory comprising at least one memory cell, the method comprising:
forming a first conductive electrode layer made of copper;
exposing the first conductive electrode layer to a gas suitable to form a passive layer including copper sulfide on the first conductive electrode layer, the passive layer being a superionic material adapted to reversibly donate and accept charged species, the charged species including ions or ions and elections;
forming an active layer including an organic polymer over the passive layer, the organic polymer having a reversibly variable electrical conductivity upon the introduction and removal of charged species from the passive layer, the organic polymer having a relatively lower electrical conductivity when free of charged species and a relatively higher electrical conductivity when charged species are introduced into the organic polymer; and
forming a second conductive electrode layer over the active layer.
2. The method of claim 1, wherein exposing the first conductive electrode layer comprises:
exposing the first conductive electrode layer to hydrogen sulfide gas suitable to form the passive layer including copper sulfide.
3. The method of claim 1, wherein the active layer comprises polystyrene.
4. The method of claim 1, wherein forming an active layer comprises:
forming a layer of the organic polymer having a thickness from about 50 to about 1000 Angstroms.
5. The method of claim 1, wherein exposing the first conductive electrode layer comprises:
forming the passive layer to have a thickness from about 20 to about 100 Angstroms.
6. The method of claim 1, further comprising:
forming a barrier layer including a material that impedes spontaneous movement of charged species between the active layer and the passive layer when an electrical potential difference is not applied between the first and second conductive electrode layers.
7. The method of claim 6, wherein the barrier layer is positioned between the active layer and the passive layer.
8. The method of claim 1, wherein the memory cell includes only one active layer and only one passive layer between the first and second conductive electrode layers.
9. The method of claim 1, further comprising:
applying an electric field to the first and second conductive electrode layers to transfer charged species from the passive layer to polymer material in the active layer, thereby one of doping the polymer charged species from the passive layer and forming nanowire features in the polymer to store information in the memory cell.
10. The method of claim 9, wherein applying the electric field comprises:
doping the polymer with charged species from the passive layer to store information in the memory cell.
11. The method of claim 9, wherein applying the electric field comprises:
forming nanowire features in the polymer to store information in the memory cell.
12. The method of claim 1, wherein the first and second conductive electrode layers are arranged to both program the memory cell to store information and read stored information from the memory cell.
13. The method of claim 1, wherein the memory cell includes only two conductive electrode layers.
14. A method for operating a reversibly programmable memory comprising at least one memory cell, the method comprising:
providing a memory cell having a stacked layer structure with first and second conductive electrode layers, and two layers between the first and second conductive electrode layers including an active layer and a passive layer, the first and second conductive electrode layers being suitable to program the memory cell to store information and read stored information from the memory cell, the active layer being an organic polymer that has a reversibly variable electrical conductivity upon the introduction and removal of charged species (ions and ions and electrons) from the passive layer, the organic polymer having a relatively lower electrical conductivity when free of charged species and a relatively higher electrical conductivity when charged species are introduced, the passive layer being a superionic material that has ion and electron conductivity; and
applying an electric field to the first and second conductive electrode layers to transfer charged species from the passive layer to polymer material in the active layer, thereby one of doping the polymer with charged species from the passive layer and forming nanowire features in the polymer to store information in the memory cell.
15. The method of claim 14, wherein applying the electric field comprises:
doping the polymer with charged species from the passive layer to store information in the memory cell.
16. The method of claim 15, wherein providing the memory cell comprises:
providing the passive layer with copper sulfide; and applying the electric field comprises:
transferring charged species from the copper sulfide to the polymer.
17. The method of claim 14, wherein applying the electric field comprises:
forming nanowire features in the polymer to store information in the memory cell.
18. The method of claim 14, wherein providing the memory cell comprises:
providing the passive layer with copper sulfide.
19. The method of claim 14, wherein providing the memory cell comprises:
forming the first conductive electrode layer made of copper; and
exposing the first conductive electrode layer to a gas suitable to form the passive layer including copper sulfide.
20. The method of claim 19, wherein exposing the first conductive electrode layer comprises:
exposing the first conductive electrode layer to hydrogen sulfide gas suitable to form the passive layer including copper sulfide.
21. The method of claim 19, wherein providing the memory cell comprises:
forming the active layer of organic polymer over the passive layer; and
forming the second conductive electrode layer over the active layer.
22. A method for forming a reversibly programmable memory comprising at least one memory cell, comprising:
forming a first conductive electrode layer comprising copper;
exposing the first conductive electrode layer to a gas suitable to form a passive layer comprising copper sulfide on the first conductive electrode layer, the passive layer being a superionic material adapted to reversibly donate and accept charged species, the charged species comprising at least one of ions and electrons, the passive layer having a thickness from about 20 to about 100 Angstroms;
forming an active layer comprising an organic polymer over the passive layer, the organic polymer having a reversibly variable electrical conductivity upon the introduction and removal of charged species from the passive layer, the organic polymer having thickness from about 50 to about 1,000 Angstroms and a relatively lower electrical conductivity when free of charged species and a relatively higher electrical conductivity when charged species are introduced into the organic polymer; and
forming a second conductive electrode layer over the active layer.
23. The method of claim 22, wherein exposing the first conductive electrode layer comprises exposing the first conductive electrode layer to hydrogen sulfide gas.
24. The method of claim 22, wherein the active layer is formed by spin-coating.
25. The method of claim 22, wherein the active layer comprises a plurality of channels therethrough for facilitating movement of the charged species.
26. The method of claim 22, wherein the active layer comprises a plurality of pores therethrough for facilitating movement of the charged species.
27. The method of claim 22, wherein the first conductive electrode layer has a thickness from about 3,000 to about 8,000 Angstroms.
28. The method of claim 22, wherein the second conductive electrode layer has a thickness from about 3,000 to about 8,000 Angstroms.
29. The method of claim 22 further comprising forming a barrier layer between the first conductive electrode layer and the second conductive electrode layer.
30. The method of claim 22, wherein the barrier layer has a thickness from about 20 to about 300 Angstroms.
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