Memory Test Device With Write and Pseudo Write Signals

This invention relates to a memory device, and especially to a semiconductor memory device fabricated on a semiconductor substrate.

Generally, the operation margin of a semiconductor memory device including a plurality of memory cells is measured by measuring the operation limit of the memory device when the memory device is operated under heavy input conditions beyond the normal one and an excessive power source voltage. With a recent tendency of the large memory capacity of the memory device, a variation in the performances of the memory cells manufactured is unavoidable. For this the operation margin of the memory device is narrowed particularly for the change of ambient or chip temperature. Adversely, the above-described operation margin check at room temperature, for example, 25.degree. C., frequently fails to detect defective cells with poor operation margin. Practically, it is very difficult to find or check such defective memory cells by changing the ambient temperature. Therefore, it is desired to find the defective cells at room temperature.

Accordingly, an object of the invention is to provide a semiconductor memory device with an electric circuit means which enables to detect defective memory cells with temperature-dependance at room temperature.

The invention is based on a discovery that such a defective memory cell already has poor operation margin in the holding state at room temperature and data may readily be written into such a cell by slightly shifting the write voltage from the normal one.

According to one aspect of the invention, there is provided a memory device including a plurality of memory cells, a selection circuit for the memory array, and a write control circuit which operates in a first mode to write data into a selected memory cell and in a second mode to write nothing into at least one of the memory cells when it is normal but write data into the memory cell when it is abnormal.

According to another aspect of the invention, there is provided a semiconductor memory device comprising a memory array including a plurality of memory cells, a selection circuit for the memory array, and a write control circuit which operates in a normal operation mode to write data into a selected memory cell and in a psuedo-write mode on a test mode to write nothing into the memory cell when it is abnormal.

According to still another aspect of the invention, there is provided a semiconduct memory device comprising a memory array including a plurality of memory cells each disposed at an intersection of row and column, a row selection circuit, a column selection circuit and a write control circuit which operates in a normal operation mode to write data into a selected memory cell, and in a test operation mode in which the signals for energizing the row lines within the row selection circuit have substantially the same level and the pseudo-write operation is performed in such a way that, when the memory cells along the column line selected are normal, the data already written into the memory cells of the selected column is not changed, while, when those cells include a defective memory cell or memory cells, the data already written into the memory cell of cells is changed.

Yet in another aspect of the invention, there is provided a semiconductor memory device of which the memory cell includes a flip-flop arrangement having cross-coupled bipolar transistors and a pair of load elements, wherein a voltage across the load element of the transistor now being turned on determines if the memory cell is normal or abnormal.

According to this invention, there is provided a memory device characteristically comprising a first write control circuit which operates in a normal write mode and a second write control circuit which operates in a pseudo write mode to supply a pseudo write signal lower than a threshold value at which the state of the normal memory cell is changed or inverted to the memory cell. In such a pseudo write mode, the state of the memory cell remains unchanged, but if the tested memory cell is abnormal, its state is changed. After the pseudo write mode, it can be checked by reading out the state of the memory cell whether the memory cell is normal or abnormal.

According to this invention, there is also provided a memory device comprising a plurality of memory cells, selection means for selecting one of said memory cells, first write control means which operates in a normal write mode and second write control means which operates in a pseudo write mode to supply a signal lower than a threshold value at which the state of the normal memory cell is inverted, to the memory cell to be tested.

According to this invention, there is also provided a memory device comprising a plurality of memory cells, selection means for selecting one of said memory cells, first write means for supplying a write signal of a normal logic level to selected one of the memory cells, and second write means for supplying pseudo write signal of a logic level lower than the normal logic level to at least the selected one of the memory cells.

Furthermore, according to the invention, there is provided a method for checking a memory device including a plurality of memory cells, comprising the steps of writing the same and one logic data into memory cell to be checked by supplying a write signal having normal logic level, thereto, supplying pseudo data of a logic level smaller than a threshold value at which the content of the normal memory cell is changed, to the memory cell to be checked, thereafter reading out the content of the memory cell to be checked, and detecting whether respective contents of the memory cell written by the writing step has been changed or not, thereby determining abnormal memory cells.

This invention will be better understood from the following description taken in connection with the accompanying drawings, in which:

FIG. 1 shows a block diagram of a conventional memory circuit;

FIG. 2 shows a block diagram of an embodiment of a memory circuit according to the invention;

FIG. 3 shows wave forms for illustrating the operation of the memory circuit shown in FIG. 2, in which

FIG. 3(a) a wave form for illustrating normal read and write operations and

FIG. 3(b) shows a wave form for illustrating operations at a test mode (pseudo-write) according to the invention;

FIG. 4 shows a circuit diagram of an embodiment of the circuit for providing control signals W'.sub.c1 and W'.sub.c0 ;

FIG. 5 shows a circuit diagram of another embodiment of the memory device according to the invention; and

FIG. 6 shows a circuit diagram of still another embodiment of the memory device according to the invention.

A conventional memory device employing bipolar transistors will be described with reference to FIG. 1. A memory array of 2 rows.times.2 columns will be used for the explanation to be given for simplicity. Of those memory cells C.sub.11, C.sub.12, C.sub.21 and C.sub.22, the memory cell C.sub.11 has load resistors R.sub.0 and R.sub.1 and multi-emitter transistors Q.sub.01 and Q.sub.02. Those transistors Q.sub.01 and Q.sub.02 are cross-coupled in a manner that the base of one of the transistors is connected to the emitter of the other while the emitter of the former to the base of the latter. In the memory cell C.sub.11, the emitters E.sub.2 and E.sub.3 of those transistors are connected to digit lines D.sub.0 and D.sub.1, and the emitters E.sub.0 and E.sub.1 are commonly connected to a line W'.sub.1 connecting to a current source IH.sub.1. The remaining memory cells C.sub.12, C.sub.21 and C.sub.22 have each the same construction as that of the memory cell C.sub.11 as mentioned above. Accordingly, no explanation of those remaining ones will be referred to.

A row selection circuit 1 has a transistor Q.sub.11 connecting at the emitter to a row line W.sub.1 called as a word line and at the base to a terminal W.sub.T1, a transistor Q.sub.12 connecting at the emitter to a row line W.sub.2 and at the base to a terminal W.sub.T2 and a couple of current sources IH.sub.1 and IH.sub.2. The row selection circuit 1 thus constructed selectively energizes row lines W.sub.1 and W.sub.2.

A column selection circuit 2 has transistors Q.sub.21 and Q.sub.22 which are respectively connected at their emitters to digit lines D.sub.0 and D.sub.1 and at their bases to a terminal D.sub.s1 and transistors Q.sub.23 and Q.sub.24 which are respectively connected at their emitters to digit lines D.sub.2 and D.sub.3 and at their base to a terminal D.sub.s2.

A read/write control circuit 3 has a transistor Q.sub.31 connecting at the emitter to the digit line D.sub.0 which cooperates with the transistor Q.sub.01 of the memory cell C.sub.11 also connecting at its emitter to form a current switch circuit for switching current. Similarly, transistors Q.sub.32, Q.sub.33 and Q.sub.34 are connected at their emitters to digit lines D.sub.1, D.sub.2 and D.sub.3, which cooperate with the transistors also connecting at their emitters to the digit lines D.sub.1, D.sub.2 and D.sub.3 to form current switch circuits for switching currents, respectively. The write operation and the read operation into and out of the memory cells are performed through a current switching logic by using control signals W.sub.c0 and W.sub.c1. At this time, a power source at high potential is applied to terminals a and b coupled to the inputs of an operational amplifier 4.

In writing "0" into the memory cell C.sub.11, for example, a high level signal is applied to the row selection terminal W.sub.T1 and a low level signal is applied to the column selection input terminal D.sub.s1. At this time, non-selection level signals are applied to the remaining input terminals W.sub.T2 and D.sub.s2. In this way, the low and high level signals are respectively applied to the selection lines terminal D.sub.s1 and the terminal W.sub.T1 to select the memory cell C.sub.11. Then, a low level signal is applied to the write terminal W.sub.c1 and a high or medium level signal is applied to the write terminal W.sub.c0, thereby to cause current to flow through the emitter E.sub.3.

In the read operation, the row and column lines are selected in a similar way to that in the write operation mentioned above. A medium level signal, however, is applied to the input terminals W.sub.c1 and W.sub.c0. When a memory cell is not selected, a holding current I.sub.H for a single cell flows through the load resistor R.sub.0 or R.sub.1 of the conductive transistor. When it is selected, the holding current I.sub.H and a digit current I.sub.D0 (or I.sub.D1) flows through the load resistor. Thus the memory cell, when it is not selected, is held by only the hold voltage V.sub.H =R.sub.0 .times.I.sub.H (or R.sub.1 .times.I.sub.H). In order to avoid the erroneous write into the memory cell C.sub.21 when the write operation is performed into the memory cell C.sub.11, the low level at the write terminal W.sub.c0 (W.sub.c1) must be set to be much higher than the level which is lower than the low level of the row selection terminal W.sub.T1 (W.sub.T2) by the holding voltage V.sub.H. And it must be substantially equal to the normal low level at the row selection terminal W.sub.T1 (W.sub.T2).

The problem is that memory cells with abnormally low holding voltage are included in the memory cells forming the memory array. Such memory cells often operate normally at a room temperature, even through those abnormally operate when it is operated over a whole range of temperature. For this reason, there has never been a method to effectively detect such defective cells at a room temperature.

The inventor has discovered that, in the memory cell which normally operates at a room temperature but erroneously inverts its state at 0.degree. C. This is due to the fact that at least one of the transistors forming such a cell has the base-emitter voltage V.sub.BE larger than that of the normal cell by about 20 mV in absolute value. Particularly, the erroneous inversion of the cell state tends to occur when the transistor with the larger voltage V.sub.BE conducts. Let us study this in detail by using a case where M (a positive integer) pieces of memory cells are connected to a word line (W) and, in one of those memory cells, one of the transistors has a large base-emitter voltage V.sub.BE. If all of the M pieces of memory cells operate normally, each cell is held by the current I.sub.hold /M, which is 1/M of the total current I.sub.hold of the current source (IH.sub.1). At this time, the holding voltage V.sub.H of each memory cell is approximately V.sub.H =R.times.I.sub.hold /M (R is resistance of the load resistor of each memory cell). When the voltage V.sub.BE of the transistor of one memory cell is large, the holding voltage of the memory cell is reduced by the voltage by which the voltage V.sub.BE is larger than the normal one. The holding voltages of the remaining M-1 pieces of cells remain unchanged.

As a result, when the memory cells with the reduced holding voltages are subjected to the read operation at a low temperature, the contents of the memory cell is inverted or, even though it is not selected, data is erronously loaded into it.

An embodiment of a semiconductor memory device according to the invention will be described with reference to FIG. 2 and FIGS. 3(a) and 3(b). As shown, the semiconductor memory device of the invention uses a pseudo-write control circuits 5 which produces write signal W'.sub.c0 and W'.sub.c1 in accordance with the level of a signal applied to a control terminal TC. The write signal W'.sub.c0 and W'.sub.c1 is applied to the base of the transistor Q.sub.31 and Q.sub.32. More specifically, when the signal appearing at the terminal T.sub.c is logical "1" (high level), the control circuit 5 produces the signals W'.sub.c0 and W'.sub.c1 with levels for pseudo-write mode which is described later. When the signal at the terminal T.sub.c is logical "0" (low level), the control circuit 5 produces the signals W'.sub.c0 and W'.sub.c1 with the level for the normal write mode such as in FIG. 1.

The normal write mode will be described with reference to FIG. 3(a). In the normal write mode, the signal at the terminal T.sub.c is logical "0". During the read period T.sub.R1, the control signals W'.sub.c0 and W'.sub.c1 are at the medium level. At this time, the transistor Q.sub.02 is non-conductive and the potential C.sub.02 at the collector thereof is high in level, while the transistor Q.sub.01 is conductive with the collector having a low level potential C.sub.01. Then, during the write period T.sub.w1, the control signal W'.sub.c0 is high in level and the signal W'.sub.c1 is low. Accordingly, the base potential (W'.sub.c0) of the transistor Q.sub.31 is high thereby to turn on the transistor Q.sub.31 and to turn off the transistor Q.sub.01. At the same time, the transistor Q.sub.32 is turned off because the signal W'.sub.c1 is low while the transistor Q.sub.02 is turned on. As a result, the state of the memory cell C.sub.11 is reversed and the reversed state is sustained during the succeeding read period T.sub.R2.

The pseudo-write mode essential to the invention will be described with reference to FIG. 3(B). Assume that the transistor Q.sub.01 is ON while the transistor Q.sub.02 is OFF in the selected memory cell. During the succeeding pseudo-write period T'.sub.W, the control signal W'.sub.c0 is high in level. Accordingly, the base potential of the transistor Q.sub.31 is higher than the collector potential C.sub.02 of the transistor Q.sub.02. In this case, the transistor Q.sub.02 has the abnormally large base-emitter voltage V.sub.BE. Such a large V.sub.BE reduces a potential difference between C.sub.01 and C.sub.02, i.e. holding voltage. As a result, the transistor Q.sub.31 is ON while the transistor Q.sub.01 is going to be OFF. At this time, if the level of the control signal W'.sub.c1 is so determined that data is written not into a memory cell having a normal holding voltage but into a memory cell having a very small holding voltage, i.e., if the potential of the control signal W'.sub.c1 is selected to be approximately equal to the abnormal holding voltage of the defective memory cell, the transistor Q.sub.02 is conductive to allow inverse writing into the memory cell when the memory cell has holding voltage smaller than the abnormal holding potential, as indicated by the collector potential C'.sub.01.

On the other hand, when the memory cell has the normal holding voltage, the transistor Q.sub.02 is kept non-conductive, and the condition of the memory cell is not inverted, as indicated by the normal collector potential C.sub.01.

As described above, in the test of the memory device, the levels of the signals W'.sub.c1 and W'.sub.c0 are switchable between the normal levels (FIG. 3(a)) and the above mentioned test levels in accordance with the external signal from the terminal TC. In the normal levels, the same logic "1" or "0" is loaded into all of the memory cells of the memory device. Then, the levels W'.sub.c1 and W'.sub.c2 are switched to the test level and the content which is an inverse of that loaded by the normal level is loaded into the memory cells in the pseudo-write mode (FIG. 3(b)). Then, all the contents of the memory cells are read out by the normal levels of the signals W'.sub.c1 and W'.sub.c0. In this case, the contents of the memory cells which have been loaded by the normal levels, read out from the memory device having the memory cells with the normal holding voltage are not inverted. In the memory device including defective memory cells with the abnormal holding voltage, the contents read out from the detective memory cells are inverted. Depending on the result of the test, a memory device having defective memory cells can be detected and thereby removed.

In order to more effectively conduct the memory device test, the level of the signal W'.sub.c0 (W'.sub.c1) which is high at the time of the test must be set to be higher than the high level (at the time of the selection) of the signal at the terminal W.sub.T1 (W.sub.T2) so that the current I.sub.D is not shunted into the transistor being conductive of the memory cell. When the current I.sub.D is shunted into the cell, a large holding voltage appears across the collector resistor of the conductive transistor. The holding voltage hinders the pseudo-write into the defective cells.

Turning now to FIG. 4, there is shown an embodiment of a circuit to produce the control signals W'.sub.c1 and W'.sub.c0 in the pseudo-write mode. As shown, a transistor Q.sub.A and the emitter resistor R.sub.A are inserted between ground and a power source V.sub.BE to form an emitter follower circuit. A level generator 10 is provided to supply selectively a signal of two-value to the base of the transistor Q.sub.A. In the level generator 10, resistor R.sub.B and R.sub.C serially connected between ground and the power source -V.sub.BE, and the resistor R.sub.B is connected in parallel with the transistor Q.sub.B. The base of the transistor Q.sub.B is biased by the resistor R.sub.D and is connected to an output terminal TC. In this circuit, the transistor Q.sub.A is controlled by the emitter potential of the transistor Q.sub.B which changes depending on the conduction and the non-conduction of the transistor Q.sub.B. In the normal write mode, for example, the control terminal TC is opened or placed at -V.sub.BE or "0" level to turn on the transistor Q.sub.B. The voltage determined by the resistance ratio between the resistors R.sub.B and R.sub.C at this time is applied to the base of the transistor Q.sub.A. The conductivity of the transistor Q.sub.A at this time is small, so that the level of the signal W'.sub.c1 is approximately -V.sub.BE. In the pseudo-write mode, the transistor Q.sub.B is turned on by grounding the terminal TC. As a result, the base potential of the transistor Q.sub.A rises and the resistance of the transistor Q.sub.A becomes small. Therefore, the level of the signal W'.sub.c1 is smaller than -V.sub.BE determined by the resistor R.sub.A.

In this way, the level of the control signal W'.sub.c1 is controlled. This is correspondingly applied to the control signal W.sub.c0. Evidently, the control signal generating means for generating the control signals W'.sub.c1 and W'.sub.c0 is not limited to the circuit 10 shown in FIG. 4. For the test level control, an additional test pad may be provided at the terminal TC or a third value level may additionally be produced at a terminal not used at the pseudo-write mode, or at a chip selection of the terminal with a fixed level signal, an output terminal or the like.

Therefore, the defective memory cells having the abnormal holding voltage can be effectively detected even when the memory device is at the manufacturing state of wafer or is loaded into the package.

With reference to FIG. 5, another embodiment of the semiconductor memory device according to the invention will be described. In this embodiment, the read output terminal OUT is used also as the control terminal Tc. A voltage higher than the breakdown voltage of a Zener diode ZD applied to the output terminal OUT turns on a transistor Q.sub.61 as a current source, so that a current switch circuit including transistors Q.sub.59 and Q.sub.60 is in an operating condition. The collectors of the transistors Q.sub.59 and Q.sub.60 are respectively coupled with the emitters of the transistors Q.sub.55 and Q.sub.56 as the output portion of a data input circuit 20. From the emitters of the transistors Q.sub.55 and Q.sub.56 are derived the control signals W'.sub.c0 and W'.sub.c1. Three combinations of a transistor Q.sub.54 and a resistor R.sub.54, a transistor Q.sub.57 and a resistor R.sub.55, and a transistor Q.sub.58 and a resistor R.sub.56 respectively operate as constant current sources. Bases of the transistors Q.sub.54, Q.sub.57 and Q.sub.58 are supplied with a constant voltage derived from a series circuit of a resistor R.sub.62 and diodes D.sub.5 and D.sub.6. A transistor Q.sub.62 and resistors R.sub.60 and R.sub.61 form a clamp circuit for clamping the above constant voltage. In the pseudo write mode, the above three constant current sources are disenabled by clamping the constant voltage at a low level because the transistor Q.sub.62 is made conductive in response to a high level of the cathode of the diode ZD. While a constant current source composed of a transistor Q.sub.53 and a resistor R.sub.53 is enabled in response to a level at a junction between a resistor R.sub.59 and a diode D.sub.3. Herein, the constant current value of the constant current source composed of the transistor Q.sub.53 and the resistor R.sub.53 is set smaller than that of the current source composed of the transistor Q.sub.54 and the resistor R.sub.54. The amount of the constant current of the constant current source including the transistor Q.sub.53 and the resistor R.sub.53 can be controlled over some range in response to a controlability of the contant voltage from the junction between the resistor R.sub.59 and the diode D.sub.3 by the terminal OUT. With the above construction, when the level at the output terminal OUT is within the breakdown voltage of the Zener diode ZD, that is to say, in the normal write mode, the transistors Q.sub.53, Q.sub.61 and Q.sub.62 are OFF state and hence an input signal supplied at an input terminal D.sub.in is transferred to the bases of the transistors Q.sub.31 and Q.sub.32 as signals W'.sub.c0 and W'.sub.c1 with the normal level such as shown in FIG. 3(a) through a current switching circuit including the transistors Q.sub.51, Q.sub.52 and Q.sub.54 and emitter-follower transistors Q.sub.55 and Q.sub.56. While in the pseudo-write mode, a voltage higher than the breakdown voltage of the Zener diode ZD is applied to the terminal OUT to turn on the transistor Q.sub.62 to clamp the constant voltage defined by the diodes D.sub.5 and D.sub.6 at the low level and hence the transistors Q.sub.54, Q.sub.57 and Q.sub.58 are made OFF state. At the same time, the transistor Q.sub.61 is also made conducting to enable the transistors Q.sub.59 and Q.sub.60. Thus, test levels supplied at the signal W'.sub.c0 and W'.sub.c1 are established by shifting the emitter voltages of the transistors Q.sub.55 and Q.sub.56 by the transistors Q.sub.59 to Q.sub.61 and by shifting the collector voltages of the transistors Q.sub.51 and Q.sub.52 by the transistor Q.sub.53.

With reference to FIG. 6, another embodiment of this invention will be described. A data input circuit 61 includes a current logic circuit having transistors Q.sub.71 and Q.sub.72 and emitter-follower transistors Q.sub.73 and Q.sub.74, from emitters of which the write control signals W'.sub.c0 and W'.sub.c1 are derived. Between the emitters of the transistors Q.sub.73 and Q.sub.74 and a control terminal Tc, a level shift circuit including a transistor Q.sub.75 and resistors R.sub.61 and R.sub.62 and a level shift circuit including a transistor Q.sub.75 and resistors R.sub.03 and R.sub.64 are respectively disposed. Diodes DS.sub.1 and DS.sub.2 are disposed between word lines W.sub.1 and W.sub.2 and the terminal TC. In this embodiment, a high level supplied at the terminal TC makes the memory device the pseudo-write mode wherein all the word lines are made a selection level by the diodes DS.sub.1 and DS.sub.2 and the levels W'.sub.c0 and W'.sub.c1, especially low one thereof are shifted by the circuit 60 as shown in FIG. 3(b). In this embodiment, all the memory cells are subjected to the test mode at the same time.