US 6,781,876 B2Grant

Memory device with gallium nitride or gallium aluminum nitride gate

Issue Date:2004-08-24

•32 Claims

•7 Drawing Sheets

Abstract

A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Metadata

Assignee

Micron Technology, Inc.

Inventors

Leonard Forbes
Kie Y. Ahn

Application Information

Application Number:US 10/047,181

Filing Date:2001-10-23

Priority Date:1997-07-29

Art Unit:7

Classifications

IPC:

G11C 1606

Field of Search:

36518501365185083651852536518528257315257318257 88438257

Patent Drawings (7 sheets)

Description

[0002] This application is a Continuation of U.S. Ser. No. 09/140,978 filed on Aug. 27, 1998, now issued as U.S. Pat. No. 6,307,775 on Oct. 23, 2001, which is a Divisional of U.S. Ser. No. 08/902,098, filed Jul. 29, 1997 now issued as U.S. Pat. No. 6,031,263 on Feb. 29, 2000.

FIELD OF THE INVENTION

[0003] The present invention relates generally to integrated circuit technology, including dynamic random access memories (DRAMs) and electrically erasable and programmable read only memories (EEPROMS), and partly, but not by way of limitation, to a floating gate transistor memory that is dynamically electrically alterable and programmable.

BACKGROUND OF THE INVENTION

[0004] Dynamic random access memories (DRAMs) are data storage devices that store data as charge on a storage capacitor. A DRAM typically includes an array of memory cells. Each memory cell includes a storage capacitor and an access transistor for transferring charge to and from the storage capacitor. Each memory cell is addressed by a word line and accessed by a bit line. The word line controls the access transistor such that the access transistor controllably couples and decouples the storage capacitor to and from the bit line for writing and reading data to and from the memory cell.

[0005] The storage capacitor must have a capacitance that is large enough to retain a charge sufficient to withstand the effects of parasitic capacitances, noise due to circuit operation, and access transistor reverse-bias junction leakage currents between periodic data refreshes. Such effects can result in erroneous data. Obtaining a large capacitance typically requires a storage capacitor having a large area. However, a major goal in DRAM design is to minimize the area of a DRAM memory cell to allow cells to be more densely packed on an integrated circuit die so that more data can be stored on smaller integrated circuits.

[0006] In achieving the goal of increasing DRAM array capacity by increasing cell density, the sufficient capacitance levels of the DRAM storage capacitors must be maintained. A “stacked storage cell” design can increase the cell density to some degree. In this technique, two or more capacitor conductive plate layers, such as polycrystalline silicon (polysilicon or poly), are deposited over a memory cell access transistor on a semiconductor wafer. A high dielectric constant is sandwiched between these capacitor plate layers. Such a capacitor structure is known as a stacked capacitor cell (STC) because the storage capacitor plates are stacked on top of the access transistor. However, formation of stacked capacitors typically requires complicated process steps. Stacked capacitors also typically increase topographical features of the integrated circuit die, making subsequent lithography and processing, such as for interconnection formation, more difficult. Alternatively, storage capacitors can be formed in deep trenches in the semiconductor substrate, but such trench storage capacitors also require additional process complexity. There is a need in the art to further increase memory storage density without adding process complexity or additional topography.

[0007] Electrically erasable and programmable read only memories (EEPROMs) provide nonvolatile data storage, EEPROM memory cells typically use field-effect transistors (FETs) having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.

[0008] In such memory cells, data is represented by charge stored on the polysilicon floating gates, such as by hot electron injection or Fowler-Nordheim tunneling during a write operation. Fowler-Nordheim tunneling is typically used to remove charge from the polysilicon floating gate during an erase operation. However, the relatively large electron affinity of the polysilicon floating gate presents a relatively large tunneling barrier energy at its interface with the underlying gate dielectric. The large tunneling barrier energy provides longer data retention times than realistically needed. For example, a data charge retention time at 85° C. is estimated to be in millions of years for some floating gate memory devices. The large tunneling barrier energy also increases the voltages and time needed to store and remove charge to and from the polysilicon floating gate. “Flash” EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells, require even longer erasure times to accomplish this simultaneous erasure. The large erasure voltages needed can result in hole injection into the gate dielectric. This can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. The high electric fields that result from the large erasure voltages can also result in reliability problems, leading to device failure. There is a need in the art to obtain floating gate transistors that allow the use of lower programming and erasure voltages and shorter programming and erasure times.

References

[0009] B. Dipert et al., “Flash Memory Goes Mainstream,” IEEE Spectrum, pp. 48-52 (Oct. 1993);

[0010] S.M. Sze, “Physics of Semiconductor Devices,” John Wiley & Sons, New York (1969), p. 496;

[0011] S.R. Pollack et al., “Electron Transport Through Insulating Thin Films,” Applied Solid State Science, Vol. 1, Academic Press, New York, (1969), p. 354;

[0012] D.A. Baglee, “Characteristics and Reliability of 100 Å Oxides,” Proc. 22nd Reliability Symposium, (1984), p. 152;

[0013] V.M. Bermudez et al. “The Growth and Properties of Al and AlN films on GaN” J. Appl. Physics, Vol. 79, pp. 110-119 (1996).

[0014] I. Akasaki et al. “Effects of AlN Buffer Layer on Crystallographic Structure and On Electrical and Optical Properties of GaN and Ga_1−xAl_xN Films Grown on Sapphire Substrate by MOVPE,” J. Of Crystal Growth, Vol. 98, pp. 209-19, North Holland, Amsterdam (1989);

SUMMARY OF THE INVENTION

[0015] The present invention includes a memory cell that allows the use of lower programming and erasure voltages and shorter programming and erasure times by providing a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) storage electrode for storing charge. According to one aspect of the invention, the storage electrode provides a barrier energy, with an adjacent insulator, of less than approximately 3.3 eV, which provides improved erase times or voltages.

[0016] In one embodiment, the memory cell includes a floating gate transistor, having a GaN or GaAlN floating gate. A refresh circuit allows dynamic refreshing of charge stored on the floating gate. The barrier energy can be lowered to a desired value by selecting the appropriate material composition of the floating gate. As a result, lower programming and erasure voltages and shorter programming and erasure times are obtained.

[0017] Another aspect of the present invention provides a method of using a floating gate transistor having a reduced barrier energy between a floating gate electrode and an adjacent insulator. Data is stored by changing the charge of the floating gate. Data is refreshed based on a data charge retention time established by the barrier energy between the GaN or GaAlN floating gate and the adjacent insulator. Data is read by detecting a conductance between a source and a drain. The large transconductance gain of the memory cell of the present invention provides a more easily detected signal and reduces the required data storage capacitance value and memory cell size when compared to a conventional dynamic random access memory (DRAM) cell.

[0018] The present invention also includes a method of forming a floating gate transistor. Source and dram regions are formed. A gate insulator is formed. A GaN or GaAlN floating gate is formed, such that the floating gate is isolated from conductors and semiconductors. In one embodiment, the floating gate is formed by metal organic chemical vapor deposition (MOCVD). In another embodiment, the floating gate is formed by plasma-enhanced molecular beam epitaxy (PEMBE). The GaN or GaAlN floating gate provides a relatively short data charge retention time, but advantageously provides a shorter write/programming and erase times, making operation of the present memory speed competitive with a DRAM.

[0019] The present invention also includes a memory device that is capable of providing short programming and erase times, low programming and erase voltages, and lower electric fields in the memory cell for improved reliability. The memory device includes a plurality of memory cells. Each memory cell includes a transistor. Each transistor includes a source region, a drain region, a channel region between the source and drain regions, and a GaN or GaAlN floating gate that is separated from the channel region by an insulator. The transistor also includes a control gate located adjacent to the floating gate and separated therefrom by an intergate dielectric. According to one aspect of the invention, a refresh circuit is provided. The memory device includes flash electrically erasable and programmable read only memory (EEPROM), dynamic random access memory (DRAM), and dynamically electrically alterable and programmable read only memory (DEAPROM) embodiments.

[0020] The memory cell of the present invention provides a reduced barrier energy, large transconductance gain, an easily detected signal and reduces the required data storage capacitance value and memory cell size. The lower barrier energy increases tunneling current and also advantageously reduces the voltage required for writing and erasing the floating gate transistor memory cells. For example, conventional polysilicon floating gate transistors typically require complicated and noisy on-chip charge pump circuits to generate the large erasure voltage, which typically far exceeds other voltages required on the integrated circuit. The present invention allows the use of lower erasure voltages that are more easily provided by simpler on-chip circuits. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. Alternatively, the thickness of the gate insulator can be increased from the typical thickness of a silicon dioxide gate insulator to improve reliability or simplify processing, since the lower barrier energy allows easier transport of charge across the gate insulator by Fowler-Nordheim tunneling.

[0021] According to another aspect of the invention, the shorter retention time of data charges on the GaN or GaAlN floating electrode, resulting from the smaller barrier energy, is accommodated by refreshing the data charges on the floating electrode. By decreasing the data charge retention time and periodically refreshing the data, the write and erase operations can be several orders of magnitude faster such that the present memory is speed competitive with a DRAM. In this respect, the memory operates similar to a memory cell in DRAM but avoids the process complexity, additional space needed, and other limitations of forming stacked or trench DRAM capacitors.

[0022] The memory cell of the present invention can be made smaller than a conventional DRAM memory cell. Moreover, because the storage capacitor of the present invention is integrally formed as part of the transistor, rather than requiring complex and costly non-CMOS stacked and trench capacitor process steps, the memory of the present invention should be cheaper to fabricate than DRAM memory cells, and should more easily scale downward as CMOS technology advances.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In the drawings, like numerals describe substantially similar components throughout the several views.

[0024] FIG. 1 is a simplified schematic/block diagram illustrating generally one embodiment of a memory including reduced barrier energy floating electrode memory cells.

[0025] FIG. 2 is a cross-sectional view that illustrates generally a floating gate transistor embodiment of a memory cell provided by the present invention.

[0026] FIG. 3 is an energy band diagram that illustrates generally conduction band energy levels in a floating gate transistor provided by the present invention.

[0027] FIG. 4 is a graph comparing barrier energy vs. tunneling distance for a conventional floating gate transistor and one embodiment of a the present invention having a lower barrier energy.

[0028] FIG. 5 is a graph that illustrates generally the relationship between Fowler-Nordheim tunneling current density vs. the barrier energy Φ_GIat various parameterized values E₁<E₂<E₃of an electric field.

[0029] FIG. 6 illustrates generally how the barrier energy affects the time needed to perform write and erase operations by Fowler-Nordheim tunneling for a particular voltage.

[0030] FIG. 7 is a graph that illustrates generally charge density vs. write/erase time for three different embodiments of a floating gate FET.

[0031] FIG. 8 is a cross-sectional view, similar to FIG. 2, but having a larger area control gate—floating gate capacitor tan the floating gate—substrate capacitor.

[0032] FIG. 9A is a schematic diagram, labeled prior art, that illustrates generally a conventional DRAM memory cell.

[0033] FIG. 9B is a schematic diagram that illustrates generally one embodiment of a floating gate FET memory cell according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0034] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The teems wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form the integrated circuit structure of the invention. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0035] The present invention discloses a memory cell such as, for example, a dynamic electrically alterable programmable read only memory (DEAPROM) cell. The memory cell has a floating electrode, which is defined as an electrode that is “electrically isolated” from conductors and semiconductors by an insulator such that charge storage upon and removal from the floating electrode depends upon charge conduction through the insulator. In one embodiment, described below, the floating electrode is a floating gate electrode in a floating gate field-effect transistor, such as used in flash electrically erasable and programmable read only memories (EEPROMs). However, a capacitor or any other structure having a floating electrode and adjacent insulator could also be used according to the techniques of the present invention described below. According to one aspect of the present invention, a barrier energy between the floating electrode and the insulator is lower than the barrier energy between polycrystalline silicon (polysilicon) and silicon dioxide (SiO₂), which is approximately 3.3 eV. According to another aspect of the present invention, the shorter retention time of data charges on the floating electrode, resulting from the smaller barrier energy, is accommodated by refreshing the data charges on the floating electrode. In this respect, the memory operates similar to a memory cell in a dynamic random access memory (DRAM). These and other aspects of the present invention are described in more detail below.

[0036] FIG. 1 is a simplified schematic/block diagram illustrating generally one embodiment of a memory 100 according to one aspect of the present invention, in which reduced barrier energy floating electrode memory cells are incorporated. Memory 100 is referred to as a dynamic electrically alterable programmable read only memory (DEAPROM) in this application, but it is understood that memory 100 possesses certain characteristics that are similar to DRAMs and flash EEPROMs, as explained below. Memory 100 includes a memory array 105 of multiple memory cells 110. Row decoder 115 and column decoder 120 decode addresses provided on address lines 125 to access the addressed memory cells in memory array 105. Command and control circuitry 130 controls the operation of memory 100 in response to control signals received on control lines 135 from a processor 140 or other memory controller during read, write, refresh, and erase operations. Command and control circuitry 130 includes a refresh circuit for periodically refreshing the data stored on the memory cells 110. Voltage control 150 provides appropriate voltages to the memory cells during read, write, refresh, and erase operations. Memory 100, as illustrated in FIG. 1, has been simplified for the purpose of illustrating the present invention and is not intended to be a complete description. Only the substantial differences between DEAPROM memory 100 and conventional DRAM and flash EEPROM memories are discussed below.

[0037] FIG. 2 is a cross-sectional view that illustrates generally, by way of example, but not by way of limitation, one floating gate transistor embodiment of a memory cell 110. Other structural arrangements of floating gate transistors are included within the present invention. Also included are any memory cells that incorporate a floating electrode (such as a floating electrode capacitor) having, at an interface between the floating electrode an adjacent insulator, a barrier energy that is less than the barrier energy at a polysilicon-SiO₂interface. In the embodiment of FIG. 2, memory cell 110 includes a floating gate FET 200, which is illustrated as an n-channel FET, but understood to include a p-channel FET embodiment as well.

[0038] FET 200 includes a source 205, a drain 210, a floating gate 215 electrode, and a control gate 220 electrode. A gate insulator 225 is interposed between floating gate 215 and substrate 230. An intergate insulator 235 is interposed between floating gate 215 and control gate 220. In one embodiment, substrate 230 is a bulk semiconductor, such as silicon. In another embodiment, substrate 230 includes a thin semiconductor surface layer formed on an underlying insulating portion, such as in a semiconductor-on-insulator (SOI) or other thin film transistor technology. Source 205 and drain 210 are formed by conventional complementary metal-oxide-semiconductor (CMOS) processing techniques. Source 205 and drain 210 are separated by a predetermined length for forming an inversion channel 240 therebetween.

[0039] FIG. 3 is an energy band diagram that illustrates generally the conduction band energy levels in floating gate 215, gate insulator 225, and substrate 230. Electron affinities χ₂₁₅, χ₂₂₅, and χ₂₃₀, describe floating gate 215, gate insulator 225, and substrate 230, respectively, when measured with respect to a vacuum level 300. A barrier energy Φ_GI, which describes the barrier energy at the interface between floating gate 215 and gate insulator 225, is given by a difference in electron affinities, as illustrated in Equation 1.

[0040] Φ_GI=χ₂₁₅−χ₂₂₅ (1)

[0041] A barrier energy Φ_SG, which describes the barrier energy at the interface between substrate 230 and gate insulator 225, is given by a difference in electron affinities, as illustrated in Equation 2.

[0042] Φ_SG=χ₂₃₀−χ₂₂₅ (2)

[0043] Silicon (monocrystalline or polycrystalline Si) has an electron affinity χ₂₁₅≈4.2 eV. Silicon dioxide (SiO₂) has an electron affinity, χ₂₂₅, of about 0.9 eV. The resulting barrier energy at a conventional Si—SiO₂interface between a floating gate and a gate insulator is approximately equal to 3.3 eV. One aspect of the present invention provides a barrier energy Φ_GIthat is less than the 3.3 eV barrier energy of a conventional Si—SiO₂interface.

[0044] According to one aspect of the invention, the interface between floating gate 215 and gate insulator 225 provides a smaller barrier energy Φ_GIthan the 3.3 eV barrier energy at an interface between polysilicon and silicon dioxide, such as by an appropriate selection of the material composition of one or both of floating gate 215 and gate insulator 225. In one embodiment, the smaller barrier energy Φ_GIis obtained by forming floating gate 215 from a material having a smaller electron affinity χ₂₁₅than polysilicon. In one embodiment, for example, polycrystalline or microcrystalline silicon carbide (SiC) is used as the material for forming floating gate 215. In another embodiment, the smaller barrier energy Φ_GIis obtained by forming gate insulator 225 from a material having a higher electron affinity χ₂₂₅than SiO₂. In one embodiment, for example, amorphous SiC is used as the material for forming gate insulator 225. In yet another embodiment, the smaller barrier energy Φ_GIis obtained by a combination of forming floating gate 215 from a material having a smaller electron affinity χ₂₁₅than polysilicon and also forming gate insulator 225 from a material having a higher electron affinity χ₂₂₅than SiO₂.

[0045] The smaller barrier energy Φ_GIprovides current conduction across gate insulator 225 that is easier than for a polysilicon-SiO₂interface. The present invention includes any mechanism of providing such easier current conduction across gate insulator 225, including, but not limited to “hot” electron injection, thermionic emission, Schottky emission, Frenkel-Poole emission, and Fowler-Nordheim tunneling. Such techniques for transporting charge carriers across an insulator, such as gate insulator 225, are all enhanced by providing a smaller barrier energy Φ_GIaccording to the techniques of the present invention. These techniques allow increased current conduction, current conduction at lower voltages across gate insulator 225 and lower electric fields in gate insulator 225, shorter data write and erase times, use of a thicker and more reliable gate insulator 225, and other advantages explained below.

[0046] FIG. 4 is a graph illustrating generally barrier energy versus tunneling distance for a conventional polysilicon-SiO₂interface having a 3.3 eV barrier energy. FIG. 4 also illustrates barrier energy versus tunneling distance for an interface according to the present invention that has a barrier energy of Φ_GI≈1.08 eV, which is selected as an illustrative example, and not by way of limitation. The smaller barrier energy Φ_GIreduces the energy to which the electrons must be excited to be stored on or removed from the floating gate 215, such as by thermal emission over the barrier. The smaller barrier energy Φ_GIalso reduces the distance that electrons have to traverse, such as by Fowler-Nordheim tunneling, to be stored upon or removed from floating gate 215. In FIG. 4, “do” represents the tunneling distance of a conventional floating gate transistor due to the 3.3 eV barrier energy represented by the dashed line “OLD”. The tunneling distance “dn” corresponds to a floating gate transistor according to the present invention and its smaller barrier energy, such as Φ_GI≈1.08 eV, for example, represented by the dashed line “NEW”. Even a small reduction in the tunneling distance results in a large increase in the tunneling probability, as described below, because the tunneling probability is an exponential function of the reciprocal of the tunneling distance.

[0047] The Fowler-Nordheim tunneling current density in gate insulator 225 is illustrated approximately by Equation 3 below.

\begin{matrix} J = {AE}^{2} ⅇ^{(- \frac{B}{E})} & (3) \end{matrix}

[0048] In Equation 3, J is the current density in units of amperes/cm², E is the electric field in gate insulator 225 in units of volts/cm and A and B are constants, which are particular to the material of gate insulator 225, that depend on the effective electron mass in the gate insulator 225 material and on the barrier energy Φ_GI. The constants A and B scale with the barrier energy Φ_GI, as illustrated approximately by Equations 4 and 5.

\begin{matrix} A α (\frac{1}{Φ_{GI}}) & (4) \\ B {α (Φ_{GI})}^{\frac{3}{2}} & (5) \end{matrix}

[0049] For a conventional floating gate FET having a 3.3 eV barrier energy at the interface between the polysilicon floating gate and the SiO₂gate insulator, A=5.5×10⁻¹⁶amperes/Volt²and B=7.07×10⁷Volts/cm. One aspect of the present invention includes selecting a smaller barrier energy Φ_GIsuch as, by way of example, but not by way of limitation, Φ_GI≈1.08 eV. The constants A and B for Φ_GI≈1.08 eV can be extrapolated from the constants A and B for the 3.3 eV polysilicon-SiO₂barrier energy using Equations 4 and 5. The barrier energy Φ_GI≈1.08 eV yields the resulting constants A=1.76×10⁻¹⁵amperes/Volt²and B=1.24×10⁷Volts/cm.

[0050] FIG. 5 is a graph that illustrates generally the relations be Fowler-Nordheim tunneling current density vs. the barrier energy Φ_GI, such as at various parameterized values E₁<E₂<E₃of an electric field in gate insulator 225. The tunneling current density increases as electric field is increased. The tunneling current also increases by orders of magnitude as the barrier energy Φ_GIis decreased, such as by selecting the materials for floating gate 215 and gate insulator 225 or otherwise reducing the barrier energy Φ_GIaccording to the techniques of the present invention. In particular, FIG. 5 illustrates a comparison between tunneling current densities at the 3.3 eV barrier energy of a conventional polysilicon-SiO₂interface and at the illustrative example barrier energy Φ_GI≈1.08 eV for which constants A and B were extrapolated above. Reducing the 3.3 eV barrier energy to Φ_GI≈1.08 eV increases the tunneling current density by several orders of magnitude.

[0051] FIG. 6 is a conceptual diagram, using rough order of magnitude estimates, that illustrates generally how the barrier energy affects the time needed to perform write and erase operations by Fowler-Nordheim tunneling for a particular voltage, such as across gate insulator 225. FIG. 6 also illustrates how the barrier energy affects data charge retention time, such as on floating gate 215 at a temperature of 250 degrees Celsius. Both write and erase time 600 and data charge retention time 605 are decreased by orders of magnitude as the barrier energy is decreased, according to the present invention, from the conventional polysilicon-SiO₂interface barrier energy of 3.3 eV to the illustrative example lower barrier energy Φ_GI≈1.08 eV for which constants A and B were extrapolated above.

[0052] The lower barrier energy Φ_GIand increased tunneling current advantageously provides faster write and erase times. This is particularly advantageous for “flash” EEPROMs or DEAPROMs in which many floating gate transistor memory cells must be erased simultaneously, requiring a longer time to transport the larger quantity of charge. For a flash EEPROM using a polysilicon floating gate transistor having an underlying SiO₂gate insulator 225, the simultaneous ensure of a block of memory cells requires a time that is on the order of milliseconds. The write and erase time of the floating gate FET 200 is illustrated approximately by Equation 6.

\begin{matrix} t = \int_{0}^{t} ⅆ t = \int_{0}^{Q} (\frac{1}{J_{225} - J_{235}}) ⅆ Q & (6) \end{matrix}

[0053] In Equation 6, t is the write/erase time, J₂₂₅and J₂₃₅are the respective tunneling current densities in gate dielectric 225 and intergate dielectric 235, Q is the charge density in Coulombs/cm²on floating gate 215. Equation 6 is evaluated for a specific voltage on control gate 220 using Equations 7 and 8.

\begin{matrix} E_{225} = \frac{V_{220}}{[d_{225} + d_{235} (\frac{ε_{225}}{ε_{235}})] - \frac{Q}{[ε_{225} + ε_{235} (\frac{d_{225}}{d_{235}})]}} & (7) \\ E_{235} = \frac{V_{220}}{[d_{235} + d_{225} (\frac{ε_{235}}{ε_{225}})] + \frac{Q}{[ε_{235} + ε_{225} (\frac{d_{235}}{d_{225}})]}} & (8) \end{matrix}

[0054] In Equations 7 and 8, V₂₂₀is the voltage on control gate 220, E₂₂₅and E₂₃₅are the respective electric fields in gate insulator 225 and intergate insulator 235, d₂₂₅and d₂₃₅are the respective thicknesses of gate insulator 225 and intergate insulator 235, and ∈₂₂₅and ∈₂₃₅are the respective permittivities of gate insulator 225 and intergate insulator 235.

[0055] FIG. 7 is a graph that illustrates generally charge density vs. write/erase time for three different embodiments of the floating gate FET 200, of which have a polysilicon floating gate 215, by way of illustrative example. Line 700 illustrates generally, by way of example, but not by way of limitation, the charge density vs. write/erase time obtained for a floating gate FET 200 having a 100 Å SiO₂gate insulator 225 and a 150 Å SiO₂(or thinner oxynitride equivalent capacitance) intergate insulator 235.

[0056] Line 705 is similar to line 700 in all respects except that line 705 illustrates a floating gate FET 200 in which gate insulator 225 comprises a material having a higher electron affinity χ₂₂₅than SiO₂, thereby providing a lower barrier energy Φ_GIat the interface between polysilicon floating gate 215 and gate insulator 225. The increased tunneling current results in shorter write/erase times than those illustrated by line 700.

[0057] Line 710 is similar to line 705 in all respects except that line 710 illustrates a floating gate FET 200 in which gate insulator 225 has a lower barrier energy Φ_GIthan for line 705, or intergate insulator 235 has a higher permittivity ∈₂₃₅than for line 705, or control gate 220 has a larger area than floating gate 215, such as illustrated by way of example by the floating gate FET 800 in the cross-sectional view of FIG. 8. As seen in FIG. 8, the area of a capacitor formed by the control gate 220, the floating gate 215, and the intergate insulator 235 is larger than the area of a capacitor formed by the floating gate 215, the gate insulator 225, and the inversion channel 240 underlying gate insulator 225. Alternatively, or in combination with the techniques illustrated in FIG. 8, the intergate insulator 235 can have a higher permittivity than the permittivity of silicon dioxide.

[0058] As illustrated in FIG. 7, the barrier energy Φ_GIcan be selected to reduce the write/erase time. In one embodiment, by way of example, but not by limitation, the barrier energy Φ_GIis selected to obtain a write/erase time of less than or equal to 1 second, as illustrated in FIG. 7. In another embodiment, by way of example, but not by way of limitation, the barrier energy Φ_GIis selected to obtain a write/erase time of less than or equal to 1 millisecond, as illustrated in FIG. 7. Other values of write/erase time can also be obtained by select the appropriate value of the barrier energy Φ_GI.

[0059] The lower barrier energy Φ_GIand increased tunneling current also advantageously reduces the voltage required for writing and erasing the memory cells 110. For example, conventional polysilicon floating gate transistors typically require complicated and noisy on-chip charge pump circuits to generate the large erasure voltage, which typically far exceeds other voltages required on the integrated circuit. The present invention allows the use of lower erasure voltages that are more easily provided by simpler on-chip circuits. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. In one embodiment, the barrier energy Φ_GIis selected, as described above, to obtain an erase voltage of less than the 12 Volts required by typical EEPROM memory cells.

[0060] Alternatively, the thickness of the gate insulator 225 can be increased from the typical thickness of a silicon dioxide gate insulator to improve reliability or simplify processing, since the lower barrier energy Φ_GIallows easier transport of charge across the gate insulator 225 by Fowler-Nordheim tunneling.

[0061] The lower barrier energy Φ_GIalso decreases the data charge retention time of the charge stored on the floating gate 215, such as from increased thermal excitation of stored charge over the lower barrier Φ_GIHowever, conventional polysilicon floating gates and adjacent SiO₂insulators (e.g., 90 Å thick) have a data charge retention time estimated in the millions of years at a temperature of 85 degrees C., and estimated in the 1000 hour range even at extremely high temperatures such as 250 degrees C. Since such long data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of the smaller barrier energy Φ_GI. In one embodiment, by way of example, but not by way of limitation, the barrier energy Φ_GIis lowered to Φ_GI≈1.08 eV by appropriately selecting the composition of the mars of floating gate 215 and gate insulator 225, as described below. As a result, estimated data charge retention time of approximately 40 seconds at a high temperature, such as 250 degrees C., is obtained.

[0062] According to one aspect of the present invention, the data stored on the memory cell 110 is periodically refreshed at an interval that is shorter than the data charge retention time. In one embodiment, for example, the data is refreshed every few seconds, such as for an embodiment having a high temperature retention time of approximately 40 seconds for Φ_GI≈1.08 eV. The exact refresh rate can be experimentally determined and tailored to a particular process of fabricating the DEAPROM. By decreasing the data charge retention time and periodically refreshing the data, the write and erase operations can be several orders of magnitude faster, as described above with respect to FIG. 7.

[0063] FIGS. 9A and 9B are schematic diagrams that respectively illustrate generally a conventional DRAM memory cell and the present invention's floating gate FET 200 embodiment of memory cell 110. In FIG. 9A, the DRAM memory cell includes an access FET 900 and stacked or trench storage capacitor 905. Data is stored as charge on storage capacitor 905 by providing a control voltage on control line 910 to activate FET 900 for conducting charge. Data line 915 provides a write voltage to conduct charge across FET 900 for storage on storage capacitor 905. Data is read by providing a control voltage on control line 910 to activate FET 900 for conducting charge from storage capacitor 905, thereby incrementally changing a preinitialized voltage on data line 915. The resulting small change in voltage on data line 915 must be amplified by a sense amplifier for detection. Thus, the DRAM memory cell of FIG. 9A inherently provides only a small data signal. The small data signal is difficult to detect.

[0064] In FIG. 9B, the memory cell 110 according to the present invention is a DEAPROM memory cell that includes floating gate FET 200, having source 205 coupled to a ground voltage or other reference potential. Data is stored as charge on floating gate 215 by providing a control voltage on control line 920 and a write voltage on data line 925 for hot electron injection or Fowler-Nordheim tunneling. This is similar to conventional EEPROM techniques, but advantageously uses the reduced voltages and/or a shorter write time of the present invention.

[0065] The DEAPROM memory cell can be smaller than the DRAM memory cell of FIG. 9A, allowing higher density data storage. The leakage of charge from floating gate 215 can be made less than the reverse-bias junction leakage from storage capacitor 905 of the DRAM memory cell by tailoring the barrier energy Φ_GIaccording to the techniques of the present invention. Also, the DEAPROM memory cell advantageously uses the large transconductance gain of the floating gate FET 200. The conventional DRAM memory cell of FIG. 9A provides no such gain; it is read by directly transferring the data charge from storage capacitor 905. By contrast, the DEAPROM memory cell is read by placing a read voltage on control line 920, and detecting the current conducted through FET 200, such as at data line 925. The current conducted through FET 200 changes significantly in the presence or absence of charge stored on floating gate 215. Thus, the present invention advantageously provides an large data signal that is easy to detect, unlike the small data signal provided by the conventional DRAM memory cell of FIG. 9A.

[0066] For example, the current for floating gate FET 200 operating in the saturation region can be approximated by Equation 9.

\begin{matrix} I_{DS} = \frac{1}{2} μ C_{o} (\frac{W}{L}) {(V_{G} - V_{T})}^{2} & (9) \end{matrix}

[0067] In Equation 9, I_DSis the current between drain 210 and source 205, C_ois the capacitance per unit area of the gate insulator 225, W/L is the width/length aspect ratio of FET 200, V_Gis the gate voltage applied to control gate 220, and V_Tis the turn-on threshold voltage of FET 200.

[0068] For an illustrative example, but not by way of limitation, a minimum-sized FET having W/L=1, can yield a transconductance gain of approximately 71 μA/Volt for a typical process. In this illustrative example, sufficient charge is stored on floating gate 215 to change the effective threshold voltage V_Tby approximately 1.4 Volts, thereby changing the current I_DSby approximately 100 microamperes. This significant change in current can easily be detected, such as by sampling or integrating over a time period of approximately 10 nanoseconds, for example, to obtain a detected data charge signal of 1000 fC. Thus, the DEAPROM memory cell is capable of yielding a detected data charge signal that is approximately an order of magnitude larger than the typical 30 fC to 100 fC data charges typically stored on DRAM stacked or trench capacitors. Since DEAPROM memory cell requires a smaller capacitance value than a conventional DRAM memory cell, DEAPROM memory cell can be made smaller than a conventional DRAM memory cell. Moreover, because the CMOS-compatible DEAPROM storage capacitor is integrally formed as part of the transistor, rather than requiring complex and costly non-CMOS stacked and trench capacitor process steps, the DEAPROM memory of the present invention should be cheaper to fabricate than DRAM memory cells, and should more easily scale downward as CMOS technology advances.

GaN and GaAlN Gate Material Embodiments

[0069] In one embodiment, the present invention provides a DEAPROM having a memory cell 110 including a FET 200 having an at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, nanocrystalline, or combination thereof) gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate 215.

[0070] In one embodiment, a composition ν of a polycrystalline Ga_1−vAl_vN floating gate 215 is selected approximately between 0<ν<1 to obtain a desired barrier energy, as described below. The GaAlN floating gate 215 provides a lower electron affinity than polysilicon. The GaAlN floating gate 215 electron affinity can be approximately between 0.6 eV<χ₂₁₅<2.7 eV as the GaAlN composition variable ν is decreased from 1 to 0. As a result, the GaAlN floating gate 215 provides a smaller resulting barrier energy Φ_GIthan a polysilicon gate material having an electron affinity χ₂₁₅≈4.2 eV. For example, using a SiO₂gate insulator 225, a barrier energy approximately between −0.3 eV<Φ_GI<1.8 eV is obtained using an GaAlN floating gate 215 as the GaAlN composition ν varies between ν≈1 (i.e., approximately AlN) and ν≈0 (i.e., approximately GaN). By contrast, a conventional polysilicon floating gate material provides a barrier energy Φ_GI≈3.3 eV at an interface with an SiO₂gate insulator 225.

[0071] In one embodiment, substrate 230 is bulk silicon, although other bulk semiconductor and semiconductor-on-insulator (SOI) materials could also be used for substrate 230 such as, for example, sapphire, gallium arsenide (GaAs), GaN, AlN, and diamond. In one embodiment, gate insulator 225 is SiO₂, although other dielectric materials could also be used for gate insulator 225, as described above, such as amorphous insulating GaN (a-GaN), and amorphous insulating AlN (a-AlN). The FET 200 using a GaAlN floating gate 215 has mobility and turn-on threshold voltage (V_T) magnitude parameters that are advantageously influenced less by charge at SiO₂-GaAlN interface surface states than at a conventional SiO₂-polysilicon interface.

[0072] In one embodiment floating gate 215 is formed of a polycrystalline, microcrystalline, or nanocrystalline, GaN thin film that is CVD deposited on a thin (e.g., 500 Å thick) AlN buffer layer, such as by metal organic chemical vapor deposition (MOCVD), which advantageously yields improved crystal quality and reduced microscopic fluctuation of crystallite orientation.

[0073] In one embodiment, floating gate 215 is formed from a GaN film grown in a horizontal reactor operating at atmospheric pressure. Trimethyl gallium (TMG), trimethylaluminum (TMA), and ammonia (NH₃) are used as source gases, and hydrogen (H₂) is used as a carrier gas. The TMG, TMA, and NH₃are mixed just before the reactor, and the mixture is fed at high velocity (e.g., 110 cm/s) to a slanted substrate 230 through a delivery tube. The desired GaAlN composition ν is obtained by controlling the concentration ratio of TMG to TMA. In one embodiment, a 500 Å AlN buffer layer is obtained by growth at 600 degrees Celsius at a deposition rate of 100 Å/minute for approximately 5 minutes, then a epitaxial crystalline or polycrystalline layer of GaN is deposited at 1000 degrees Celsius.

[0074] In another embodiment plasma-enhanced molecular beam epitaxy (PEMBE) is used to form a GaN or GaAlN floating gate 215, for example, by using electron cyclotron resonance (ECR) plasma during molecular beam epitaxy (MBE). The background pressure in the MBE chamber is typically less than 10⁻¹⁰torr. Ga flux (e.g., 99.99999% pure) is supplied by a conventional Knudsen effusion cell. The semiconductor substrates 230 are heated to a temperature of approximately 850 degrees Celsius, and exposed to a nitrogen plasma (e.g., 35 Watt plasma power level) to clean the surface of the substrate 230 and form a thin AlN layer thereupon. The temperature is then lowered to approximately 550 degrees Celsius for growth of a thin (e.g., 300 Å) GaN buffer layer (e.g., using 20 Watt plasma power level for growth in a low active nitrogen overpressure environment). The temperature is then increased, such as to approximately 800 degrees Celsius, to form the remainder of the GaN or GaAlN film forming floating gate 215, such as at a deposition rate of approximately 0.22 microns/hour.

Conclusion

[0075] The present invention provides a DEAPROM cell. The memory cell has a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating electrode, such as a floating gate electrode in a floating gate field-effect transistor. According to one aspect of the invention, a barrier energy between the floating electrode and the insulator is lower than the barrier energy between polysilicon and SiO₂, approximately 3.3 eV. The memory cell also provides large transconductance gain, which provides a more easily detected signal and reduces the required data storage capacitance value. According to another aspect of the invention, the shorter retention time of data charges on the floating electrode, resulting from the smaller barrier energy, is accommodated by refreshing the data charges on the floating electrode. By decreasing the data charge retention time and periodically refreshing the data, the write and erase operations can be several orders of magnitude faster. In this respect, the memory operates similar to a memory cell in DRAM but avoids the process complexity, additional space needed, and other limitations of forming stacked or trench DRAM capacitors.

[0076] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that the above-described embodiments can be used in combination, and any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

Certificate of Correction present

The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.

What is claimed is:

1. A method of operating a floating gate transistor comprising:

coupling a first voltage to a source region in a substrate of a floating gate transistor;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

reading the floating gate transistor.

2. The method of claim 1 wherein:

causing charge to transfer further comprises writing data to the floating gate transistor or erasing data from the floating gate transistor and causing charge to transfer across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the floating gate transistor when writing data to the floating gate transistor;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the floating gate transistor;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

reading the floating gate transistor comprises coupling a read voltage to a control gate separated from the floating gate by an intergate dielectric and detecting current conducted through the floating gate transistor; and

further comprising coupling a control voltage to the control gate when writing data to the floating gate transistor.

3. A method of operating a floating gate transistor comprising:

coupling a first voltage to a source region in a substrate of a floating gate transistor;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

causing charge to transfer between the channel region and a floating gate comprising gallium nitride (GaN) or gallium aluminum nitride (GaAlN) through a silicon dioxide insulator between the channel region and the floating gate by coupling a control voltage to a control gate separated from the floating gate by an intergate dielectric;

refreshing a charge on the floating gate; and

reading the floating gate transistor.

4. The method of claim 3 wherein:

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the floating gate transistor;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate; and

reading the floating gate transistor comprises coupling a read voltage to the control gate and detecting current conducted through the floating gate transistor.

5. A method of operating a memory cell comprising:

coupling a first voltage to a source region in a substrate of a memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

reading the memory cell.

6. The method of claim 5 wherein:

causing charge to transfer further comprises writing data to the memory cell or erasing data from the memory cell and causing charge to transfer across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the memory cell when writing data to the memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

reading the memory cell comprises coupling a read voltage to a control gate separated from the floating gate by an intergate dielectric and detecting current conducted through the memory cell; and

further comprising coupling a control voltage to the control gate when writing data to the memory cell.

7. A method of operating a memory cell comprising:

coupling a first voltage to a source region in a substrate of a memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

reading the memory cell.

8. The method of claim 7 wherein:

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the memory cell when writing data to the memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate; and

reading the memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the memory cell.

9. A method of operating a memory device comprising:

selecting a first memory cell from a plurality of memory cells in a memory device;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

10. The method of claim 9 wherein:

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in a DEAPROM memory device;

causing charge to transfer further comprises writing data to the first memory cell or erasing data from the first memory cell and causing charge to transfer across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

reading the second memory cell comprises coupling a read voltage to a control gate separated from the floating gate by an intergate dielectric and detecting current conducted through the first memory cell; and

further comprising:

coupling a control voltage to the control gate when writing data to the first memory cell;

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

11. A method of operating a memory device comprising:

selecting a first memory cell from a plurality of memory cells in a memory device;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

12. The method of claim 11 wherein:

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in a DEAPROM memory device;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

reading the second memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the first memory cell; and

further comprising:

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

13. A method of operating a system comprising:

exchanging signals between a processor and a memory device in a system;

selecting a first memory cell from a plurality of memory cells in the memory device based on the signals;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

14. The method of claim 13 wherein:

exchanging signals comprises exchanging address signals, data signals, and control signals over respective lines coupled between a processor and a DEAPROM memory device in a system; selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in the DEAPROM memory device based on the signals;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

further comprising:

coupling a control voltage to the control gate when writing data to the first memory cell;

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to the control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

15. A method of operating a system comprising:

exchanging signals between a processor and a memory device in a system;

selecting a first memory cell from a plurality of memory cells in the memory device based on the signals;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

16. The method of claim 15 wherein:

exchanging signals comprises exchanging address signals, data signals, and control signals over respective lines coupled between a processor and a DEAPROM memory device in a system;

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in the DEAPROM memory device based on the signals;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

reading the second memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the first memory cell; and

further comprising:

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to the control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

17. A method of operating a floating gate transistor comprising:

coupling a first voltage to a source region in a substrate of a floating gate transistor;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

causing charge to transfer between the channel region and a floating gate comprising gallium aluminum nitride (GaAlN) through an insulator between the channel region and the floating gate;

refreshing a charge on the floating gate; and

reading the floating gate transistor.

18. The method of claim 17 wherein:

causing charge to transfer further comprises writing data to the floating gate transistor or erasing data from the floating gate transistor and causing charge to transfer through a silicon dioxide insulator between the channel region and the floating gate across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the floating gate transistor;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

further comprising coupling a control voltage to the control gate when writing data to the floating gate transistor.

19. A method of operating a floating gate transistor comprising:

coupling a first voltage to a source region in a substrate of a floating gate transistor;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

causing charge to transfer between the channel region and a floating gate comprising gallium aluminum nitride (GaAlN) through an insulator between the channel region and the floating gate by coupling a control voltage to a control gate separated from the floating gate by an intergate dielectric;

refreshing a charge on the floating gate; and

reading the floating gate transistor.

20. The method of claim 19 wherein:

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the floating gate transistor;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate; and

reading the floating gate transistor comprises coupling a read voltage to the control gate and detecting current conducted through the floating gate transistor.

21. A method of operating a memory cell comprising:

coupling a first voltage to a source region in a substrate of a memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

causing charge to transfer between the channel region and a floating gate comprising gallium aluminum nitride (GaAlN) through an insulator between the channel region and the floating gate;

refreshing a charge on the floating gate; and

reading the memory cell.

22. The method of claim 21 wherein:

causing charge to transfer further comprises writing data to the memory cell or erasing data from the memory cell and causing charge to transfer through a silicon dioxide insulator between the channel region and the floating gate across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the memory cell when writing data to the memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

reading the memory cell comprises coupling a read voltage to a control gate separated from the floating gate by an intergate dielectric and detecting current conducted through the memory cell; and

further comprising coupling a control voltage to the control gate when writing data to the memory cell.

23. A method of operating a memory cell comprising:

coupling a first voltage to a source region in a substrate of a memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

reading the memory cell.

24. The method of claim 23 wherein:

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the memory cell when writing data to the memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate; and

reading the memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the memory cell.

25. A method of operating a memory device comprising:

selecting a first memory cell from a plurality of memory cells in a memory device;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

26. The method of claim 25 wherein:

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in a DEAPROM memory device;

causing charge to transfer further comprises writing data to the first memory cell or erasing data from the first memory cell and causing charge to transfer through a silicon dioxide insulator between the channel region and the floating gate across a barrier energy between the floating gate and the silicon dioxide insulator that is less than approximately 3.3 eV by hot electron injection or Fowler-Nordheim tunneling to change a charge on the floating gate;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

further comprising:

coupling a control voltage to the control gate when writing data to the first memory cell;

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

27. A method of operating a memory device comprising:

selecting a first memory cell from a plurality of memory cells in a memory device;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

28. The method of claim 27 wherein:

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in a DEAPROM memory device;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

reading the second memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the first memory cell; and

further comprising:

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

29. A method of operating a system comprising:

exchanging signals between a processor and a memory device in a system;

selecting a first memory cell from a plurality of memory cells in the memory device based on the signals;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

30. The method of claim 29 wherein:

exchanging signals comprises exchanging address signals, data signals, and control signals over respective lines coupled between a processor and a DEAPROM memory device in a system;

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in the DEAPROM memory device based on the signals;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

further comprising:

coupling a control voltage to the control gate when writing data to the first memory cell;

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to the control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

31. A method of operating a system comprising:

exchanging signals between a processor and a memory device in a system;

selecting a first memory cell from a plurality of memory cells in the memory device based on the signals;

coupling a first voltage to a source region in a substrate of the first memory cell;

coupling a second voltage to a drain region in the substrate separated from the source region by a channel region in the substrate;

refreshing a charge on the floating gate; and

selecting a second memory cell in the memory device and reading the second memory cell.

32. The method of claim 31 wherein:

exchanging signals comprises exchanging address signals, data signals, and control signals over respective lines coupled between a processor and a DEAPROM memory device in a system;

selecting a first memory cell comprises selecting a first memory cell from an array of memory cells in the DEAPROM memory device based on the signals;

coupling a first voltage further comprises coupling a ground voltage to an n+-type source region in a silicon substrate of the first memory cell when writing data to the first memory cell;

coupling a second voltage further comprises coupling a write voltage to an n+-type drain region in the silicon substrate when writing data to the first memory cell;

refreshing a charge on the floating gate comprises refreshing a charge on the floating gate at an interval that is shorter than a charge retention time of the floating gate;

selecting a second memory cell comprises selecting the first memory cell;

reading the second memory cell comprises coupling a read voltage to the control gate and detecting current conducted through the first memory cell; and

further comprising:

decoding an address of the first memory cell in a row decoder and a column decoder;

controlling read, write, erase, and refresh operations in the DEAPROM memory device in response to the control signals with a control circuit; and

providing appropriate voltages to the array from a voltage control circuit.

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