Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems

[0002] 1. Field of the Invention

[0003] The present invention relates generally to pipelined analog-to-digital converters.

[0004] 2. Description of the Related Art

[0005] An impressive variety of modern electronic systems (e.g., scanners, camcorders, communication modems, medical image processors and high-definition television) require the signal conditioning provided by analog-to-digital converters (ADCs) which convert input data signals to digital codes with a resolution that corresponds to the number of bits in the digital code.

[0006] An especially useful ADC structure is exemplified in FIG. 1 which illustrates a pipelined ADC system 20 that includes a sampler 22 and N pipelined converter stages 24. The sampler provides samples of an input data signal S_inand each pipelined converter stage converts a respective analog input data signal to that converter stage's predetermined number of digital bits and passes an amplified residue signal to a succeeding converter stage (the amplified residue signal is the respective analog input signal of the succeeding converter stage).

[0007] As the succeeding converter stage converts its received residue signal in a similar manner, the preceding converter stage is converting a succeeding analog input signal. All converter stages, therefore, are simultaneously converting input data signals to their respective digital bits with final converted words issuing at the same rate as the sampling rate of input data signals. By partitioning the conversion among a number of low resolution converter stages, the pipelined structure provides high resolution a high sampling speeds.

[0008] Broken lines 26 in FIG. 1 indicate that the ith converter stage, for example, comprises an m_i-bit ADC 30 which provides digital bits D_iand also comprises an m_i-bit digital-to-analog converter (DAC) 32 that converts m_ibits to an analog signal which is then subtracted in a summer 34 from this converter stage's respective analog input to form an analog residue R_ithat is amplified in a respective amplifier 36 with a respective gain G_iand passed to a successive converter stage.

[0009] The N converter stages thus generate digital bits D₁, D₂-D_Nthat correspond to each input data signal. Generally, one or more redundant bits are also generated and a control and correction logic 37 includes circuits (e.g., full adders) that use the bits of succeeding stages to digitally correct preceding-stage errors which result from various degrading effects. The control and correction logic also includes circuits (e.g., shift registers) that time-align the corresponding digital bits of the different converter stages to produce the final digital code C_dgtl.

[0010] A particularly useful structure for realizing the converter stage structure within the broken line 38 is a switched-capacitor multiplying digital-to-analog converter (MDAC) 40 which is indicated by the broken-line arrow 39. The MDAC 40 is shown in a 1.5 bit version which comprises a differential amplifier 42, equal-sized capacitors C₁and C₂and a plurality of switches. For clarity of illustration, the switches are not shown but in operation, the switches are placed in first and second states which configure the MDAC 40 (in states 40A and 40B) for first and second operational phases.

[0011] In the first operational phase that corresponds to state 40A, both capacitors are coupled to their converter stage's input voltage v_in. Because the amplifier 42 has high gain, its inverting and noninverting inputs are at substantially the same potential, i.e., they are both at ground potential. Accordingly, the capacitors take on an electrical charge that corresponds to the input voltage v_in.

[0012] In the second operational phase that corresponds to state 40A, a decision signal DV_ris applied (by the m_i-bit ADC 30) to one plate of the capacitor C₁which transfers its electrical charge to the capacitor C₂as indicated by charge-transfer arrow 44. The voltage V_rrepresents plus and minus limits of the input range of the converter stage. D is set by the decision of the corresponding ADC converter stage concerning its analog input signal and, for a 1.5 bit converter stage, takes on values +1, 0 and −1. Because the capacitors C₁and C₂have the same capacitance, the amplifier's output voltage v_outis doubled by the charge transfer and, when D is +1 and −1, is also offset respectively up and down. The proper gained-up residue signal is thereby provided to the succeeding converter stage.

[0013] An error component will be inserted in the gained up residue signal if the capacitances of the capacitors C₁and C₂differ, i.e., if they are not matched. An error component will also be inserted if the gain A of the amplifier 40 is not infinite. As indicated in FIG. 1, the voltage at the inverting input of the amplifier is −v_out/A. This is an error voltage that appears at one plate of the capacitor C₁and corrupts the transfer of electrical charge to the capacitor C₂which, in turn, introduces error into the gained up residue signal. These converter stage errors introduce a nonlinearity into the output digital code C_dgtlof the pipelined ADC 20 which cannot be removed by the control and correction logic 37.

[0014] Fortunately, current fabrication technologies can sufficiently match the capacitors to achieve conversion accuracies in excess of 12 bits. It is quite difficult, however, to realize a large amplifier gain A at the exceedingly high frequencies (e.g., 1 GHz) required of modern pipelined ADCs. Although various modifications have been proposed to reduce the conversion errors introduced by insufficient differential amplifier gain, they are generally complex and/or add substantial structure and cost to pipelined ADC systems.

[0015] The present invention is directed to methods and structures for interleavably processing data signals and error signals in alternating first and second operational phases of successive converter stages of pipelined analog-to-digital converter systems

[0016] These goals are realized with converter stages that are arranged to interleavably process data signals and error signals in alternating first and second operational phases as they convert input data signals to corresponding digital code.

[0017] The interleaved methods and structures significantly reduce conversion errors caused by less-than-infinite and/or nonlinear gain A of converter stage amplifiers and/or samplers. Because this performance enhancement is realized primarily with existing pipelined structure, modification complexity and cost of conventional pipelined systems is substantially reduced. The advantages of the invention are also realized with minimal increase in power consumption and circuit space.

[0018] The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.

[0019] FIG. 1 is a block diagram of a pipelined ADC system;

[0020] FIGS. 2A and 2B illustrate first and second operational phases for a multiplying digital-to-analog (MDAC) embodiment that modifies the ADC system of FIG. 1;

[0021] FIG. 3 is a flow diagram that illustrates process steps for interleavably processing data signals and error signals in the MDAC of FIGS. 2A and 2B

[0022] FIG. 4 is a schematic of a multiplying digital-to-analog (MDAC) embodiment that realizes the operational phases of FIGS. 2A and 2B;

[0023] FIGS. 5A-5D illustrate successive first and second operational phases for another multiplying digital-to-analog (MDAC) embodiment that modifies the ADC system of FIG. 1;

[0024] FIG. 6A is a schematic of another multiplying digital-to-analog (MDAC) embodiment that realizes the operational phases of FIGS. 5A-5D;

[0025] FIG. 6B is a timing diagram that indicates switch states in the schematic of FIG. 6A; and

[0026] FIGS. 7A and 7B show operational phases for sampler embodiments in the ADC system of FIG. 1.

[0027] The present invention is directed to methods and structures for interleavably processing data and error signals in pipelined ADC systems. This processing significantly reduces ADC nonlinearity and is interleaved to enhance the use of existing pipelined structures and thereby significantly reduce pipeline modifications that would otherwise be required. Interleaving data and error signal processing also reduces the additional power consumption and circuit space that would be required by non-interleaved methods.

[0028] Among other significant features of the invention, its error processing methods can be periodically terminated with stored error bits used during the termination periods, it can include randomly-selected capacitors to reduce spurious output signals and its methods and structures improve sampler performance.

[0029] Although interleaved processes of the invention are recited in the flow chart of FIG. 3, a description of those processes is facilitated by preceding it with an investigation of MDAC operational phases that are shown in FIGS. 2A and 2B. A description then follows of an MDAC embodiment (shown in FIG. 3) for realizing these operational phases. Subsequently, MDAC operational phases of FIGS. 5A-5D will be investigated and an MDAC embodiment (shown in FIGS. 6A and 6B) for realizing these operational phases is described.

[0030] FIGS. 2A and 2B illustrate first and second operational phases in a switched-capacitor MDAC 60 of the present invention. In particular these figures show an MDAC of a present converter stage and portions of MDAC's of preceding and succeeding converter stages (shown in broken lines). The MDAC 60 includes a differential amplifier 62, equal-sized capacitors C₁, C₂and C₃and two capacitors C₄/2 that each have a capacitance one half that of the capacitors C₁, C₂and C₃.

[0031] Although the MDAC 60 also includes a plurality of switches, FIGS. 2A and 2B illustrate the configuration of the amplifier 62 and the capacitors C₁, C₂, C₃, C₄/2 and C₄/2 after the switches have been respectively placed in first and second states and, accordingly, the switches themselves are not shown (an MDAC embodiment with switches is shown in FIG. 4 and will be described below). It is noted that the present amplifier 62 of the present converter stage generates an output signal at an output port 66 in response to an input signal at an input port 65 as does also the preceding amplifier 48 that is shown in the preceding converter stage.

[0032] In FIG. 2A, the switches (not shown) have been placed in a first state that causes capacitors C₁and C₂to capacitively extract a preceding data sample from the amplifier output signal of the preceding amplifier (i.e., the capacitors are coupled to the amplifier output signal to take on a corresponding electrical charge). In FIG. 2B, the switches (not shown) have been placed in a second state that causes the two capacitors C₄/2 to capacitively extract a present error sample from the amplifier input signal of the present amplifier 62. Because the amplifier has an output signal v_outand a gain A, an error signal−vout/A exists at its inverting input. The capacitors are coupled to the error signal−vout/A to take on a corresponding electrical charge.

[0033] In FIG. 2A, the first state of the switches also couple the two C4/2 capacitors to capacitively multiply the present error sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 70. In FIG. 2B, the second state of the switches couples capacitors C₁and C₂to capacitively multiply the present data sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 72.

[0034] The present invention recognizes that the gain of the MDAC 40B of FIG. 1 is $\begin{array}{cc}{v}_{\mathrm{out}}=\frac{G}{1+G/A}\left(v_{\mathrm{in}}-{\mathrm{DV}}_r/2\right)& \left(1\right)\end{array}$

[0035] when the decision signal DV_r(introduced in the background section) is applied to capacitor C₁wherein G=((C₁+C₂)/C₂). The gain G is two if capacitors C₁and C₂are well matched and, in that event,

[0036] v_out=2v_in−DV_r.  (2)

[0037] If the capacitors are matched so there is no error in G and if the amplifier gain A, then the term G(v_in−DV_r/2) represents an ideal v_out. Substitution of ideal v_outinto equation (1) yields

[0038] v_out=ideal v_out−G v_out/A  (3)

[0039] which identifies an ideal term and an error term G v_out/A that is generated by the limited amplifier gain A. The error term represents error that is introduced into the processing of data signals because of the limited amplifier gain G. It also represents nonlinearity that is introduced because the amplifier gain G generally changes in response to changes in amplitude of the amplifier's input signal.

[0040] The input signal at the amplifier's input port 65 in FIG. 2B thus represents an error signal−vout/A which is the present error sample, that is capacitively extracted by the capacitors C₄/2 in the second operational phase of FIG. 2B. Because these capacitors have the same value, they capacitively multiply the present error sample by a factor of two which equals the gain G in the error term of equation (3).

[0041] The present converter stage of FIGS. 2A and 2B therefore interleavably processes data signals and error signals in alternating first and second operational phases as it converts input data signals to corresponding digital code. As the capacitors C₁and C₂are capacitively extracting a preceding data signal from the output signal of a preceding converter stage in the first operational phase of FIG. 2A, the amplifier 62 is employed with capacitors C₄/2 to capacitively multiply a present error sample to the output port 66 of the present amplifier.

[0042] Then, as the capacitors C₄/2 are capacitively sampling a present error sample in the second operational phase of FIG. 2B, the amplifier 62 is employed with capacitors C₁and C₂to capacitively multiply the preceding data sample to the output port 66 of the present amplifier. Error samples are thus processed through the amplifier 62 in the first operational phase and data samples are processed through the amplifier 62 in the second operational phase.

[0043] This method of interleaved processing is summarized in the process steps that are shown in the flow chart 80 of FIG. 3. In a first process step 82, at least a present and a preceding converter stage are provided that respectively have a present and a preceding amplifier which each generates an amplifier output signal in response to an amplifier input signal.

[0044] In a first operational phase of process step 83, a preceding data sample is capacitively extracted from the amplifier output signal of the preceding amplifier and a present error sample is capacitively multiplied through the present amplifier. In a second operational phase of process step 84, a preceding data sample is capacitively multiplied through the present amplifier and the present error sample is capacitively extracted from the amplifier input signal of the present amplifier.

[0045] Thus, the preceding data sample and the present error sample are interleavably processed through the present converter stage in the first and second operational phases. Because the amplifier gain A of the preceding converter stage of FIG. 2A is also not infinite, this converter stage also generates an error signal G v_out/A at its output port. Preferably, the error history of preceding converter stages is accumulated with the present error signal of the present converter stage for further processing by downstream converter stages.

[0046] Accordingly, FIG. 2B also shows that the second state of the switches of the present converter stage couples the capacitor C₃to capacitively extract a preceding error sample G v_out/A from the amplifier output signal of the preceding amplifier 62 (note that this preceding amplifier is now in the first state of the present converter stage shown in FIG. 2A). In FIG. 2A, the switches are then placed in a first state that couples capacitor C₃to capacitively multiply the preceding error sample through the present amplifier 62. This occurs by charge transfer (that is indicated by a charge-transfer arrow 74) to the capacitor C₄/2 that is coupled about the present amplifier 62.

[0047] The preceding amplifier 62 is shown in broken lines in FIGS. 2A and 2B. Because the switches (not shown) of the present converter stage are in their first state in FIG. 2A, the switches of the succeeding converter stage are in their second state in this figure. Accordingly, capacitor C₃of the succeeding converter stage is shown in broken lines coupled to capacitively extract an error sample from the output signal of the present amplifier. Because the switches (not shown) of the present converter stage are in their second state in FIG. 2B, the switches of the succeeding converter stage are in their first state in this figure. Accordingly, capacitors C₁and C₂of the succeeding converter stage are shown in broken lines coupled to capacitively extract a data sample from the output signal of the present amplifier.

[0048] The coupling of capacitor C₃is also recited in the flow chart 80 of FIG. 3. In a first operational phase of process step 85, a preceding error sample is capacitively multiplied through the present amplifier. In a second operational phase of process step 85, the preceding error sample is capacitively extracted from the amplifier output signal of the preceding amplifier.

[0049] FIG. 4 illustrates an MDAC embodiment 100 that can realize the first and second operational phases of FIGS. 2A and 2B. The MDAC 100 includes the amplifier 62 and the capacitors C₁, C₂, C₃, C₄/2 and C₄/2 of FIGS. 2A and 2B. In addition, the MDAC 100 shows switches which were not shown in FIGS. 2A and 2B. Portions of the preceding and succeeding converter stages are shown in broken lines.

[0050] All of the switches are shown in an open state. A first group of eight switches (including an exemplary switch 102), however, are labeled φ1 to indicate that they are closed during the first operational phase of FIG. 2A and a second group of nine switches (including an exemplary switch 103) are labeled 02 to indicate that they are closed during the second operational phase of FIG. 2B. It is apparent that the present converter stage 60 of FIG. 2A is realized when the switches labeled φ1 are closed and the present converter stage 60 of FIG. 2B is realized when the switches labeled φ2 are closed.

[0051] It is recalled that the present error signal−vout/A exists at the amplifier input port 65 in FIG. 2B. Coupling an additional load (e.g., parasitic capacitance) to the input port may corrupt the accuracy of the error signal. Therefore, a buffer amplifier 106 is preferably inserted between the input port 65 and the capacitors C₄/2 to reduce disturbance of the error signal (the buffer amplifier 106 is also shown in FIG. 2B).

[0052] Because the error signal is typically a very small signal, one method embodiment of interleavably processing data signals and error signals is to accumulate the error in a number of the upstream ones of the converter stages 24 of FIG. 1. Subsequently, the error signal can continue to be accumulated but is then digitized in a number of downstream ones of the converter stages.

[0053] When the error is being digitized in downstream converter stages, the capacitive multiplication should be accomplished with a decision signal from each converter stage's ADC (30 in FIG. 1) just as is done when digitizing the data signals. The decision signal DV_rfor digitizing data signals is formed with the decision D that each converter stage's ADC makes just prior to the second operational phase of FIG. 2B.

[0054] Similarly, a decision signal D_eV_r(subscript e indicating error signal) is formed with the decision D_ethat each converter stage's ADC makes just prior to the first operational phase of FIG. 2A. In the downstream converter stages that are digitizing the accumulated error signal, the decision signal DeV_ris therefore placed on an appropriate one of the capacitors C₄/2 in FIG. 2A during the first operational phase. This is indicated in FIG. 2B by a substitution arrow 110 which indicates substitution of the decision signal D_eV_rfor the ground signal currently shown at the end of the capacitor C₄/2.

[0055] If it is desired to stop further error accumulation in the downstream converter stages that are digitizing the accumulated error, this is accomplished by ceasing (in those converter stages) to couple the capacitor C₃to the output signal of the preceding converter stage (as in FIG. 2B) and to the input 65 of the present amplifier (as in FIG. 2A).

[0056] Digitization of the error signals is thus realized in the second operational phase of FIG. 2B and interleaved with digitization of the data signals which is realized in the first operational phase of FIG. 2A. For each converter stage that is digitizing error signals, the resulting error bits are added to the signal bits for that stage.

[0057] FIGS. 5A-5D illustrate operational phases in another switched-capacitor MDAC embodiment 120 of the present invention. The MDAC 120 includes elements of the MDAC 60 of FIGS. 2A and 2B with like elements indicated by like reference numbers. Capacitor Cl, however, now comprises two equal-size capacitors C₁/2 and capacitors C₄/2 are renamed as capacitors C₅/2 to differentiate their function in the MDAC 120 from that of the capacitors C₄/2 in the MDAC 60.

[0058] In FIG. 5A, switches (not shown) have been placed in a first state that causes capacitors C₁and C₂to capacitively extract a preceding data sample from the amplifier output signal of the preceding amplifier. In FIG. 5B, the switches have been placed in the second state which couples capacitors C₁and C₂to capacitively multiply the present data sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 130. In the same operational phase, the switches couple the capacitor C₃to capacitively extract a preceding error sample from the amplifier output signal of the preceding amplifier 62.

[0059] Because the data signal is being digitized, the decision signal DV_r(from the present converter stage's ADC) is applied to capacitor C₁in FIG. 5B just as was done in FIG. 2B. The invention notes that the error signal−vout/A is at the input port 65 of the amplifier 62 so that capacitor C₁has a voltage DV_r+v_out/A across it in FIG. 5B.

[0060] In accordance with the invention, therefore, the capacitor C₁is formed of two equal-sized capacitors C₁/2 and in FIG. 5C the switches have been placed in a successive first state (the next first operational state after the first operational state of FIG. 5A) that couples the two C₁/2 capacitors to capacitively multiply the present error sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 132.

[0061] In the same operational phase, the switches couple the capacitor C₃to capacitively multiply the preceding error sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 134. The decision signal DV_ris applied to the capacitor C₃to cancel charges corresponding to the voltage DV_rthat was applied to the capacitor in FIG. 5B (it is recalled that the capacitance of the capacitor C₃equals that of the two capacitors C₁/2). Accordingly, only charges related to the present error sample−vout/A are capacitively multiplied through the present amplifier 62 by the charge-transfer arrow 132.

[0062] Because the capacitors C₁/2 are now in use in the successive operational phase of FIG. 5C for capacitively multiplying the preceding error sample through the present amplifier 62, they cannot also capacitively extract a preceding data sample from the amplifier output signal of the preceding amplifier. Accordingly, the invention substitutes a capacitor C₅which performs, in the operational phases of FIGS. 5C, 5D and 5A, the functions of the capacitor C₁in the operational phases of FIGS. 5A, 5B and 5C.

[0063] That is, the switches of the MDAC 120 are configured in FIG. 5C in a third state that couples capacitors C₅and C₂to capacitively extract a preceding data sample from the amplifier output signal of the preceding amplifier in FIG. 5C. In FIG. 5D, the switches are placed in a fourth state which couples capacitors C₅and C₂to capacitively multiply the present data sample through the present amplifier 62 by charge transfer that is indicated by a charge-transfer arrow 136. In the same operational phase, the switches couple the capacitor C₃to capacitively extract a preceding error sample from the amplifier output signal of the preceding amplifier 62.

[0064] Finally, the capacitor C₅is formed of two equal-sized capacitors C₅/2 and in FIG. 5A the switches have been placed in a successive sixth state that causes the two C₅/2 capacitors to capacitively multiply the present error sample through the present amplifier 62 by charge transfer that is indicated by the charge-transfer arrow 132 (also shown in FIG. 5C). The switches also couple the capacitor C₃to once again capacitively multiply the preceding error sample through the present amplifier 62 by charge transfer that is indicated by the charge-transfer arrow 134 (also shown in FIG. 5C).

[0065] Thus, the capacitors C₁and C₅share responsibilities for capacitively extracting a preceding data sample from the amplifier output signal of the preceding amplifier, capacitively multiplying the preceding data sample through the present amplifier and capacitively multiplying the present error sample through the present amplifier. Data and error signals are therefore interleavably processed through the pipelined converter stages in repeating first and second operational phases with capacitors C₁and C₅successively performing the same operational tasks.

[0066] As previously stated, the error signal is typically a very small signal and, accordingly, one method embodiment of interleavably processing data signals and error signals is to accumulate the error in a number of the upstream converter stages and digitize the error with continued error accumulation in a number of downstream converter stages.

[0067] When the error is being accumulated in upstream converter stages, the decision signal DV_ris placed on capacitor C₃in the first and third operational phases of FIGS. 5A and 5C to cancel charges (related to the decision signal DV_r) that were acquired in the second and fourth operational phases of FIGS. 5D and 5B. When the error is being digitized in downstream converter stages, the ground signals on capacitor C₅/2 in the first operational phase of FIG. 5A and on capacitor C₁/2 in the third operational phase of FIG. 5C are replaced with the decision signal D_eV_ras was previously done for capacitor C₄/2 in the first operational phase of FIG. 2A. Accordingly, a substitution arrow 139 in FIG. 5A indicates substitution of the decision signal D_eV_rfor the ground signal currently shown at the end of this capacitor C₄/2.

[0068] If it is desired to stop further error accumulation in the downstream stages that are digitizing the accumulated error, this is accomplished by ceasing (in those stages) to couple the capacitor C₃to the output signal of the preceding converter stage in FIGS. 5B and 5D and to the input 65 of the present amplifier in FIGS. 5A and 5C.

[0069] As stated above, FIGS. 5A-5D illustrate that capacitors C₁and C₅share responsibilities for capacitively extracting a preceding data sample from the amplifier output signal of the preceding amplifier, capacitively multiplying the preceding data sample through the present amplifier and capacitively multiplying the present error sample through the present amplifier.

[0070] When capacitors C₁and C₅are not perfectly matched, it is noted that this shared responsibility (i.e., repetitive alteration) may generate spurious lines in the output spectrum of the converted digital code. Accordingly, other converter embodiments of the invention add at least one additional capacitor C_xso that capacitors can be repeatably selected (e.g., on a random basis) from the group C₁, C₅and C_xto thereby reduce the generated spurious lines. For example, C₁and C₅may be used in some cycles of the processes of FIGS. 5A-5D, C₁and C_xused in other cycles of the processes of FIGS. 5A-5D, and C₅and C_xused in yet other cycles of the processes of FIGS. 5A-5D.

[0071] FIG. 6A illustrates an MDAC embodiment 140 that can realize the successive first and second operational phases of FIGS. 5A-5D. The MDAC 140 includes elements of the MDAC 100 of FIG. 4 with like elements indicated by like reference numbers. The MDAC 140, however, substitutes first and second capacitors C₁/2 for capacitor C₁of the MDAC 100 and substitutes first and second capacitors C₅/2 for first and second capacitors C₄/2 of the MDAC 100. In addition, the MDAC 140 shows switches which were not shown in FIGS. 5A-5D. Portions of the preceding and succeeding converter stages are shown in broken lines.

[0072] All of the switches are shown in an open state in FIG. 6A wherein the open state corresponds to low states 151 in a corresponding timing diagram 150 of FIG. 6B. A first group of three switches (including an exemplary switch 142), however, are labeled φ1 in FIG. 6A to indicate that they are closed during the first operational phases of FIGS. 5A and 5C as indicated by high states 152 in the φ1 waveform of FIG. 6B. A second group of three switches (including an exemplary switch 143) are labeled φ2 to indicate that they are closed during the second operational phases of FIGS. 5B and 5D as indicated by high states 152 in the φ2 waveform of FIG. 6B.

[0073] In addition, a third group of eight switches (including an exemplary switch 144) are labeled φ1ain FIG. 6A to indicate that they are closed during the first operational phase of FIG. 5A as indicated by high states 152 in the φ1awaveform of FIG. 6B. A fourth group of four switches (including an exemplary switch 145) are labeled φ2ato indicate that they are closed during the second operational phase of FIG. 5B as indicated by high states 152 in the φ2awaveform of FIG. 6B.

[0074] Finally, a fifth group of eight switches (including an exemplary switch 146) are labeled φ1bin FIG. 6A to indicate that they are closed during the succeeding first operational phase of FIG. 5C as indicated by high states 152 in the φ1bwaveform of FIG. 6B. A sixth group of four switches (including an exemplary switch 147) are labeled φ2bto indicate that they are closed during the succeeding second operational phase of FIG. 5D as indicated by high states 152 in the φ2bwaveform of FIG. 6B.

[0075] It is apparent that the present converter stage of FIG. 5A is realized when the switches labeled φ1 and φ1aare closed, the present converter stage of FIG. 5B is realized when the switches labeled φ2 and φ2aare closed, the present converter stage of FIG. 5C is realized when the switches labeled φ1 and φ1bare closed and the present converter stage of FIG. 5D is realized when the switches labeled φ2 and φ2bare closed.

[0076] In addition to the switched-capacitor converter stages 24 of the ADC system 20 of FIG. 1, the interleaved teachings of the invention also apply to switched-capacitor samplers such as the sampler 22 of that system wherein FIGS. 7A and 7B illustrate first and second exemplary sampler structures 160 and 162.

[0077] The sampler 160 has a first capacitor C₁coupled to the inverting input of a differential amplifier 162 and a second capacitor C₂coupled between the inverting input and the output port of the amplifier. In a first operational phase 160A of the sampler 160, switches 163 and 164 short the inverting input and the output port to ground. This permits the first capacitor C₁to receive (through its input plate) an electrical charge from the input signal S_inand insures there is no electrical charge in the second capacitor C₂.

[0078] In a second operational phase 160B, the input plate of the first capacitor C₁is grounded and the switches 163 and 164 are opened. This transfers the electrical charge first capacitor C₁from the to the second capacitor C₂. The capacitors are generally equal sized so that this charge transfer realizes a signal gain of one. A held signal S_hldapproximately equal to the input signal S_inis thus presented to the succeeding converter stage.

[0079] The sampler 162 is similar to the sampler 160 except the first capacitor C₁is the switch 164 are removed. In a first operational phase 162A, one plate of the second capacitor C₂is grounded through the switch 163 and a second plate is coupled to receive an electrical charge from the input signal S_in.

[0080] In a second operational phase 162B, the input plate of the second capacitor C₂is coupled to the output port of the differential amplifier 162 and the switch 163 is opened. The sample of the input signal S_inis thus presented as a held signal S_hldto a succeeding converter stage. The gain of this sampler is also one.

[0081] In the present invention, the sampler 160 can be modified to operate with the processes 82, 83 and 84 of the flow chart 80 of FIG. 3. It can, for example, be modified to operate as shown in FIGS. 2A and 2B or as shown in FIGS. 5A-5D. The sampler 162 is also modified to operate with the processes 82, 83 and 84 of the flow chart 80 of FIG. 3. It can, for example, be modified to operate as shown in FIGS. 5A-5D.

[0082] Simulations were run of a 14 bit, 200 megasample per second, pipelined ADC system having 1.5 bit converter stages that have amplifiers (42 in FIG. 1) with a gain A of only 60 dB. The system exhibited a (signal plus noise plus distortion) to (noise plus distortion) ratio (SINAD) of 60 dB and a spurious free dynamic range (SFDR) of 62 dB. Accordingly, this system can only achieve 10 bit resolution of input signals.

[0083] The system was altered to contain the interleaved structures of the invention. In particular, error signals were interleavably accumulated in the initial eight converter stages and interleavably digitized in the remaining stages with no further error accumulation. Simulations of this structure showed an enhanced SINAD of 80 dB and an enhanced SFDR of 98 dB so that the interleaved system achieves a full 14 bit resolution of input signals. This advantage was realized with minimal increase in power consumption.

[0084] Interleaved MDAC methods and structures have been shown which significantly reduce conversion errors caused by less-than-infinite gain A of MDAC amplifiers. They also reduce nonlinearity caused when amplifier gain G changes with changes in input signal amplitude. This performance enhancement is realized primarily with existing MDAC structure so that modification complexity and cost of pipelined ADC systems is substantially reduced.

[0085] Interleaving error and data signal processing also reduces the additional power consumption and circuit space that would otherwise be required. As previously described, error signal digitization is phase-interleaved with digitization of data signals. For each converter stage that is digitizing error signals, the resulting error bits are added to the signal bits for that stage.

[0086] Other converter embodiments of the invention further reduce converter power consumption by operating the converter stages in the interleaved methods of the invention during selected operating periods and operating them in conventional methods during the intervening operating periods. In the selected operating periods, the error bits produced by the methods of the invention may be stored (e.g., in the control and correction logic 37 of FIG. 1) as calibration bits and then, in the remaining operational periods, used to correct the output digital code. This intermittent generation and storage of calibration bits further reduces power consumption (e.g., the buffer 106 of FIG. 4 can be turned off) and also permits use of the stage amplifiers (e.g., amplifiers 62 in FIGS. 2A-2B and 5A-5D) to be used for other purposes when they are not processing error samples.

[0087] The switches of the invention are generally realized with transistors. In FIG. 4, for example, a bipolar junction transistor 170 or a metal-oxide-semiconductor transistor 171 are substituted for a switch labeled φ1 as indicated by substitution arrow 172.

[0088] Although interleaved converter stage embodiments have been illustrated with 1.5 bit structures, the teachings of the invention generally describe interleaved converter stages that convert to any number of digital bits. The capacitor C₁of FIGS. 2A and 2B, for example, generally becomes multiple capacitors that receive different decision signals for charge transfer.

[0089] Although interleaved converter stage embodiments have been illustrated with single-ended structures, the teachings of the invention also embrace differential embodiments.

[0090] To simplify the above description, capacitors in different converter stage embodiments have been simply referenced by capacitor numbers, e.g., capacitors C₁, C₂, C₃and C₄/2 in FIGS. 2A and 2B. In claims corresponding to these figures, these capacitor embodiments are referenced by names that best describe their functions. Thus, C₁is a signal-input capacitor, C₂is a signal-transfer capacitor, C₃is an error-input capacitor and the capacitors C₄/2 are error-transferring capacitors. Similarly, FIGS. 5A-5D references capacitor embodiments C₁/2, C₂, C₃and C₅/2. In claims corresponding to these figures, the capacitors C₁/2 and C₅/2 are signal-input capacitors, C₂is a signal-transfer capacitor, and C₃is an error-input capacitor. These names are for referencing purposes only and are not intended to limit the functionality of the capacitors. For example, capacitor C₂in FIGS. 5A and 5B also functions as a signal-input capacitor in addition to functioning as a signal-transfer capacitor.

[0091] The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.