Voltage output differential (VOD) correction circuit for differential drivers

[0002] The present invention relates generally to electrical circuits and more particularly to current driven differential drivers.

[0003] In a typical communication system, inter-chip high-speed communication is generally limited by the performance of driver and receiver circuits at the interface of communicating chips. Standards have been established for high-speed signal handling applications including, for example, low voltage differential signaling (LVDS) and positive emitter-coupled logic (PECL). These standards enable the design of high-speed systems with minimum power dissipation and low electromagnetic interference (EMI). However, inter-chip high-speed communication is still limited by the performance of driver and receiver circuits at the interface of these devices. The LVDS TIA/EIA-644 standard specifies an output voltage through 100 Ohms to be within 247 mv to 454 mv. This provides sufficient signal amplitude for transforming data without overdriving the connected receiver.

[0004] One limitation involves a condition known as low voltage output differential (VOD). The VOD of a differential driver is the voltage differential between the two components of the differential output signal. In systems employing LVDS, the VOD is designed to be on the order of about 400 mv. In LVDS, the lower voltage output of the differential pair is typically 1.0 V while the higher output voltage is typically 1.4 V. The difference between the two is about 400 mv while the average of the two is the common mode voltage, V_CM. For the above example, V_CMis about 1.2V. The VOD is created by steering a constant current from one output terminal though a standard 100 ohm load resistor to the other output terminal. Current generators are typically used to establish the output currents, I_SOURCEand I_SINKat the two respective output terminals. When process variations cause output current sources to provide I_SOURCEand I_SINKvalues that are below specified levels, then the resulting VOD will be low. A low VOD reduces the noise immunity within the LVDS system and can impact total system performance. Low output currents often result from process variations in resistors that are used to determine the current values. As process limitations can produce variations of plus or minus 20% in resistor values, the corresponding output currents are also subject to plus or minus 20% variations that result in similar variations of VOD.

[0005] The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

[0006] The present invention relates to system and methods for compensating the Voltage Output Differential (VOD) of current driven driver circuits (e.g., LVDS driver circuits) to maintain a desired VOD during driver operation. The system and methods provide for monitoring internal circuit performance and correcting for variations in output current supplied to maintain a desired VOD between the two differential output signals. The present invention provides for comparing the voltage of a representative signal that is based on the VOD with a reference signal that is set to a desired voltage level based on a desired VOD. By determining whether the representative voltage level is higher, equal to, or lower than the desired reference level, balanced adjustments may be made to at least one of the output current source level and the output current sink level to alter the VOD. Balancing the adjustment to the two current sources maintains the existing desired common mode voltage (V_CM). A balanced increase in the source and sink currents at the output results in an increased, VOD while a balanced decrease in the source and sink currents results in a decrease in VOD.

[0007] In one aspect of the present invention, a representative DC signal of the VOD is compared with a reference signal that is set to a desired level. The representative DC signal varies in voltage level by a known offset. The reference signal is set to a value equal to the desired output voltage level plus the known offset. A common mode voltage (V_CM) regulator is employed to maintain V_CMequal to the average of the two output voltage levels. Since V_CMis known, monitoring either the higher differential output voltage or the lower differential output voltage is equivalent to monitoring the VOD. If VOD is low, the output source current and/or the output sink current is increased such that VOD is restored to the desired level. This is accomplished by increasing (e.g., adding) current to a current source that is reflected to at least one of the source current and sink current until the desired VOD is achieved. Similarly, if VOD is high, one or both of the output source current and output sink current are decreased such that VOD is restored to the desired level. This is accomplished by decreasing the current to a current source that is reflected to one or both the source current and the sink current until the desired VOD is achieved.

[0008] The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

[0009] FIG. 1 illustrates a block diagram of a driver system in accordance with an aspect of the present invention.

[0010] FIG. 2 illustrates a block diagram of an alternate driver system in accordance with another aspect of the present invention.

[0011] FIG. 3 illustrates a functional block diagram of a differential driver system with VOD regulation in accordance with an aspect of the present invention.

[0012] FIG. 4 illustrates an electrical schematic of current generator in accordance with an aspect of the present invention.

[0013] FIG. 5 illustrates a VOD correction circuit for low VOD in accordance with an aspect of the present invention.

[0014] FIG. 6 illustrates a VOD correction circuit for both high VOD and low VOD in accordance with an aspect of the present invention.

[0015] FIG. 7 illustrates a block diagram of a methodology for increasing low VOD in accordance with an aspect of the present invention.

[0016] FIG. 8 illustrates a block diagram of a methodology for decreasing high VOD in accordance with an aspect of the present invention.

[0017] The present invention provides systems and methodologies to correct voltage output differential (VOD) variations that result from process variations in current driven drivers, such as Low Voltage Differential Signal (LVDS) drivers. VOD variations result when the resistance values of resistors that determine reference currents vary as a function of the manufacturing process. The reference currents are reflected through a series of current mirrors to create output source and output sink currents that drive a specified load. The voltage created by the output currents that flow through the load provides the VOD. The VOD is the difference in voltage between the high and low output signals of a differential driver pair. The present invention utilizes a compensation device (e.g., differential comparator circuit) that compares an internal DC signal that is based on the VOD to an established reference voltage level, and generates a current stimulus that modifies current through the driver outputs to maintain a desired VOD. The internal DC signal has a known relationship to the VOD.

[0018] In one aspect of the invention, a compensation or correction circuit is employed that determines the results of a comparison of an internal DC signal based on the VOD and an established reference voltage level, and provides a correction current that will either be added, or subtracted, to a reference current that is reflected through a series of current mirrors to create an adjustment in one or both the source and sink currents of the output of the driver. Balancing the adjustment between the source and the sink currents maintains the established common mode voltage (V_CM). V_CMis the average of the high and low differential outputs.

[0019] FIG. 1 is a block diagram of a driver system 10 that regulates the VOD of the differential outputs in accordance with an aspect of the present invention. The driver system 10 consists of a differential driver 12, a nominal current reference generator 14, and a VOD current compensator 16. The nominal current reference generator 14 generates reference current signals that in part determine the output currents I_SOURCEand I_SINKin addition to regulating the common mode voltage (V_CM) of the differential driver 12. The reference current signals include I_SOURCENOM, I_SINKNOMand I_CNTRLNOM. The differential driver 12 utilizes the reference current signal I_SOURCENOMto generate I_SOURCEand the reference current signal I_SINKNOMto generate I_SINK. The differential driver 12 utilizes the reference current signal I_CNTRLNOMto modify I_SOURCEand I_SINKto sustain a desired V_CMvoltage level

[0020] The differential driver 12 receives a singled ended input signal (A), and converts it to a pair of differential output signals Y and YZ. The differential driver 12 drives output currents I_SOURCEand I_SINKthrough a load resistance (R_LOAD) that is external to the driver system 10. The voltage differential across the output nodes Y and YZ is known as the voltage output differential (VOD). The VOD current compensator 16 determines if the resulting VOD is low. If the resultant VOD is low, the VOD current compensator 16 adds current that results in an increase to at least one of the output currents I_SOURCEand I_SINK. If the resultant VOD is high, the VOD current compensator 16 subtracts current that results in a decrease to at least one of the output currents I_SOURCEand I_SINKIt is to be appreciated that although I_SOURCEis illustrated as flowing through top terminal Y and I_SINKis illustrated as flowing through the bottom terminal YZ, the direction I_SOURCEcan be through terminal YZ and the direction of I_SINKcan be through terminal Y. The direction that the current I_SOURCEand I_SINKare steered determines whether the output signal is a logic high or a logic low. In the example of FIG. 1, the direction of I_SOURCEis illustrated as flowing through terminal Y and the direction of I_SINKis illustrated as flowing through terminal YZ indicating a logic high.

[0021] FIG. 2 is a block diagram of an alternate driver system 50 that regulates the VOD of the differential outputs in accordance with another aspect of the present invention. The driver system 50 consists of a differential driver 52, a nominal current reference generator 54, and a VOD current adder/subtractor 56. The nominal current reference generator 54 generates reference current signals that in part determine the nominal output currents I_SOURCEand I_SINKin addition to regulating the common mode voltage (V_CM) of the differential driver 52. The reference current signals include I_SOURCENOM, I_SINKNOMand I_CNTRLNOM. The differential driver 52 utilizes the reference current signal I_SOURCENOMto generate I_SOURCEand the reference current signal I_SINKNOMto generate I_SINK. The differential driver 52 utilizes the reference current signal I_CNTRLNOMto modify I_SOURCEand I_SINKto sustain a desired V_CMvoltage level,

[0022] The differential driver 52 receives a singled ended input signal (A), and converts it to a pair of differential output signals Y and YZ. The differential driver 52 drives output currents I_SOURCEand I_SINKthrough a load resistance (R_LOAD) that is external to the driver system 50. The VOD current adder/subtractor 56 determines if the resulting VOD is low or high. If the resultant VOD is low, the VOD current adder/subtractor 56 adds current that results in an increase to at least one of the output currents I_SOURCEand I_SINK. If the resultant VOD is high, the VOD current adder/subtractor 56 subtracts current that results in a decrease to at least one of the output currents I_SOURCEand I_SINK. In the example of FIG. 2, the direction of I_SOURCEis illustrated as flowing through terminal YZ and the direction of I_SINKis illustrated as flowing through terminal Y indicating a logic low. It is to be appreciated that the adder portion or the subtractor portion of the VOD current adder/subtractor 56 can be implemented without the other if desired for a particular implementation.

[0023] FIG. 3 illustrates a differential driver system 100 that includes VOD regulation in accordance with an aspect of the present invention. In system 100, input signal A is a single ended input such as a TTL input provided to an input state 102. It is to be appreciated that signal A can be any singled ended or rail-to-rail input signal. The input stage 102 receives input signal A and provides signal A and signal AZ (the inverse of signal A) to an output stage 106. The output stage 106 also receives currents I_SOURCEREFand I_SINKREFfrom a Source/Sink Current Controller 112. The output stage 106, based on the logic levels of the inputs received, drives output currents I_SOURCEand I_SINKfrom terminals Y and YZ to an external load. The output currents I_SOURCEand I_SINKare derived from the currents I_SOURCEREFand I_SINKREFfrom the Source/Sink Current Controller 112. The VOD is measured across terminals Y and YZ as a function of the output currents I_SOURCEand I_SINKdriven through external load R_LOAD.

[0024] The output stage 106 also provides two reference signals, V_CMand V_REFVOD, that are used in part to control the output currents I_SOURCEand I_SINKV_CMis the common mode voltage that represents the average of the voltage level between terminal Y and ground and between terminal YZ and ground. V_CMis provided by the output stage 106 to a V_CMregulator 118 and is used in keeping I_SOURCEand I_SINKbalanced such that the desired V_CMis achieved. The other output signal, V_REFVOD, provides a signal that is a function of VOD. V_REFVODis utilized by a current/adder subtractor 132 in maintaining VOD at an appropriate level.

[0025] The common mode voltage is controlled by the V_CMRegulator 118. The V_CMregulator 118 receives signal V_CMfrom the output stage and compares V_CMwith known reference signal V_BG(Bandgap Voltage). V_BGis set to be equal to the desired value of V_CM. In the case of an LVDS driver, V_BGis typically set equal to about 1.2 volts. Another input to the V_CMregulator 118 is a current, I_CNTRLwhich originates in a VCM control 124. Under nominal operating conditions, I_CNTRLwill be equally divided into two currents, I_SOURCEDELTAand I_SINKDELTAwhich are output from V_CMregulator 118. However, if VCM is less than V_BG, then V_CMis low and must be adjusted to a higher level. The V_CMregulator 118 enables this result by shifting the division of I_CNTRLbetween I_SOURCEDELTAand I_SOURCEDELTAto increase the current I_SOURCEDELTAand decrease the current I_SINKDELTA. Similarly, if V_CMis greater than V_BG, then V_CMis high and must be adjusted to a lower level. The VCM regulator 118 enables this result by shifting the division of I_CNTRLbetween I_SOURCEDELTAand I_SOURCEDELTAto decrease the current I_SOURCEDELTAand increase the current I_SINKDELTA.

[0026] I_SOURCEDELTAand I_SINKDELTAare inputs to the Source/Sink Current Controller 112. The Source/Sink Current Controller 112 combines nominal reference currents, I_SOURCENOMand I_SINKNOM, with incremental delta currents to form reference currents, I_SOURCEREFand I_SINKREFwhich are reflected by the output stage 106 as currents I_SOURCEand I_SINK. Source/Sink Current Controller 112 combines I_SOURCENOMwith I_SOURCEDELTAto form I_SOURCEREF. Remembering that I_SOURCEDELTAis increased when V_CMis low, I_SOURCEREFwill correspondingly increase and result in an increased current being reflected to I_SOURCE. Similarly, Source/Sink Current Controller 112 combines I_SINKNOMwith I_SINKDELTAto form I_SINKREF. Remembering that I_SINKDELTAis decreased when V_CMis low, I_SINKREFwill correspondingly decrease and result in a decreased current being reflected to I_SINK. Increasing I_SOURCEand decreasing I_SINKserves to raise the level of V_CM.

[0027] A nominal current reference generator 128 generates three reference currents I_SOURCENOM, I_SINKNOMand I_CNTRLNOM. The source/sink current control 112 utilizes the reference current signal I_SOURCENOMto generate I_SOURCEand the reference current signal I_SINKNOMto generate I_SINK. The V_CMcontrol 124 utilizes the reference current signal I_CNTRLNOMto generate I_CNTRL. I_CNTRLis output from the V_CMcontrol 124 to the VCM Regulator 118. An increase in I_CNTRLserves to increase the VOD observed across the output terminals Y and YZ. This is accomplished as an increase in I_CNTRLresults in an increase to at least one of I_SOURCEDELTAand I_SINKDELTAwhich in turn increases at least one of I_SOURCEREFand I_SINKREF. An increase in at least one of I_SOURCEREFand I_SINKREFresults in an increase in at least one of I_SOURCEand I_SINKcausing an increase VOD across terminals Y and YZ while still maintaining a constant V_CM.

[0028] I_VOD+ and I_VOD− are determined by the Current Adder/Subtractor 132. The Current Adder/Subtractor compares a signal, V_REFVOD, related to VOD, to a known reference input V_REF. V_REFis set to a predetermined value that corresponds to the expected value of V_REFVODfor the desired level of VOD. If VOD is low, then V_REFVODwill be low and the Current Adder/Subtractor 132 creates an adder current I_VOD+ which is output to the VCM control 124 and results in an increase to I_CNTRL. Similarly, if VOD is high, the V_REFVODwill be high and the Current Adder/Subtractor 132 creates a subtractor current I_VOD− which is output to the VCM control 124 and results in a decrease to I_CNTRL. As described above, the present invention adjusts the output currents I_SOURCEand I_SINKin order to maintain a desired VOD. This is accomplished by comparing a signal based on VOD to a known reference and correspondingly adjusting the output currents to compensate for either a low or high VOD.

[0029] FIG. 4 is an electrical schematic of a current generator 150 that is used to generate reference currents employed in a differential driver in accordance with an aspect of the present invention. The current generator 150 includes a current reference 154 formed from transistor P3, transistor N4 and resistor R1 to generate a reference current I_REF. In FIG. 4, current I_REFis established based in part on the resistance value R1. The resistance value of R1 will vary on the order of plus or minus 20% based on process limitations. As a result, I_REFis subject to similar variations of plus or minus 20%. In current generator 150, P3 is coupled in a current mirror configuration with P4, P5, and P6 such that the current I_REFis mirrored to three reference currents I_SOURCENOM, I_SINKNOMand I_CNTRLNOM, which are output through terminal pins CHP, CHN and CHCNTRL, respectively. Since I_REFis subject to variations of plus or minus 20%, the three nominal current references will also be subject to similar variations of plus or minus 20%.

[0030] I_SOURCENOM, I_SINKNOMand I_CNTRLNOMare utilized in differential driver circuit 200 of FIG. 5 to, in part, establish the nominal parameters at the output of the differential driver, (e.g. I_SOURCE, I_SINK, V_CMand VOD). Without some type of feedback and adjustment, the output currents I_SOURCE, I_SINKand output voltages VOD and V_CMwill be subject to similar variations. Referring again to FIG. 4, the current generator 150 includes a differential comparator 152 comprised of transistor P1, P2, N1, N2 and N3. The differential comparator 152 compares a voltage at the resistor RI with a bandgap reference voltage V_BG, which is substantially equal to the common mode voltage V_CM(e.g., 1.2 Volts for LVDS drivers). Transistor N1 is a bias transistor that sets the current of the differential comparator 152 and is controlled by a signal V_B. Transistors P1 and P2 are active loads for the differential comparator 152, while transistor N2 and N3 form the differential pair of the differential comparator 152. The differential comparator 152 adds current through N4 to I_REFin the event that the voltage across R1 is below V_BG.

[0031] FIG. 5 illustrates an electrical schematic of a differential driver circuit 200 in accordance with an aspect of the present invention. The differential driver circuit 200 provides for increasing VOD in response to a low VOD condition. This particular implementation provides for increasing the level of VOD when expected process variations cause deviations from nominal conditions, such that the nominal VOD level may be below a desired VOD level. Dashed lines in FIG. 5 are employed to help identify functionality that is implemented in a designated portion of the circuit. A data input stage 210 is provided that comprises MOSFET devices MP89 and MN90. Input stage 210 receive input signal A at the gate of the two MOSFET devices MP89 and MN90. MP89 and MN90 are coupled in series together to form an inverter circuit that provides a signal AZ that is the inverse of A. Signal A and AZ are are provided to an output stage 280.

[0032] The output stage 280 comprises MOSFET devices MP38, MP41, MN37, MN42, MP55, MN12, Resistors, R111, R112, R_TOPand Capacitor C_TOP. MP38, MP41, MN37 and MN42 are coupled together in an H configured crosspoint switch that steers the output current to output Y or YZ based upon signals A and AZ. The current which flows between outputs Y and YZ generates the VOD when it flows through an external load of a specified value (e.g., 100 ohms). MOSFET device MP55 is coupled to MP38 and MP41 and provides current I_SOURCEwhich flows through either MP41 to output YZ or through MP38 to output Y depending on the logic levels of signals A and AZ. MP55 and MOSFET device MP8 form a current mirror such that current I_SOURCEis determined by a current I_SOURCEREF(I5) that flows through MP8 and a source current controller 240.

[0033] Similarly, MOSFET device MN12 is coupled to MN37 and MN42 and provides current I_SINKfrom output terminal Y through MN37 or from output terminal YZ through MN42 depending upon the logic levels of signals A and AZ. MN12 and MOSFET device MN9 form a current mirror such that current I_SINKis determined by current I_SINKREF(I3) that flows through MN9 in a sink current controller 242. R111 and R112 are resistors of substantially equal value. R111 is coupled to output Y and R112, while R112 is coupled to R111 and output YZ. One side of R_TOPis coupled to the drain of MP55 and the sources of MP38 and MP41 and the other side of R_TOPis coupled to C_TOP. C_TOPis also coupled to ground. R_TOPand C_TOPserve to filter out AC ripple or noise on an otherwise DC signal. The common node of R_TOPand C_TOPprovides a voltage reference signal V_REFVOD. V_REFVODis a signal which differs in voltage by a known amount (the voltage drop across one MOSFET device) from the higher of the two voltages at outputs Y and YZ. As will be discussed, V_CMis controlled to a known value, therefore, the DC component of V_REFVODcan be determined to be equal to about V_CM+½VOD+the voltage drop across one MOSFET device. V_REFVODis provided by the output stage 220 to a current adder 260. Voltage signal V_CMoriginates at the node which couples R111 and R112 together and represents the midpoint of the voltage measured between output terminals Y and YZ.

[0034] A V_CMregulator 230 functions to alter currents I_SOURCEand I_SINKwhen necessary to keep V_CMat a desired level (e.g., 1.2V). The V_CMregulator 230 comprises MOSFET devices MP13, MP14, MN15, MN16 and MP19. MPl9 is coupled in a current mirror configuration with MOSFET device MP1 of a V_CMcontrol 270. MP19 provides current I_CNTRLthat is mirrored from I6 that flows through MP1. MP13 and MP14 are coupled together in a comparator configuration that divides I_CNTRLinto Delta I_SOURCE(I8) and Delta I_SINK(I7). The division of current is based on a comparison of V_CM(coupled to MP13) and V_BG(coupled to MP14). V_BGis set to a known, stable voltage level substantially equal to the desired voltage level for V_CM. The comparator divides I_CNTRLsuch that Delta I_SOURCE(I8) is increased and Delta I_SINK(I7) is decreased when V_CMis low. Delta I_SOURCE(I8) is decreased and Delta I_SINK(I7) is increased when V_CMis high. Delta I_SINK(I7) flows though MN9 of the sink current controller 242 that is configured as a current mirror with MN12 of the output stage 280. The change in Delta I_SINK(I7), changes I_SINKREF(I3) in MN9 which is reflected as a change in I_SINKthrough MNI12. Similarly, Delta I_SOURCE(I8) flows through MN15. MN15 and MN16 are configured as current mirrors such that a change in Delta I_SOURCE(I8) reflects as a change in current through MN16 which in turn changes the current I_SOURCEREF(I5) through MP8 of the source current controller 240 which is configured as a current mirror with MN55 of the output stage 280. The change in Delta I_SOURCE(I8) adds to I_SOURCEREF(I5) in MP8 that is reflected as a change in I_SOURCEthrough MP55.

[0035] The source current controller 240 serves to generate I_SOURCEby combining Nominal I_SOURCE(I1) and Delta I_SOURCE(I8), while the sink current controller 242 serves to generate I_SINKREFby combining Nominal I_SINK(I3) with Delta I_SINK(I8). The source current controller 240 comprises MOSFET devices MN8, MN11, MN5, MN6 and MP8. The sink current controller 242 comprises MOSFET devices MN 10 and MN9. Nominal I_SINK(I3), Nominal I_SOURCE(I1), and Nominal I_CNTRL(I2) originate in a nominal current reference generator such as described in FIG. 4.

[0036] MN9 and MN10 are coupled together in series. Nominal I_SINK(I3) flows through MN10 and combines with Delta I_SINK(I7) to form I_SINKREFthat flows through MN9. Since MN9 and MN12 (output stage 280) are coupled together in a current mirror configuration, I_SINKREFis reflected as I_SINKthrough MN12. MN8 is coupled in series with MN11 and MN5 is coupled in series with MN6. Additionally, MN8 is coupled together with MN5 in a current mirror configuration and, similarly, MN11 and MN6 are coupled together in a current mirror configuration. Nominal I_SOURCE(I1) flows through MN8 and MN11 such that a mirrored current, I5 also flows through MN5 and MN6. MP8 serves to combine I5 and a current mirrored from Delta I_SOURCE(I8), to form I_SOURCEREF. Since MP8 and MP55 (output stage 280) are coupled together in a current mirror configuration, I_SOURCEREFis reflected as I_SOURCEthrough MP55.

[0037] The current adder circuit 260 monitors a voltage related to VOD and provides a stimulus when VOD is low that results in an increase to both I_SOURCEand I_SINK, which thereby increases VOD. The current adder circuit 260 is a differential comparator and comprises MOSFET devices MPO, MN1, MP2, MP3, MN7 and MN14. Signal V_GATEcontrols the MOSFET device MP14, which acts as a bias transistor. MN1 is coupled to MP2 and MN7 is coupled to MPO. MN1 and MN7 are coupled together in a comparator configuration and MPO and MP2 serve as active loads for the comparator. MP3 is coupled to MN7 and to the current mirror pair MN2 and MN0 (VCM Control 270) such that I_VOD+ adds to the current flowing through the current mirror pair MN2 and MN0. The input to the gate of MN1 is V_REFVODwhich varies in direct relationship to VOD. The input to MN7 is V_REF. V_REFis established to be equal to the desired level of V_REFVODfor the desired level of VOD.

[0038] If VOD is at the desired voltage level, then V_REFVODand V_REFare equal. In this condition, MN7 and MN1 provide equal components of current I4. If VOD is low, I_VOD+ will increase driving V_REFVODsubstantially equal to V_REF. The result is that the component of I4 provided by MN7 will increase and the component of I4 provided by MN1 will decrease. As a result, the gate of MP3 will be pulled lower and I_VOD+ will further increase through MP3. I_VOD+ is provided to the V_CMcontrol 270.

[0039] The V_CMcontrol 270 responds to I_VOD+ with a stimulus that will result in an increase in VOD. The V_CMcontrol 270 comprises MOSFET devices MP1, MNO, MN2, MN3, and MN4. MN3 is coupled in series with MN2 and MP1 is coupled in series with MN0 and MN4. Additionally, MN3 is coupled together with MN4 in a cascode mirror configuration and, similarly, MN0 and MN2 are coupled together in a current mirror configuration. I_CNTRLNOM(I2) flows through MN3 to MN2 where MN2 serves to combine I_CNTRLNOM(I2) and IVOD+into a current that is reflected to MN0 as I6. I6 flows through MN4 and MP1 where it is reflected to I_CNTRLthrough MP19 of the VCM regulator 230. The change in I_CNTRLwill result in a balanced change to both Delta I_SOURCE(I8) and Delta I_SINK(I7). These current changes will be reflected as discussed before and will result in a balanced increase to both I_SOURCEand I_SINKsuch that VOD will be appropriately increased or decreased while maintaining the level of V_CM.

[0040] FIG. 6 illustrates an electrical schematic of the differential driver circuit 300 that includes a current adder/subtractor circuit 290 in accordance with an aspect of the present invention. FIG. 6 illustrates a differential driver circuit similar to the differential driver circuit 200 of FIG. 5, but provides for decreasing VOD in response to a high VOD condition in addition to increasing VOD in response to a low VOD condition. The differential driver circuit 300 includes similar components as that described with respect to the differential driver circuit 200 (FIG. 5) except that three additional MOSFET devices MP4, MN17 and MN18 have been added to the current adder circuit 260 of FIG. 5 to provide the current/adder subtractor circuit 290 of FIG. 6. These three MOSFET devices implement the ability to subtract current from the current I_CNTRLprovided to the VCM regulator 230.

[0041] The current adder/subtractor circuit 290 monitors a voltage related to VOD and provides a stimulus when VOD is low that results in an increase to both I_SOURCEand I_SINK, which thereby increases VOD. Similarly, when VOD is high, the current adder/subtractor circuit 290 provides a stimulus that results in a decrease to both I_SOURCEand I_SINK, which thereby decreases VOD. The current adder/subtractor circuit 290 comprises MOSFET devices MP0, MN1, MP2, MP3, MP4 MN7, MN14, MN17, and MN18. The adder portion of the current adder/subtractor circuit 290 has been described in FIG. 5 and therefore a description of the adder portion will be omitted for the sake of redundancy.

[0042] The subtractor portion of the current adder/subtractor circuit 290 includes the addition of MP4 coupled to MN1 and to MN18, which is coupled to MN17 in a current mirror configuration such that the current flowing through MN17 is reflected to provide I_VOD−. MN 17 is coupled to current mirror pair MN2 and MN0 (VCM control 270) such that the current through MN17 reduces the currents through the current mirror pair MN2 and MN0. The input to the gate of MN1 is V_REFVOD(filtered) which varies in direct relationship to VOD. The input to MN7 is V_REF. V_REFis established to be equal to the desired level of V_REFVODfor the desired level of VOD. If VOD is at the desired voltage level, then V_REFVODand V_REFare equal. In this condition, MN7 and MN1 provide equal components of current I4 and the voltage level of the gates of MP3 and MP4 are such that current I_VOD+ is zero and I_VOD− is zero.

[0043] If VOD is low, then V_REFVODwill be less than V_REF. The result is than the component of I4 provided by MN7 will increase and the component of I4 provided by MN1 will decrease. As a result, the gate of MP3 will be pulled lower and IVOD+will increase through MP3. I_VOD+ is provided to the VCM control 270. Similarly, the gate of MP4 will rise and I_VOD− will remain zero. If VOD is high, then V_REFVODwill be greater than V_REF. The result is than the component of I4 provided by MN1 will increase and the component of I4 provided by MN7 will decrease. As a result, the gate of MP4 will be pulled lower and current will decrease through MP4. The gate of MP3 will rise and I_VOD+ will remain zero. I_VOD− is provided to the VCM control 270 through the current mirror pair MN18, MN17.

[0044] The VCM control 270 responds to I_VOD+ with a stimulus that will result in an increase in VOD and similarly responds to I_VOD− such with a stimulus that will result in a decrease in VOD. The VCM control 270 comprises MOSFET devices MP1, MNO, MN2, MN3, and MN4. MN3 is coupled in series with MN2. MP1 is coupled in series with MN0 and MN4. Additionally, MP3 is coupled together with MN4 in a current mirror configuration and, similarly, MN0 and MN2 are coupled together in a current mirror configuration. I_CNTRLNOM(I2) flows through MN3 to MN2 where MN2 serves to combine I_CNTRLNOM(I2), I_VOD− and I_VOD+ into a current that is reflected to MN0 as I6. I6 flows through MN4 and MP1 where it is reflected to I_CNTRLthrough MP19 of the VCM Regulator 230. The change in I_CNTRLwill result in a balanced change to both Delta I_SOURCE(I8) and Delta I_SINK(I7). These current changes will be reflected as discussed before and will result in a balanced increase to both I_SOURCEand I_SINKsuch that VOD will be appropriately increased or decreased while maintaining the level of V_CM.

[0045] In view of the foregoing structural and functional features described above, methodologies in accordance with various aspects of the present invention will be better appreciated with reference to FIGS. 7-8. While, for purposes of simplicity of explanation, the methodologies of FIGS. 7-8 is shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the present invention. Further, the methodologies of FIGS. 7-8 may be combined and implemented together.

[0046] FIG. 7 illustrates one particular methodology for implementing a VOD correction of a current driver device (e.g., LVDS) in accordance with an aspect of the present invention. The methodology begins at 300, where a signal that is representative of an actual VOD level is monitored. The signal can be monitored at a location of the driver that the voltage is relatively constant during operation. The representative signal will then have a know relationship to the VOD of the driver device. The methodology then proceeds to 310. At 310, the representative signal is compared to a reference signal that is set to be equal to the level that the signal representative of VOD will be if VOD is at the desired level. At 320, the comparison is employed to determine if the VOD is low or below a desired VOD. If at 320, the two signals are equal, then VOD is not low (NO) and the method returns to 300 to continue to monitor the representative signal. If at 320, the representative signal is less than the reference signal, then VOD is low (YES) and the method proceeds to 330.

[0047] At 330 an incremental current is generated which is added at 340 to the nominal current that determines the nominal VOD to provide an increased current. At 350, the increased current is reflected through to a VCM regulator. At 360, the reflected increased current is equally divided and added to reference currents that determine the output source current and output sink current. At 370, the increased reference currents are reflected to the output source and output sink currents. The method then returns to 300 where the signal that is representative of VOD will continue to be monitored.

[0048] FIG. 8 illustrates another methodology for implementing a VOD correction for a current driver device (e.g., LVDS) in accordance with an aspect of the present invention. The methodology begins at 400, where a signal that is representative of an actual VOD level is monitored. The signal can be monitored at a location of the driver that the voltage is relatively constant during operation. The representative signal will then have a know relationship to the VOD of the driver device. The methodology then proceeds to 410. At 410, the representative signal is compared to a reference signal that is set to be equal to the level that the signal representative of VOD will be if VOD is at the desired level. At 420, the comparison is employed to determine if the VOD is high or above a desired VOD. If at 420, the two signals are equal, then VOD is not high (NO) and the method returns to 400 to continue to monitor the representative signal. If at 420, the representative signal is higher than the reference signal, then VOD is high (YES) and the method proceeds to 430.

[0049] At 430 an incremental current is generated which is subtracted at 440 from the nominal current that determines the nominal VOD to provide a decreased current. At 450, the decreased current is reflected through to a V_CMregulator. At 460, the reflected decreased current is equally divided and subtracted from the reference currents that determine the output source current and output sink current. At 470, the decreased reference currents are reflected to the output source and output sink currents. The method then returns to 400 where the signal that is representative of VOD will continue to be monitored.

[0050] What has been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.