Differential Amplifier With Common-Mode Stability Enhancement

This invention relates generally to amplifiers, and more particularly, to differential amplifiers with common-mode feedback.

In analog circuitry, signals are often represented as differential voltages. A differential signal may be characterized as having a differential component and a common-mode component. A differential amplifier is very useful in processing differential signal voltages. If the differential amplifier also provides a differential output signal, it is known as a fully differential amplifier. The fully differential amplifier needs a mechanism to set the common-mode voltage to a desired reference voltage, such as an analog ground voltage, typically designated "V.sub.AG ". This mechanism is commonly a circuit which senses the common-mode component of the fully differential output signal, and provides a feedback signal to the amplifier proportional to the sensed difference between the two signals. This common-mode feedback mechanism thus prevents the common-mode voltage from drifting away from the desired reference voltage.

Known differential amplifiers are able to function with characteristics close to those of ideal voltage amplifiers, by having high input impedance, low output impedance, and stable frequency response. For some circuit applications, however, amplifier operation may become unstable. For example, some common-mode feedback circuits cause a node in the feedback circuit to compete with the output nodes of the amplifier gain stages as the dominant pole of the amplifier, causing instability in known amplifiers. Thus, new amplifiers are needed for this and other instability problems.

Accordingly, there is provided, in one form, a differential amplifier with common-mode stability enhancement comprising input means, differential load means, and means for providing first and second output voltages. The input means provides first and second currents respectively into first and second nodes. Differential components of the first and second currents are respectively proportional to positive and negative differences between first and second input signals. A common-mode component of the first and second currents is proportional to a common-mode feedback signal. The differential load means is coupled to the input means. The differential load means converts the differential and common-mode components of the first and second currents into differential and common-mode voltages at third and fourth nodes, respectively. The differential load means also provides a high impedance to the differential component and a low impedance to the common-mode component. The means for providing the first and second output voltages is coupled to the input means and to the differential load means, and provides the first and second output voltages respectively proportional to voltages at the third and fourth nodes, and provides the common-mode feedback voltage in response to a difference between a reference voltage and a sensed common-mode component of the first and second output voltages.

These and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 illustrates in partial schematic form a differential amplifier with common-mode feedback known in the prior art.

FIG. 2 illustrates in partial schematic form one embodiment of a differential amplifier with common-mode stability enhancement in accordance with the present invention.

FIG. 3 illustrates in partial schematic form another embodiment of a differential amplifier with common-mode stability enhancement in accordance with a preferred embodiment of the present invention.

FIG. 1 illustrates in partial schematic form a differential amplifier 20 with common-mode feedback known in the prior art. Differential amplifier 20 includes generally a differential portion 30 and a common-mode feedback circuit 50. FIG. 1 also illustrates a common-mode capacitor 55 and a differential-mode capacitor 56. Differential portion 30 includes a current source 31, an N-channel transistor 32, a capacitor 33, P-channel transistors 34,35, and 36, current sources 37,38, and 39, an N-channel transistor 40, and a capacitor 41. Current source 31 has a first terminal connected to a power supply voltage terminal labelled "V.sub.DD ", and a second terminal providing a negative output voltage signal labelled "V.sub.OUT- ". V.sub.DD is a more-positive power supply voltage terminal and is typically at five volts. Transistor 32 has a drain connected to the second terminal of current source 31, a gate, and a source connected to a power supply voltage terminal labelled "V.sub.SS ". V.sub.SS is a more-negative power supply voltage terminal and is typically at zero volts. Capacitor 33 has a first terminal connected to the second terminal of current source 31, and a second terminal connected to the gate of transistor 32. Transistor 34 has a source connected to V.sub.DD, a gate for receiving a common-mode feedback signal labelled "V.sub.CMFB ", and a drain. Transistor 35 has a source connected to the drain of transistor 34, a gate for receiving a negative input signal voltage labelled "V.sub.IN- ", and a drain connected to the second terminal of capacitor 33. Transistor 36 has a source connected to the drain of transistor 34, a gate for receiving a positive input signal voltage labelled "V.sub.IN+ ", and a drain. Current source 37 has a first terminal connected to the drain of transistor 35, and a second terminal connected to V.sub.SS. Current source 38 has a first terminal connected to the drain of transistor 36, and a second terminal connected to V.sub.SS. Current source 39 has a first terminal connected to V.sub.DD, and a second terminal for providing a positive output signal labelled "V.sub.OUT+ ". Transistor 40 has a drain connected to the second terminal of current source 39, a gate connected to the drain of transistor 36, and a source connected to V.sub.SS. Capacitor 41 has a first terminal connected to the drain of transistor 36, and a second terminal connected to the second terminal of current source 39.

Common-mode feedback circuit 50 includes resistors 51 and 52, and an amplifier 54. Resistor 51 has a first terminal for receiving signal "V.sub.OUT+ ", and a second terminal for providing a sensed common-mode voltage labelled "V.sub.CM ". Resistor 52 has a first terminal connected to the second terminal of resistor 51, and a second terminal for receiving signal V.sub.OUT-. Amplifier 54 has a positive input terminal for receiving a reference voltage labelled "V.sub.CMREF ", a negative input terminal connected to the second terminal of resistor 51 and receiving signal V.sub.CM thereon, and an output terminal connected to the gate of transistor 34 and providing signal V.sub.CMFB thereon. Common-mode capacitor 55 has a first terminal connected to the second terminal of resistor 51, and a second terminal connected to V.sub.SS. Differential-mode capacitor 56 has a first terminal connected to the drain of transistor 40 for receiving signal V.sub.OUT+ thereon, and a second terminal connected to the drain of transistor 32 for receiving signal V.sub.OUT- thereon.

Here and in the following discussion, all transistors are assumed to be biased into saturation. Differential portion 30 is a standard, Miller-compensated two-stage fully differential amplifier with common-mode feedback. Differential portion 30 has two voltage gain stages with high-impedance outputs. The first stage includes transistors 34,35, and 36 and current sources 37 and 38, providing outputs at the drains of transistors 35 and 36. Transistor 34, biased by voltage V.sub.CMFB, functions as a controlled current source. Transistors 35 and 36 selectively divert the current provided by transistor 34 in response to a differential voltage between V.sub.IN+ and V.sub.IN-. The second stage includes current sources 31 and 39, and transistors 32 and 40, providing outputs at the drains of transistors 32 and 40.

Resistors 51 and 52 are equal-valued resistors which sense the common-mode between signals V.sub.OUT+ and V.sub.OUT- as voltage V.sub.CM. Voltage V.sub.CM is provided to the negative input terminal of differential amplifier 54. Differential amplifier 54 receives V.sub.CMREF at the positive input terminal. Amplifier 54 changes its output V.sub.CMFB in response to a difference between the voltages present at its inputs.

Each stage introduces a pole in the frequency response of differential portion 30. Capacitors 33 and 41 are connected between the high-impedance outputs of the two stages to stabilize the operation of differential portion 30. Both the differential-mode and the common-mode dominant poles are at the outputs of the first stage (at the drains of transistors 35 and 36), and both the differential-mode and the common-mode secondary poles are at the outputs of the second stage. However, in some cases, common-mode capacitor 55 is much larger than differential-mode capacitor 56. As the value of common-mode capacitor 55 becomes large in relation to the value of differential-mode capacitor 56, the secondary common-mode pole (at the drains of transistors 32 and 40) begins to compete with the dominant common-mode pole (at the drains of transistors 35 and 36), causing common-mode instability. Thus when the value of common-mode capacitor 55 is large, it is difficult to stabilize the common-mode operation of differential portion 30 while maintaining wide common-mode bandwidth. For this and other problems, new amplifiers are needed.

FIG. 2 illustrates in partial schematic form one embodiment of a differential amplifier 60 with common-mode stability enhancement in accordance with the present invention. Differential amplifier 60 includes generally a differential amplifier 70 and common-mode feedback portion 50. FIG. 2 also illustrates common-mode capacitor 55 and differential-mode capacitor 56 as previously illustrated. Common-mode feedback portion 50, common-mode capacitor 55, and differential-mode capacitor 56 function as described previously. Differential portion 70 includes generally an input portion 80, an output portion 100, and a load portion 110. Differential portion 70 also includes power down circuitry for reducing power consumption during a power down condition. Such circuitry is known in the art and is thus omitted from FIG. 2.

Input portion 80 includes P-channel transistors 81, 82, and 83. Transistor 81 has a source connected to V.sub.DD, a gate for receiving signal V.sub.CMFB, and a drain. Transistor 82 has a source connected to the drain of transistor 81, a gate for receiving signal V.sub.IN-, and a drain connected to a node 84. Transistor 83 has a source connected to the drain of transistor 81, a gate for receiving signal V.sub.IN+, and a drain connected to a node 85. Two other nodes, 86 and 87, are associated with input portion 80. In input portion 80, node 86 is connected to node 84, and node 87 is connected to node 85.

Output portion 100 includes a current source 101, an N-channel transistor 102, a capacitor 103, a current source 104, an N-channel transistor 105, and a capacitor 106. Current source 101 has a first terminal connected to V.sub.DD, and a second terminal providing signal V.sub.OUT- thereon. Transistor 102 has a drain connected to the second terminal of current source 101, a gate connected to node 86, and a source connected to V.sub.SS. Capacitor 103 has a first terminal connected to the second terminal of current source 101, and a second terminal connected to node 86. Current source 104 has a first terminal connected to V.sub.DD, and a second terminal providing signal V.sub.OUT+ thereon. Transistor 105 has a drain connected to the second terminal of current source 104, a gate connected to node 87, and a source connected to V.sub.SS. Capacitor 106 has a first terminal connected to node 87, and a second terminal connected to the second terminal of current source 104.

Load portion 110 includes N-channel transistors 111-114. Transistor 111 has a drain connected to node 84, a gate connected to node 86, and a source connected to V.sub.SS. Transistor 112 has a drain connected to node 85, a gate connected to node 86, and a source connected to V.sub.SS. Transistor 113 has a drain connected to node 84, a gate connected to node 87, and a source connected to V.sub.SS. Transistor 114 has a drain connected to node 85, a gate connected to node 87, and a source connected to V.sub.SS.

Differential portion 70, like differential portion 30, is also a Miller-compensated two-stage fully differential amplifier. The first stage includes input portion 80 and load portion 110, and the second stage is output portion 100. However, differential portion 70 enhances common-mode stability by moving the common-mode pole that would normally reside at nodes 86 and 87 to frequencies much greater than that of other competing poles in the common-mode feedback loop. Thus, the common-mode loop is easier to stabilize. This enhancement occurs because load portion 110 reduces the common-mode output impedance at the first amplifier stage.

To analyze the effect of including load portion 110 in differential portion 70, it is helpful to separately analyze the common-mode and differential components of currents flowing into load portion 110. In the preferred embodiment, the gates of transistors 111-114 have the same size. Thus the common-mode component of the currents are distributed equally through transistors 111-114, making the voltages at nodes 86 and 87 substantially equal. Since the common-mode voltages at nodes 86 and 87 are equal, the effective common-mode impedance is equivalent to that of a gate-to-drain-connected (diode-connected) transistor.

The differential component of the current distributes in such a way that the currents in transistors 111 and 112 are equal and opposite to the currents in transistors 113 and 114 (which are also equal). The differential currents in transistors 111 and 112 are equal because transistors 111 and 112 form a current mirror. Likewise, the differential currents in transistors 113 and 114 are equal because transistors 113 and 114 form a current mirror. Thus, the differential component of the current conducted from node 84 (by transistors 111 and 113) is equal in magnitude and opposite in direction to that conducted from node 85 (by transistors 112 and 114). All of the differential component of the current flowing into the drain of transistor 111 is provided by the differential component of the current of transistor 113. Similarly, all of the differential component of the current flowing into the drain of transistor 114 is provided by the differential component of the current of transistor 112. This in effect creates a positive feedback, enhancing the differential impedance at nodes 86 and 87. Thus, the differential impedance looking into nodes 84 and 85 is very high.

FIG. 3 illustrates in partial schematic form another embodiment of a differential amplifier with common-mode stability enhancement 60' in accordance with a preferred embodiment of the present invention. Differential amplifier 60' includes common-mode feedback portion 50 and a differential portion 70'. FIG. 3 also illustrates common-mode capacitor 55 and differential-mode capacitor 56 as previously illustrated in FIGS. 1 and 2. Differential amplifier 70' includes an input portion 80', output portion 100 as previously illustrated in FIG. 2, and load portion 110'. Differential portion 70' also includes power down circuitry for reducing power consumption during the power down condition. Such circuitry is known in the art and is thus omitted from FIG. 3.

Input portion 80' includes P-channel transistors 81-83 and 88-91. Elements in common with circuit 80 of FIG. 2 retain their respective reference numbers. Input portion 80' has four additional transistors, 88-91. Transistor 88 has a source connected to V.sub.DD, a gate for receiving signal V.sub.CMFB, and a drain. Transistor 89 has a source connected to the drain of transistor 88, a gate for receiving a bias voltage labelled "CPBIAS", and a drain connected to node 86. Transistor 90 has a source connected to V.sub.DD, a gate for receiving signal V.sub.CMFB, and a drain. Transistor 91 has a source connected to the drain of transistor 90, a gate for receiving bias voltage CPBIAS, and a drain connected to node 87. CPBIAS is a bias voltage sufficient to bias P-channel transistors 89 and 91 into saturation.

Load portion 110' includes N-channel transistors 111-114, and N-channel cascode transistors 115 and 116. Elements in common with load portion 110 of FIG. 2 retain their respective reference numbers. In load portion 110', transistor 115 has a drain connected to node 86, a gate for receiving a bias voltage labelled "CNBIAS", and a source connected to node 84. Transistor 116 has a drain connected to node 87, a gate for receiving bias voltage CNBIAS, and a source connected to node 85. CNBIAS is a bias voltage sufficient to bias N-channel transistors 115 and 116 into saturation.

Differential portion 70' is similar to differential portion 70, but there are two principal differences between the two. First, in load portion 110', cascode transistors 115 and 116 increase the differential output impedance at nodes 86 and 87, while not substantially affecting low common-mode output impedance as in FIG. 2. Second, transistors 88-91, in addition to transistor 81, provide a common-mode feedback network to change the magnitude of the common-mode component of current provided into nodes 86 and 87 in response to signal V.sub.CMFB.

Amplifiers 70 and 70' enhance common-mode stability by moving the common-mode pole at nodes 86 and 87 to a frequency much greater than that of the other competing common-mode poles typically located at the output of the second amplification stage or at the output of amplifier 54. The common-mode loop of this amplifier may easily be stabilized in two ways. First, giving amplifier 54 low output impedance broadbands the pole (moves the pole frequency to a higher frequency) at its output. Second, using a Miller capacitor to provide feedback from the second terminal of resistor 51 to the output of amplifier 54 broadbands the pole at the output of output portion 100 and forces the pole at the output of amplifier 54 to become dominant.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. For example, circuitry for reducing power consumption of the amplifier during a power down mode (not shown in FIGS. 2 and 3) is commonly used and well-known. Furthermore, FIGS. 1-3 illustrate a common-mode capacitor 55 between the second terminal of resistor 51 and power supply voltage terminal V.sub.SS. In other embodiments, differential amplifiers 60 or 60' may appropriately be used when a large common-mode capacitance exists between the second terminal of resistor 51 and some other fixed-voltage terminal. Note also that different transistor types and different power supply voltages may be used. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.